Re: [Openocd-development] [PATCH 1/1] - add dsp563xx support
So you wrote this from scratch? I.e. are you the sole copyright holder? Does someone see a reason why we shouldn't commit this? It needs documentation in openocd.texi. -- Øyvind Harboe US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] [PATCH 1/1] - add dsp563xx support
Hello, So you wrote this from scratch? Yes. I.e. are you the sole copyright holder? Yes. This work is based on the freescale documentation and included examples in this documents. List of documents: AN1751.pdf AN1839.pdf AN1935.pdf AN2074.pdf APR25.pdf DSP56300FM.pdf DSP56321.pdf DSP56321RM.pdf DSP56F801-7UM.pdf Regards, Mathias Am 11.12.2009 09:14, schrieb Øyvind Harboe: So you wrote this from scratch? I.e. are you the sole copyright holder? Does someone see a reason why we shouldn't commit this? It needs documentation in openocd.texi. ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] [PATCH 1/1] - add dsp563xx support
Work on the documentation and the other things that David Zach(?) mentioned and post again. -- Øyvind Harboe US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] [PATCH 1/1] - add dsp563xx support
The Format things are changed but no work on doc. Am 11.12.2009 10:34, schrieb Øyvind Harboe: Work on the documentation and the other things that David Zach(?) mentioned and post again. ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] [PATCH 1/1] - add dsp563xx support
From: Mathias Kuester mkd...@users.sourceforge.net --- src/target/Makefile.am |6 +- src/target/dsp563xx.c | 988 src/target/dsp563xx.h | 88 src/target/dsp563xx_once.c | 122 ++ src/target/dsp563xx_once.h | 81 src/target/target.c|2 + 6 files changed, 1286 insertions(+), 1 deletions(-) create mode 100644 src/target/dsp563xx.c create mode 100644 src/target/dsp563xx.h create mode 100644 src/target/dsp563xx_once.c create mode 100644 src/target/dsp563xx_once.h diff --git a/src/target/Makefile.am b/src/target/Makefile.am index f1d4caa..df54a03 100644 --- a/src/target/Makefile.am +++ b/src/target/Makefile.am @@ -33,7 +33,9 @@ libtarget_la_SOURCES = \ $(ARMV7_SRC) \ $(ARM_MISC_SRC) \ $(MIPS32_SRC) \ - avrt.c + avrt.c \ + dsp563xx.c \ + dsp563xx_once.c TARGET_CORE_SRC = \ algorithm.c \ @@ -120,6 +122,8 @@ noinst_HEADERS = \ armv7a.h \ armv7m.h \ avrt.h \ + dsp563xx.h \ + dsp563xx_once.h \ breakpoints.h \ cortex_m3.h \ cortex_a8.h \ diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c new file mode 100644 index 000..356795e --- /dev/null +++ b/src/target/dsp563xx.c @@ -0,0 +1,988 @@ +/*** + * Copyright (C) 2009 by Mathias Kuester * + * mkd...@users.sourceforge.net * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of* + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***/ +#ifdef HAVE_CONFIG_H +#include config.h +#endif + +#include target.h +#include target_type.h +#include register.h +#include dsp563xx.h +#include dsp563xx_once.h + +#define DSP563XX_JTAG_INS_LEN 4 + +#define JTAG_STATUS_NORMAL 0x01 +#define JTAG_STATUS_STOPWAIT 0x05 +#define JTAG_STATUS_BUSY 0x09 +#define JTAG_STATUS_DEBUG 0x0d + +#define JTAG_INSTR_EXTEST 0x00 +#define JTAG_INSTR_SAMPLE_PRELOAD 0x01 +#define JTAG_INSTR_IDCODE 0x02 +#define JTAG_INSTR_CLAMP 0x03 +#define JTAG_INSTR_HIZ 0x04 +#define JTAG_INSTR_ENABLE_ONCE 0x06 +#define JTAG_INSTR_DEBUG_REQUEST 0x07 +#define JTAG_INSTR_BYPASS 0x0F + +/* forward declarations */ +int dsp563xx_target_create(struct target *target, Jim_Interp * interp); +int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target); + +int dsp563xx_arch_state(struct target *target); +int dsp563xx_poll(struct target *target); +int dsp563xx_halt(struct target *target); +int dsp563xx_resume(struct target *target, int current, uint32_t address, + int handle_breakpoints, int debug_execution); +int dsp563xx_step(struct target *target, int current, uint32_t address, + int handle_breakpoints); + +int dsp563xx_assert_reset(struct target *target); +int dsp563xx_deassert_reset(struct target *target); +int dsp563xx_soft_reset_halt(struct target *target); + +/* IR and DR functions */ +int dsp563xx_jtag_sendinstr(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out); +int dsp563xx_jtag_senddat(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out, + int len); + +int dsp563xx_read_memory_p(struct target *target, uint32_t address, uint32_t size, + uint32_t count, uint8_t * buffer); +int dsp563xx_write_memory_p(struct target *target, uint32_t address, uint32_t size, + uint32_t count, uint8_t * buffer); + +#define ASM_REG_R_R0 0x607000 +#define ASM_REG_R_R1 0x617000 +#define ASM_REG_R_R2 0x627000 +#define ASM_REG_R_R3 0x637000 +#define ASM_REG_R_R4 0x647000
Re: [Openocd-development] [PATCH 1/1] - add dsp563xx support
On Fri, Dec 11, 2009 at 11:31 AM, Mathias K. kes...@freenet.de wrote: The Format things are changed but no work on doc. Also at least one target and/or board config file would be good. -- Øyvind Harboe US toll free 1-866-980-3434 / International +47 51 63 25 00 http://www.zylin.com/zy1000.html ARM7 ARM9 ARM11 XScale Cortex JTAG debugger and flash programmer ___ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
Re: [Openocd-development] [PATCH 1/1] - add dsp563xx support
It is a custom board but should work with other configurations to. The JTAG is
a olimex ARM-USB-TINY.
I think a better target name (target struct) is dsp563xx instead of dsp56.
Am 11.12.2009 11:37, schrieb Øyvind Harboe:
On Fri, Dec 11, 2009 at 11:31 AM, Mathias K. kes...@freenet.de wrote:
The Format things are changed but no work on doc.
Also at least one target and/or board config file would be good.
interface ft2232
ft2232_device_desc Olimex OpenOCD JTAG TINY
ft2232_layout olimex-jtag
ft2232_vid_pid 0x15ba 0x0004
script dsp56321.cfg# Script for freescale DSP56321
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME dsp56321
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# this defaults to a big endian
set _ENDIAN big
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
# force an error till we get a good number
set _CPUTAPID 0x1181501d
}
# RCLK
jtag_khz 4500
jtag_nsrst_delay 100
jtag_ntrst_delay 100
#has only srst
reset_config srst_only
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x1 -expected-id
$_CPUTAPID
# the luminary variant causes a software reset rather than asserting SRST
# this stops the debug registers from being cleared
# this will be fixed in later revisions of silicon
set _TARGETNAME [format %s.cpu $_CHIPNAME]
target create $_TARGETNAME dsp56 -endian $_ENDIAN -chain-position $_TARGETNAME
# working area at base of ram
$_TARGETNAME configure -work-area-virt 0
#flash configuration
#external flash is 3x 8bit mode MBM29LV400BC
#mapped to LOW/MID/HIGH Byte of the 24bit data bus
flash bank name cfi 0x00c0 0x0008 1 3 0
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[Openocd-development] [patch 1/3] ARM: disassembly fixes for LDC/STC/MRRC/MCRR
Properly detect all of these, including the 2 variants;
and bugfix parameter display for LDC and STC.
---
src/target/arm_disassembler.c | 51 +---
1 file changed, 33 insertions(+), 18 deletions(-)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -288,8 +288,13 @@ static int evaluate_ldc_stc_mcrr_mrrc(ui
mnemonic = MRRC;
}
- snprintf(instruction-text, 128, 0x%8.8 PRIx32 \t0x%8.8
PRIx32 \t%s%s p%i, %x, r%i, r%i, c%i,
-address, opcode, mnemonic, COND(opcode),
cp_num, cp_opcode, Rd, Rn, CRm);
+ snprintf(instruction-text, 128,
+ 0x%8.8 PRIx32 \t0x%8.8 PRIx32
+ \t%s%s%s p%i, %x, r%i, r%i, c%i,
+address, opcode, mnemonic,
+ ((opcode 0xf000) == 0xf000)
+ ? 2 : COND(opcode),
+COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm);
}
else /* LDC or STC */
{
@@ -300,7 +305,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(ui
CRd = (opcode 0xf000) 12;
Rn = (opcode 0xf) 16;
- offset = (opcode 0xff);
+ offset = (opcode 0xff) 2;
/* load/store */
if (opcode 0x0010)
@@ -318,19 +323,27 @@ static int evaluate_ldc_stc_mcrr_mrrc(ui
N = (opcode 0x0040) 22;
/* addressing modes */
- if ((opcode 0x0120) == 0x0100) /* immediate offset */
- snprintf(addressing_mode, 32, [r%i, #%s0x%2.2x*4],
Rn, (U) ? : -, offset);
- else if ((opcode 0x0120) == 0x0120) /* immediate
pre-indexed */
- snprintf(addressing_mode, 32, [r%i, #%s0x%2.2x*4]!,
Rn, (U) ? : -, offset);
- else if ((opcode 0x0120) == 0x0020) /* immediate
post-indexed */
- snprintf(addressing_mode, 32, [r%i], #%s0x%2.2x*4,
Rn, (U) ? : -, offset);
+ if ((opcode 0x0120) == 0x0100) /* offset */
+ snprintf(addressing_mode, 32, [r%i, #%s%d],
+ Rn, U ? : -, offset);
+ else if ((opcode 0x0120) == 0x0120) /* pre-indexed */
+ snprintf(addressing_mode, 32, [r%i, #%s%d]!,
+ Rn, U ? : -, offset);
+ else if ((opcode 0x0120) == 0x0020) /* post-indexed */
+ snprintf(addressing_mode, 32, [r%i], #%s%d,
+ Rn, U ? : -, offset);
else if ((opcode 0x0120) == 0x) /* unindexed */
- snprintf(addressing_mode, 32, [r%i], #0x%2.2x, Rn,
offset);
+ snprintf(addressing_mode, 32, [r%i], {%d},
+ Rn, offset 2);
- snprintf(instruction-text, 128, 0x%8.8 PRIx32 \t0x%8.8
PRIx32 \t%s%s%s p%i, c%i, %s,
-address, opcode, mnemonic, ((opcode
0xf000) == 0xf000) ? COND(opcode) : 2,
-(N) ? L : ,
-cp_num, CRd, addressing_mode);
+ snprintf(instruction-text, 128, 0x%8.8 PRIx32
+ \t0x%8.8 PRIx32
+ \t%s%s%s p%i, c%i, %s,
+ address, opcode, mnemonic,
+ ((opcode 0xf000) == 0xf000)
+ ? 2 : COND(opcode),
+ (opcode (1 22)) ? L : ,
+ cp_num, CRd, addressing_mode);
}
return ERROR_OK;
@@ -1638,7 +1651,8 @@ static int evaluate_data_proc(uint32_t o
return ERROR_OK;
}
-int arm_evaluate_opcode(uint32_t opcode, uint32_t address, struct
arm_instruction *instruction)
+int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
+ struct arm_instruction *instruction)
{
/* clear fields, to avoid confusion */
memset(instruction, 0, sizeof(struct arm_instruction));
@@ -1760,7 +1774,7 @@ int arm_evaluate_opcode(uint32_t opcode,
}
/* catch opcodes with [27:25] = b110 */
- if ((opcode 0x0e00) == 0x0a00)
+ if ((opcode 0x0e00) == 0x0c00)
{
/* Coprocessor load/store and double register transfers */
return evaluate_ldc_stc_mcrr_mrrc(opcode, address, instruction);
@@ -1782,7 +1796,8 @@ int arm_evaluate_opcode(uint32_t opcode,
return evaluate_cdp_mcr_mrc(opcode, address,
instruction);
}
- LOG_ERROR(should never reach this point);
+ LOG_ERROR(ARM: should never reach this point
[Openocd-development] [patch 3/3] ARM DPM: support updating HW breakpoints
Abstract the DPM breakpoint and watchpoint data structures to
have a shared core for housekeeping.
Abstract the code updating the watchpoint registers so that it
can be used to update breakpoint registers. Then do so, when
something has set up the breakpoint state used by this code.
---
Nothing currently sets up those breakpoint registers, so this
is a NOP for the moment.
src/target/arm_dpm.c | 107 ++---
src/target/arm_dpm.h | 20 -
2 files changed, 75 insertions(+), 52 deletions(-)
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -277,6 +277,51 @@ fail:
return retval;
}
+/* Avoid needless I/O ... leave breakpoints and watchpoints alone
+ * unless they're removed, or need updating because of single-stepping
+ * or running debugger code.
+ */
+static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
+ struct dpm_bpwp *xp, int *set_p)
+{
+ int retval = ERROR_OK;
+ bool disable;
+
+ if (!set_p) {
+ if (!xp-dirty)
+ goto done;
+ xp-dirty = false;
+ /* removed or startup; we must disable it */
+ disable = true;
+ } else if (bpwp) {
+ if (!xp-dirty)
+ goto done;
+ /* disabled, but we must set it */
+ xp-dirty = disable = false;
+ *set_p = true;
+ } else {
+ if (!*set_p)
+ goto done;
+ /* set, but we must temporarily disable it */
+ xp-dirty = disable = true;
+ *set_p = false;
+ }
+
+ if (disable)
+ retval = dpm-bpwp_disable(dpm, xp-number);
+ else
+ retval = dpm-bpwp_enable(dpm, xp-number,
+ xp-address, xp-control);
+
+ if (retval != ERROR_OK)
+ LOG_ERROR(%s: can't %s HW bp/wp %d,
+ disable ? disable : enable,
+ target_name(dpm-arm-target),
+ xp-number);
+done:
+ return retval;
+}
+
/**
* Writes all modified core registers for all processor modes. In normal
* operation this is called on exit from halting debug state.
@@ -296,47 +341,22 @@ int arm_dpm_write_dirty_registers(struct
if (retval != ERROR_OK)
goto done;
+ /* enable/disable hardware breakpoints */
+ for (unsigned i = 0; i dpm-nbp; i++) {
+ struct dpm_bp *dbp = dpm-dbp + i;
+ struct breakpoint *bp = dbp-bp;
+
+ retval = dpm_maybe_update_bpwp(dpm, bpwp, dbp-bpwp,
+ bp ? bp-set : NULL);
+ }
+
/* enable/disable watchpoints */
for (unsigned i = 0; i dpm-nwp; i++) {
struct dpm_wp *dwp = dpm-dwp + i;
struct watchpoint *wp = dwp-wp;
- bool disable;
- /* Avoid needless I/O ... leave watchpoints alone
-* unless they're removed, or need updating because
-* of single-stepping or running debugger code.
-*/
- if (!wp) {
- if (!dwp-dirty)
- continue;
- dwp-dirty = false;
- /* removed or startup; we must disable it */
- disable = true;
- } else if (bpwp) {
- if (!dwp-dirty)
- continue;
- /* disabled, but we must set it */
- dwp-dirty = disable = false;
- wp-set = true;
- } else {
- if (!wp-set)
- continue;
- /* set, but we must temporarily disable it */
- dwp-dirty = disable = true;
- wp-set = false;
- }
-
- if (disable)
- retval = dpm-bpwp_disable(dpm, 16 + i);
- else
- retval = dpm-bpwp_enable(dpm, 16 + i,
- wp-address ~3, dwp-control);
-
- if (retval != ERROR_OK)
- LOG_ERROR(%s: can't %s HW watchpoint %d,
- target_name(arm-target),
- disable ? disable : enable,
- i);
+ retval = dpm_maybe_update_bpwp(dpm, bpwp, dwp-bpwp,
+ wp ? wp-set : NULL);
}
/* NOTE: writes to breakpoint and watchpoint registers might
@@ -696,8 +716,9 @@ static int dpm_watchpoint_setup(struct a
*/
dpm-dwp[index].wp = wp;
- dpm-dwp[index].control = control;
- dpm-dwp[index].dirty = true;
+ dpm-dwp[index].bpwp.address = addr ~3;
+
[Openocd-development] NAND: breakage
Hi,
looks like the NAND isn't registered at all. I use the following (incorrect)
patch to work it around FTTB.
diff --git a/src/flash/nand/tcl.c b/src/flash/nand/tcl.c
index e69882b..15426e9 100644
--- a/src/flash/nand/tcl.c
+++ b/src/flash/nand/tcl.c
@@ -580,6 +580,13 @@ static COMMAND_HELPER(create_nand_device, const char
*bank_name,
return ERROR_OK;
}
+ if (nand_devices) {
+ struct nand_device *p = nand_devices;
+ while (p p-next) p = p-next;
+ p-next = c;
+ } else
+ nand_devices = c;
+
return ERROR_OK;
}
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