Re: [Qemu-devel] [PATCH v3 1/4] iotests: add script_initialize
On 8/29/19 2:27 PM, Philippe Mathieu-Daudé wrote: > This restrict test 208 to the Linux platform, is this OK? > > The rest looks good. I forgot about that, so good catch. I don't know. We seem to already restrict a LOT of tests to the Linux platform. Does this one actually work on other platforms? Actually, I can't see any other supported oses/supported platforms calls anywhere in iotests that don't just specify Linux or leave it the default (...which is also linux.) There isn't a way to engage the old-style python unittest framework without implying Linux; you have to manually override it if so. For new tests, MOST of them specified Linux in some way or another, as you saw. So either: - 208 was an oversight, or - Many tests are accidentally limiting to Linux and could be loosened. Which is it? Dunno. Guess I'll look at the VM tests to see if I can co-opt some of that... stay tuned? --js
Re: [Qemu-devel] [PATCH v3 4/4] iotests: use python logging for iotests.log()
On 8/29/19 2:34 PM, Philippe Mathieu-Daudé wrote:
> On 8/21/19 1:52 AM, John Snow wrote:
>> We can turn logging on/off globally instead of per-function.
>>
>> Remove use_log from run_job, and use python logging to turn on
>> diffable output when we run through a script entry point.
>>
>> iotest 245 changes output order due to buffering reasons.
>> ---
>> tests/qemu-iotests/030| 4 +--
>> tests/qemu-iotests/245| 1 +
>> tests/qemu-iotests/245.out| 24 +-
>> tests/qemu-iotests/iotests.py | 47 +--
>> 4 files changed, 43 insertions(+), 33 deletions(-)
>>
>> diff --git a/tests/qemu-iotests/030 b/tests/qemu-iotests/030
>> index 1b69f318c6..a382cb430b 100755
>> --- a/tests/qemu-iotests/030
>> +++ b/tests/qemu-iotests/030
>> @@ -411,8 +411,8 @@ class TestParallelOps(iotests.QMPTestCase):
>> result = self.vm.qmp('block-job-set-speed', device='drive0',
>> speed=0)
>> self.assert_qmp(result, 'return', {})
>>
>> -self.vm.run_job(job='drive0', auto_dismiss=True, use_log=False)
>> -self.vm.run_job(job='node4', auto_dismiss=True, use_log=False)
>> +self.vm.run_job(job='drive0', auto_dismiss=True)
>> +self.vm.run_job(job='node4', auto_dismiss=True)
>> self.assert_no_active_block_jobs()
>>
>> # Test a block-stream and a block-commit job in parallel
>> diff --git a/tests/qemu-iotests/245 b/tests/qemu-iotests/245
>> index bc1ceb9792..3bc29acb33 100644
>> --- a/tests/qemu-iotests/245
>> +++ b/tests/qemu-iotests/245
>> @@ -1000,4 +1000,5 @@ class TestBlockdevReopen(iotests.QMPTestCase):
>> self.reopen(opts, {'backing': 'hd2'})
>>
>> if __name__ == '__main__':
>> +iotests.activate_logging()
>> iotests.main(supported_fmts=["qcow2"])
>
> Why not use:
>
>iotests.script_main(iotests.main, supported_fmts=['qcow2')
>
Well, that'd call iotests.execute_test twice and it'd perform setup
twice, too.
Usually, we want logging on for "script-style" tests, but we want
logging off for unittest-style ones. This test has opted to use both.
(Or more likely: just wanted to use run_job and just dealt with the
extramodal output.)
OK; we can turn on logging as we see fit.
--js
Re: [Qemu-devel] [PATCH] target/arm: Free TCG temps in trans_VMOV_64_sp()
27.08.2019. 14.20, "Peter Maydell" је написао/ла: > > The function neon_store_reg32() doesn't free the TCG temp that it > is passed, so the caller must do that. We got this right in most > places but forgot to free the TCG temps in trans_VMOV_64_sp(). > > Cc: qemu-sta...@nongnu.org > Signed-off-by: Peter Maydell > --- Hello, Peter, I am just curious if you found this by manual code inspection, or perhaps using a tool? Yours, Aleksandar > target/arm/translate-vfp.inc.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c > index 3e8ea80493b..9ae980bef63 100644 > --- a/target/arm/translate-vfp.inc.c > +++ b/target/arm/translate-vfp.inc.c > @@ -880,8 +880,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a) > /* gpreg to fpreg */ > tmp = load_reg(s, a->rt); > neon_store_reg32(tmp, a->vm); > +tcg_temp_free_i32(tmp); > tmp = load_reg(s, a->rt2); > neon_store_reg32(tmp, a->vm + 1); > +tcg_temp_free_i32(tmp); > } > > return true; > -- > 2.20.1 > >
Re: [Qemu-devel] [PATCH v3 1/4] iotests: add script_initialize
On 8/29/19 8:43 PM, John Snow wrote: > On 8/29/19 2:27 PM, Philippe Mathieu-Daudé wrote: >> This restrict test 208 to the Linux platform, is this OK? >> >> The rest looks good. > > I forgot about that, so good catch. > > I don't know. We seem to already restrict a LOT of tests to the Linux > platform. Does this one actually work on other platforms? > > Actually, I can't see any other supported oses/supported platforms calls > anywhere in iotests that don't just specify Linux or leave it the > default (...which is also linux.) > > There isn't a way to engage the old-style python unittest framework > without implying Linux; you have to manually override it if so. Then let's use: iotests.script_initialize(supported_oses=[]) and call it a day? > > For new tests, MOST of them specified Linux in some way or another, as > you saw. > > So either: > - 208 was an oversight, or > - Many tests are accidentally limiting to Linux and could be loosened. This can stay in your TODO for after this painful series. > Which is it? Dunno. Guess I'll look at the VM tests to see if I can > co-opt some of that... stay tuned? > > --js >
Re: [Qemu-devel] [PATCH v3 1/4] iotests: add script_initialize
On 8/29/19 2:58 PM, Philippe Mathieu-Daudé wrote: > On 8/29/19 8:43 PM, John Snow wrote: >> On 8/29/19 2:27 PM, Philippe Mathieu-Daudé wrote: >>> This restrict test 208 to the Linux platform, is this OK? >>> >>> The rest looks good. >> >> I forgot about that, so good catch. >> >> I don't know. We seem to already restrict a LOT of tests to the Linux >> platform. Does this one actually work on other platforms? >> >> Actually, I can't see any other supported oses/supported platforms calls >> anywhere in iotests that don't just specify Linux or leave it the >> default (...which is also linux.) >> >> There isn't a way to engage the old-style python unittest framework >> without implying Linux; you have to manually override it if so. > > Then let's use: > > iotests.script_initialize(supported_oses=[]) > > and call it a day? > *whines* The even lazier thing to do is to do more work to come up with some excuse to avoid re-spinning the series: commit bc521696607c5348fcd8a9e57b408d0ac0dbe2f8 Author: Fam Zheng Date: Sun Jan 4 09:53:52 2015 +0800 qemu-iotests: Add supported os parameter for python tests If I understand correctly, qemu-iotests never meant to be portable. We only support Linux for all the shell cases, but didn't specify it for python tests. Now add this and default all the python tests as Linux only. If we cares enough later, we can override the parameter in individual cases. I think it's only an oversight that this one test didn't specify a platform. It's certainly the only one. If someone feels strongly that other platforms are supported, let them send the patch. --js
Re: [Qemu-devel] [PATCH] target/arm: Free TCG temps in trans_VMOV_64_sp()
Aleksandar Markovic writes: > 27.08.2019. 14.20, "Peter Maydell" је написао/ла: >> >> The function neon_store_reg32() doesn't free the TCG temp that it >> is passed, so the caller must do that. We got this right in most >> places but forgot to free the TCG temps in trans_VMOV_64_sp(). >> >> Cc: qemu-sta...@nongnu.org >> Signed-off-by: Peter Maydell >> --- > > Hello, Peter, > > I am just curious if you found this by manual code inspection, or perhaps > using a tool? I'm guessing that if you run code that exercises this while built with --enable-tcg-debug then TCG's sanity checking complains about unfreed temps. > > Yours, > Aleksandar > >> target/arm/translate-vfp.inc.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/target/arm/translate-vfp.inc.c > b/target/arm/translate-vfp.inc.c >> index 3e8ea80493b..9ae980bef63 100644 >> --- a/target/arm/translate-vfp.inc.c >> +++ b/target/arm/translate-vfp.inc.c >> @@ -880,8 +880,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, > arg_VMOV_64_sp *a) >> /* gpreg to fpreg */ >> tmp = load_reg(s, a->rt); >> neon_store_reg32(tmp, a->vm); >> +tcg_temp_free_i32(tmp); >> tmp = load_reg(s, a->rt2); >> neon_store_reg32(tmp, a->vm + 1); >> +tcg_temp_free_i32(tmp); >> } >> >> return true; >> -- >> 2.20.1 >> >> -- Alex Bennée
[Qemu-devel] [Bug 1841990] [NEW] instruction 'denbcdq' misbehaving
Public bug reported: Instruction 'denbcdq' appears to have no effect. Test case attached. On ppc64le native: -- gcc -g -O -mcpu=power9 bcdcfsq.c test-denbcdq.c -o test-denbcdq $ ./test-denbcdq 0x 0x000c 0x2208 $ ./test-denbcdq 1 0x0001 0x001c 0x22080001 $ ./test-denbcdq $(seq 0 99) 0x0064 0x100c 0x22080080 -- With "qemu-ppc64le -cpu power9" -- $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq 0x 0x000c 0x000c $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq 1 0x0001 0x001c 0x001c $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq $(seq 100) 0x0064 0x100c 0x100c -- I started looking at the code, but I got confused rather quickly. Could be related to endianness? I think denbcdq arrived on the scene before little-endian was a big deal. Maybe something to do with utilizing implicit floating-point register pairs... I don't think the right data is getting to helper_denbcdq, which would point back to the gen_fprp_ptr uses in dfp-impl.inc.c (GEN_DFP_T_FPR_I32_Rc). (Maybe?) ** Affects: qemu Importance: Undecided Status: New ** Attachment added: "test case for using denbcdq" https://bugs.launchpad.net/bugs/1841990/+attachment/5285701/+files/test-denbcdq.c -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1841990 Title: instruction 'denbcdq' misbehaving Status in QEMU: New Bug description: Instruction 'denbcdq' appears to have no effect. Test case attached. On ppc64le native: -- gcc -g -O -mcpu=power9 bcdcfsq.c test-denbcdq.c -o test-denbcdq $ ./test-denbcdq 0x 0x000c 0x2208 $ ./test-denbcdq 1 0x0001 0x001c 0x22080001 $ ./test-denbcdq $(seq 0 99) 0x0064 0x100c 0x22080080 -- With "qemu-ppc64le -cpu power9" -- $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq 0x 0x000c 0x000c $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq 1 0x0001 0x001c 0x001c $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq $(seq 100) 0x0064 0x100c 0x100c -- I started looking at the code, but I got confused rather quickly. Could be related to endianness? I think denbcdq arrived on the scene before little-endian was a big deal. Maybe something to do with utilizing implicit floating-point register pairs... I don't think the right data is getting to helper_denbcdq, which would point back to the gen_fprp_ptr uses in dfp-impl.inc.c (GEN_DFP_T_FPR_I32_Rc). (Maybe?) To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1841990/+subscriptions
Re: [Qemu-devel] [PATCH 0/2] tests/acceptance: Update MIPS Malta ssh test
On Fri, Aug 02, 2019 at 05:35:56PM +0200, Aleksandar Markovic wrote: > From: Aleksandar Markovic > > This little series improves linux_ssh_mips_malta.py, both in the sense > of code organization and in the sense of quantity of executed tests. Thanks! I'm queueing it on python-next. The changes suggested by others can be implemented as follow up patches. > > Aleksandar Markovic (2): > tests/acceptance: Refactor and improve reporting in > linux_ssh_mips_malta.py > tests/acceptance: Add new test cases in linux_ssh_mips_malta.py > > tests/acceptance/linux_ssh_mips_malta.py | 81 > ++-- > 1 file changed, 66 insertions(+), 15 deletions(-) > > -- > 2.7.4 > > -- Eduardo
[Qemu-devel] [PATCH] migration: Do not re-read the clock on pre_save in case of paused guest
The clock move makes the guest knows about the paused time between the
'stop' and 'migrate' commands. This is an issue in an already-paused
VM because some side effects, like process stalls, could happen
after migration.
So, this patch checks the runstate of guest in the pre_save handler and
do not re-reads the clock in case of paused state (cold migration).
Signed-off-by: Maxiwell S. Garcia
---
hw/i386/kvm/clock.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c
index 80c133a724..2c59b6894b 100644
--- a/hw/i386/kvm/clock.c
+++ b/hw/i386/kvm/clock.c
@@ -41,6 +41,9 @@ typedef struct KVMClockState {
uint64_t clock;
bool clock_valid;
+/* whether the 'clock' value was obtained in the 'paused' state */
+bool runstate_paused;
+
/* whether machine type supports reliable KVM_GET_CLOCK */
bool mach_use_reliable_get_clock;
@@ -202,6 +205,8 @@ static void kvmclock_vm_state_change(void *opaque, int
running,
return;
}
+s->runstate_paused = runstate_check(RUN_STATE_PAUSED);
+
kvm_synchronize_all_tsc();
kvm_update_clock(s);
@@ -260,9 +265,9 @@ static int kvmclock_pre_load(void *opaque)
}
/*
- * When migrating, read the clock just before migration,
- * so that the guest clock counts during the events
- * between:
+ * When migrating a running guest, read the clock just
+ * before migration, so that the guest clock counts
+ * during the events between:
*
* * vm_stop()
* *
@@ -277,7 +282,9 @@ static int kvmclock_pre_save(void *opaque)
{
KVMClockState *s = opaque;
-kvm_update_clock(s);
+if (!s->runstate_paused) {
+kvm_update_clock(s);
+}
return 0;
}
--
2.20.1
Re: [Qemu-devel] [PATCH] migration: Do not re-read the clock on pre_save in case of paused guest
CCing Marcelo, who wrote kvm_update_clock() and
kvmclock_pre_save().
On Thu, Aug 29, 2019 at 06:07:11PM -0300, Maxiwell S. Garcia wrote:
> The clock move makes the guest knows about the paused time between the
> 'stop' and 'migrate' commands. This is an issue in an already-paused
> VM because some side effects, like process stalls, could happen
> after migration.
>
> So, this patch checks the runstate of guest in the pre_save handler and
> do not re-reads the clock in case of paused state (cold migration).
>
> Signed-off-by: Maxiwell S. Garcia
> ---
> hw/i386/kvm/clock.c | 15 +++
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c
> index 80c133a724..2c59b6894b 100644
> --- a/hw/i386/kvm/clock.c
> +++ b/hw/i386/kvm/clock.c
> @@ -41,6 +41,9 @@ typedef struct KVMClockState {
> uint64_t clock;
> bool clock_valid;
>
> +/* whether the 'clock' value was obtained in the 'paused' state */
> +bool runstate_paused;
> +
> /* whether machine type supports reliable KVM_GET_CLOCK */
> bool mach_use_reliable_get_clock;
>
> @@ -202,6 +205,8 @@ static void kvmclock_vm_state_change(void *opaque, int
> running,
> return;
> }
>
> +s->runstate_paused = runstate_check(RUN_STATE_PAUSED);
> +
> kvm_synchronize_all_tsc();
>
> kvm_update_clock(s);
> @@ -260,9 +265,9 @@ static int kvmclock_pre_load(void *opaque)
> }
>
> /*
> - * When migrating, read the clock just before migration,
> - * so that the guest clock counts during the events
> - * between:
> + * When migrating a running guest, read the clock just
> + * before migration, so that the guest clock counts
> + * during the events between:
> *
> * * vm_stop()
> * *
> @@ -277,7 +282,9 @@ static int kvmclock_pre_save(void *opaque)
> {
> KVMClockState *s = opaque;
>
> -kvm_update_clock(s);
> +if (!s->runstate_paused) {
> +kvm_update_clock(s);
> +}
>
> return 0;
> }
> --
> 2.20.1
>
--
Eduardo
Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
On Thu, Aug 29, 2019 at 5:05 AM liuzhiwei wrote: > > On 2019/8/29 上午5:34, Alistair Francis wrote: > > On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei wrote: > >> Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25 > >> Signed-off-by: liuzhiwei > >> --- > >> fpu/softfloat.c | 119 + > >> include/fpu/softfloat.h | 4 + > >> linux-user/riscv/cpu_loop.c | 8 +- > >> target/riscv/Makefile.objs | 2 +- > >> target/riscv/cpu.h |30 + > >> target/riscv/cpu_bits.h |15 + > >> target/riscv/cpu_helper.c | 7 + > >> target/riscv/csr.c |65 +- > >> target/riscv/helper.h | 354 + > >> target/riscv/insn32.decode | 374 +- > >> target/riscv/insn_trans/trans_rvv.inc.c | 484 + > >> target/riscv/translate.c| 1 + > >> target/riscv/vector_helper.c| 26563 > >> ++ > >> 13 files changed, 28017 insertions(+), 9 deletions(-) > >> create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c > >> create mode 100644 target/riscv/vector_helper.c > >> > > Hello, > > > > Thanks for the patch! > > > > As others have pointed out you will need to split the patch up into > > multiple smaller patches, otherwise it is too hard to review almost > > 30,000 lines of code. > > Hi, Alistair > > I'm so sorry for the inconvenience. It will be a patch set with a cover > letter in V2. No worries. > > > Can you also include a cover letter with your patch series describing > > how you are testing this? AFAIK vector extension support isn't in any > > compiler so I'm assuming you are handwriting the assembly or have > > toolchain patches. Either way it will help if you can share that so > > others can test your implementation. > > Yes, it's handwriting assembly. The assembler in Binutils has support > Vector extension. First define an function test_vadd_vv_8 in assembly > and then it can be called from a C program. > > The function is something like > > /* vadd.vv */ > TEST_FUNC(test_vadd_vv_8) > vsetvlit1, x0, e8, m2 > vlb.v v6, (a4) > vsb.v v6, (a3) > vsetvlit1, a0, e8, m2 > vlb.v v0, (a1) > vlb.v v2, (a2) > vadd.vv v4, v0, v2 > vsb.v v4, (a3) > ret > .size test_vadd_vv_8, .-test_vadd_vv_8 If possible it might be worth releasing the code that you are using for testing. > > It takes more time to test than to implement the instructions. Maybe > there is some better test method or some forced test cases in QEMU. > Could you give me some advice for testing? Richard's idea of risu seems like a good option. Thinking about it a bit more we are going to have other extensions in the future that will need assembly testing so setting up a test framework seems like a good idea. I am happy to help try and get this going as well. Alistair > > Best Regards, > > Zhiwei > > > Alex and Richard have kindly started the review. Once you have > > addressed their comments and split this patch up into smaller patches > > you can send a v2 and we can go from there. > > > > Once again thanks for doing this implementation for QEMU! > > > > Alistair > >
Re: [Qemu-devel] [PATCH v2 2/8] exec: Factor out core logic of check_watchpoint()
On 8/29/19 10:26 AM, Philippe Mathieu-Daudé wrote: >> -wp->hitaddr = vaddr; >> +wp->hitaddr = MAX(addr, wp->vaddr); > > When is addr > wp->vaddr? Both the watchpoint and the access are arbitrary ranges. wp:[ 1000 - 1008 ] store: [ 1002 - 1004 ] wp: [ 1004- 1008 ] store: [ 1000 - 1008 ] The old code would, for the first case, return 1002 and not the 1000 of the watch point, which seems reasonable. For the second case, we would set 1000, an address outside of the watchpoint. David's change makes sure that the address signaled is inside the watchpoint. I.e. leaving the first case unchanged and making the second set 1004. It seems very reasonable to me. r~
Re: [Qemu-devel] [PATCH for-4.2 v10 03/15] virtio-iommu: Add skeleton
On Thu, Aug 29, 2019 at 02:18:42PM +0200, Auger Eric wrote:
> Hi Peter,
>
> First of all, please forgive me for the delay.
> On 8/15/19 3:54 PM, Peter Xu wrote:
> > On Tue, Jul 30, 2019 at 07:21:25PM +0200, Eric Auger wrote:
> >> +static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
> >> +{
> >> +VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
> >> +struct virtio_iommu_req_head head;
> >> +struct virtio_iommu_req_tail tail;
> >
> > [1]
> >
> >> +VirtQueueElement *elem;
> >> +unsigned int iov_cnt;
> >> +struct iovec *iov;
> >> +size_t sz;
> >> +
> >> +for (;;) {
> >> +elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
> >> +if (!elem) {
> >> +return;
> >> +}
> >> +
> >> +if (iov_size(elem->in_sg, elem->in_num) < sizeof(tail) ||
> >> +iov_size(elem->out_sg, elem->out_num) < sizeof(head)) {
> >> +virtio_error(vdev, "virtio-iommu bad head/tail size");
> >> +virtqueue_detach_element(vq, elem, 0);
> >> +g_free(elem);
> >> +break;
> >> +}
> >> +
> >> +iov_cnt = elem->out_num;
> >> +iov = g_memdup(elem->out_sg, sizeof(struct iovec) *
> >> elem->out_num);
> >
> > Could I ask why memdup is needed here?
> Indeed I don't think it is needed and besides iov is not freed!
>
> I got inspired from hw/net/virtio-net.c. To be honest I don't get why
> the g_memdup is needed there either. The out_sg gets duplicated and
> commands work on the duplicated data and not in place.
Oh true, I found that it's because of calling of iov_discard_front().
Please have a look at 771b6ed37e3. Though it seems to me that
virtio-iommu does not truncate iovs so it should not be needed.
> >
> >> +sz = iov_to_buf(iov, iov_cnt, 0, &head, sizeof(head));
> >> +if (unlikely(sz != sizeof(head))) {
> >> +tail.status = VIRTIO_IOMMU_S_DEVERR;
> >
> > Do you need to zero the reserved bits to make sure it won't contain
> > garbage? Same question to below uses of tail.
> yes. I initialized tail.
> >
> >> +goto out;
> >> +}
> >> +qemu_mutex_lock(&s->mutex);
> >> +switch (head.type) {
> >> +case VIRTIO_IOMMU_T_ATTACH:
> >> +tail.status = virtio_iommu_handle_attach(s, iov, iov_cnt);
> >> +break;
> >> +case VIRTIO_IOMMU_T_DETACH:
> >> +tail.status = virtio_iommu_handle_detach(s, iov, iov_cnt);
> >> +break;
> >> +case VIRTIO_IOMMU_T_MAP:
> >> +tail.status = virtio_iommu_handle_map(s, iov, iov_cnt);
> >> +break;
> >> +case VIRTIO_IOMMU_T_UNMAP:
> >> +tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt);
> >> +break;
> >> +default:
> >> +tail.status = VIRTIO_IOMMU_S_UNSUPP;
> >> +}
> >> +qemu_mutex_unlock(&s->mutex);
> >> +
> >> +out:
> >> +sz = iov_from_buf(elem->in_sg, elem->in_num, 0,
> >> + &tail, sizeof(tail));
> >> +assert(sz == sizeof(tail));
> >> +
> >> +virtqueue_push(vq, elem, sizeof(tail));
> >
> > s/tail/head/ (though they are the same size)?
> That's unclear to me. Similarly when checking against virtio-net.c, the
> element is pushed back to the used ring and len is set to the size of
> the status with:
>
> /*
> * Control virtqueue data structures
> *
> * The control virtqueue expects a header in the first sg entry
> * and an ack/status response in the last entry. Data for the
> * command goes in between.
> */
I was referencing the balloon code when reading the patch, e.g.,
virtio_balloon_handle_output(). Though after I read more carefully I
see that other places are using it as you described. Now I tend to
agree with you, because virtqueue_push() who calls
virtqueue_unmap_sg() used the len to unmap in_sg[] rather than
out_sg[]. So please ignore my previous comment.
(then I'm not sure whether the usage in the balloon code was correct
now...)
> >
> >> +virtio_notify(vdev, vq);
> >> +g_free(elem);
> >> +}
> >> +}
> >
> > [...]
> >
> >> +static void virtio_iommu_set_features(VirtIODevice *vdev, uint64_t val)
> >> +{
> >> +VirtIOIOMMU *dev = VIRTIO_IOMMU(vdev);
> >> +
> >> +dev->acked_features = val;
> >> +trace_virtio_iommu_set_features(dev->acked_features);
> >> +}
> >> +
> >> +static const VMStateDescription vmstate_virtio_iommu_device = {
> >> +.name = "virtio-iommu-device",
> >> +.unmigratable = 1,
> >
> > Curious, is there explicit reason to not support migration from the
> > first version? :)
> The state is made of red black trees, lists. For the former there is no
> VMSTATE* ready. I am working on it but I think this should be handled
> separately
Fair enough. Would you mind to add a similar comment above
unmigratable?
Thanks,
--
Peter Xu
Re: [Qemu-devel] [PATCH v2 4/8] exec: Factor out cpu_watchpoint_address_matches
On 8/29/19 10:20 AM, Philippe Mathieu-Daudé wrote:
>> +/* Avoid trapping reads of pages with a write breakpoint. */
>> +match = (prot & PAGE_READ ? BP_MEM_READ : 0)
>> + | (prot & PAGE_WRITE ? BP_MEM_WRITE : 0);
>
> Isn't it cheaper to do here:
>
>if (!match) {
>return iotlb;
>}
>
> or
>
>if (match) {
Note that PROT_NONE pages never reach here; they always trap in tlb_fill.
The only way we can get match == 0 here is for the case of an execute-only
page. Which is possible, but extremely unlikely. Almost all targets merge the
text and rodata sections, which means that virtually all executable pages are
also readable.
(Although I must say that in this age of ROP-gadgets, leaving the rodata
section executable is probably a mistake, and tools should be updated to *not*
merge them. That's still not necessarily execute-only for the text section,
but I don't see anything in principal that would prevent it.)
r~
Re: [Qemu-devel] [PATCH v3 0/4] Introduce the microvm machine type
Hi Sergio, On 8/29/2019 11:46 PM, Sergio Lopez wrote: Jing Liu writes: Hi Sergio, The idea is interesting and I tried to launch a guest by your guide but seems failed to me. I tried both legacy and normal modes, but the vncviewer connected and told me that: The vm has no graphic display device. All the screen in vnc is just black. The microvm machine type doesn't support any graphics device, so you need to rely on the serial console. Got it. kernel config: CONFIG_KVM_MMIO=y CONFIG_VIRTIO_MMIO=y I don't know if any specified kernel version/patch/config is needed or anything I missed. Could you kindly give some tips? I'm testing it with upstream vanilla Linux. In addition to MMIO, you need to add support for PVH (the next version of this patchset, v4, will support booting from FW, so it'll be possible to use non-PVH ELF kernels and bzImages too). I've just uploaded a working kernel config here: https://gist.github.com/slp/1060ba3aaf708584572ad4109f28c8f9 Thanks very much and this config is helpful to me. As for the QEMU command line, something like this should do the trick: ./x86_64-softmmu/qemu-system-x86_64 -smp 1 -m 1g -enable-kvm -M microvm,legacy -kernel vmlinux -append "earlyprintk=ttyS0 console=ttyS0 reboot=k panic=1" -nodefaults -no-user-config -nographic -serial stdio If this works, you can move to non-legacy mode with a virtio-console: ./x86_64-softmmu/qemu-system-x86_64 -smp 1 -m 1g -enable-kvm -M microvm -kernel vmlinux -append "console=hvc0 reboot=k panic=1" -nodefaults -no-user-config -nographic -serial pty -chardev stdio,id=virtiocon0,server -device virtio-serial-device -device virtconsole,chardev=virtiocon0 I tried the above two ways and it works now. Thanks! If is still working, you can try adding some devices too: ./x86_64-softmmu/qemu-system-x86_64 -smp 1 -m 1g -enable-kvm -M microvm -kernel vmlinux -append "console=hvc0 reboot=k panic=1 root=/dev/vda" -nodefaults -no-user-config -nographic -serial pty -chardev stdio,id=virtiocon0,server -device virtio-serial-device -device virtconsole,chardev=virtiocon0 -netdev user,id=testnet -device virtio-net-device,netdev=testnet -drive id=test,file=alpine-rootfs-x86_64.raw,format=raw,if=none -device virtio-blk-device,drive=test But I'm wondering why the image I used can not be found. root=/dev/vda3 and the same image worked well on normal qemu/guest- config bootup, but didn't work here. The details are, -append "console=hvc0 reboot=k panic=1 root=/dev/vda3 rw rootfstype=ext4" \ [0.022784] Key type encrypted registered [0.022988] VFS: Cannot open root device "vda3" or unknown-block(254,3): error -6 [0.023041] Please append a correct "root=" boot option; here are the available partitions: [0.023089] fe00 8946688 vda [0.023090] driver: virtio_blk [0.023143] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(254,3) [0.023201] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.3.0-rc3 #23 BTW, root=/dev/vda is also tried and didn't work. The dmesg is a little different: [0.028050] Key type encrypted registered [0.028484] List of all partitions: [0.028529] fe00 8946688 vda [0.028529] driver: virtio_blk [0.028615] No filesystem could mount root, tried: [0.028616] ext4 [0.028670] [0.028712] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(254,0) I tried another ext4 img but still doesn't work. Is there any limitation of blk image? Could I copy your image for simple test? Thanks in advance, Jing Sergio. Thanks very much. Jing A QEMU instance with the microvm machine type can be invoked this way: - Normal mode: qemu-system-x86_64 -M microvm -m 512m -smp 2 \ -kernel vmlinux -append "console=hvc0 root=/dev/vda" \ -nodefaults -no-user-config \ -chardev pty,id=virtiocon0,server \ -device virtio-serial-device \ -device virtconsole,chardev=virtiocon0 \ -drive id=test,file=test.img,format=raw,if=none \ -device virtio-blk-device,drive=test \ -netdev tap,id=tap0,script=no,downscript=no \ -device virtio-net-device,netdev=tap0 - Legacy mode: qemu-system-x86_64 -M microvm,legacy -m 512m -smp 2 \ -kernel vmlinux -append "console=ttyS0 root=/dev/vda" \ -nodefaults -no-user-config \ -drive id=test,file=test.img,format=raw,if=none \ -device virtio-blk-device,drive=test \ -netdev tap,id=tap0,script=no,downscript=no \ -device virtio-net-device,netdev=tap0 \ -serial stdio
Re: [Qemu-devel] [PATCH 3/4] RFC target/arm: Do not build pre-ARMv7 cpus when using KVM
On 29/08/2019 20.19, Philippe Mathieu-Daudé wrote: > Hi Thomas, > > On 8/23/19 4:28 PM, Thomas Huth wrote: >> On 8/23/19 3:58 PM, Philippe Mathieu-Daudé wrote: >>> A KVM-only build won't be able to run pre-ARMv7 cpus, disable them. >>> >>> If KVM is not enabled, they are enabled by default. >> [...] >>> config CHEETAH >>> bool >>> +select ARM_V4 >>> select OMAP >>> select TSC210X >> >> Are you sure about the "enabled by default" ? There is not "default y" >> here, is it? > > What I mean is if you build with --disable-kvm, this selects > --enable-tcg which provides the pre-ARMv7 cpus. So to make no changes, I > also added: > > config ARM_V4 > default y > > Which include the "default y". Well, so the ARM_V4 config switch is enabled by default. But where is the CHEETAH config switch enabled now? >> I think we should maybe rather rework the default-configs directory: >> Rename the default to "config/default/" instead and then we can add >> other subfolders with such special configurations, e.g. config/nemu/ or >> config/lean-kvm/ or however you want to call it. Then add a new switch >> to the configure script to be able to use the configs from such a >> different folder. > > OK so if someone wants a special config, he'd know the config values to > select, so it is pointless/confusing to keep them commented. > Are you suggesting to simply remove the default entries? Certainly not! I meant to keep the current file (with everything enabled) in config/default/, and to add another config file to config/lean-kvm/ where the TCG-only boards are disabled. Then the user can easily run "./configure --build-config-dir=config/lean-kvm/" to enable these settings. Thomas
[Qemu-devel] [Bug 1841990] Re: instruction 'denbcdq' misbehaving
** Tags added: ppc64 testcase -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1841990 Title: instruction 'denbcdq' misbehaving Status in QEMU: New Bug description: Instruction 'denbcdq' appears to have no effect. Test case attached. On ppc64le native: -- gcc -g -O -mcpu=power9 bcdcfsq.c test-denbcdq.c -o test-denbcdq $ ./test-denbcdq 0x 0x000c 0x2208 $ ./test-denbcdq 1 0x0001 0x001c 0x22080001 $ ./test-denbcdq $(seq 0 99) 0x0064 0x100c 0x22080080 -- With "qemu-ppc64le -cpu power9" -- $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq 0x 0x000c 0x000c $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq 1 0x0001 0x001c 0x001c $ qemu-ppc64le -cpu power9 -L [...] ./test-denbcdq $(seq 100) 0x0064 0x100c 0x100c -- I started looking at the code, but I got confused rather quickly. Could be related to endianness? I think denbcdq arrived on the scene before little-endian was a big deal. Maybe something to do with utilizing implicit floating-point register pairs... I don't think the right data is getting to helper_denbcdq, which would point back to the gen_fprp_ptr uses in dfp-impl.inc.c (GEN_DFP_T_FPR_I32_Rc). (Maybe?) To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1841990/+subscriptions
[Qemu-devel] [PULL 0/3] Usb 20190829 patches
The following changes since commit 23919ddfd56135cad3cb468a8f54d5a595f024f4: Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20190827' into staging (2019-08-27 15:52:36 +0100) are available in the Git repository at: git://git.kraxel.org/qemu tags/usb-20190829-pull-request for you to fetch changes up to e4c1c64112565a9be50008e6f28dbc41b53da740: usb-mtp: add sanity checks on rootdir (2019-08-29 07:31:12 +0200) usb: bugfixes for xhci and mtp. Bandan Das (1): usb-mtp: add sanity checks on rootdir Ying Fang (1): xhci: Fix memory leak in xhci_address_slot fangying (1): xhci: Fix memory leak in xhci_kick_epctx hw/usb/dev-mtp.c | 38 -- hw/usb/hcd-xhci.c | 2 ++ 2 files changed, 26 insertions(+), 14 deletions(-) -- 2.18.1
[Qemu-devel] [PULL 2/3] xhci: Fix memory leak in xhci_kick_epctx
From: fangying
Address Sanitizer shows memory leak in xhci_kick_epctx hw/usb/hcd-xhci.c:1912.
A sglist is leaked when a packet is retired and returns USB_RET_NAK status.
The leak stack is as bellow:
Direct leak of 2688 byte(s) in 168 object(s) allocated from:
#0 0xae8b11db in __interceptor_malloc (/lib64/libasan.so.4+0xd31db)
#1 0xae5c9163 in g_malloc (/lib64/libglib-2.0.so.0+0x57163)
#2 0xbb6fb3f7 in qemu_sglist_init dma-helpers.c:43
#3 0xbba705a7 in pci_dma_sglist_init include/hw/pci/pci.h:837
#4 0xbba705a7 in xhci_xfer_create_sgl hw/usb/hcd-xhci.c:1443
#5 0xbba705a7 in xhci_setup_packet hw/usb/hcd-xhci.c:1615
#6 0xbba77a6f in xhci_kick_epctx hw/usb/hcd-xhci.c:1912
#7 0xbbdaad27 in timerlist_run_timers util/qemu-timer.c:592
#8 0xbbdab19f in qemu_clock_run_timers util/qemu-timer.c:606
#9 0xbbdab19f in qemu_clock_run_all_timers util/qemu-timer.c:692
#10 0xbbdab9a3 in main_loop_wait util/main-loop.c:524
#11 0xbb6ff5e7 in main_loop vl.c:1806
#12 0xbb1e1453 in main vl.c:4488
Signed-off-by: Ying Fang
Message-id: 20190828062535.1573-1-fangyi...@huawei.com
Signed-off-by: Gerd Hoffmann
---
hw/usb/hcd-xhci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index 471759cd4cc0..80988bb305a1 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -1914,6 +1914,7 @@ static void xhci_kick_epctx(XHCIEPContext *epctx,
unsigned int streamid)
}
usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
if (xfer->packet.status == USB_RET_NAK) {
+xhci_xfer_unmap(xfer);
return;
}
xhci_try_complete_packet(xfer);
--
2.18.1
[Qemu-devel] [PULL 3/3] usb-mtp: add sanity checks on rootdir
From: Bandan Das
Currently, we don't check if rootdir exists and is accessible.
Furthermore, a trailing slash results in a null "desc" string which
ends up in the share not visible in the guest. Add some simple
sanity checks for appropriate permissions. Also, bail out if the
user does not supply an absolute path.
Signed-off-by: Bandan Das
Message-id: jpga7bto3on@linux.bootlegged.copy
Signed-off-by: Gerd Hoffmann
---
hw/usb/dev-mtp.c | 38 --
1 file changed, 24 insertions(+), 14 deletions(-)
diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c
index 9846e4b5130b..7c07295519d3 100644
--- a/hw/usb/dev-mtp.c
+++ b/hw/usb/dev-mtp.c
@@ -2038,26 +2038,36 @@ static void usb_mtp_realize(USBDevice *dev, Error
**errp)
{
MTPState *s = USB_MTP(dev);
-usb_desc_create_serial(dev);
-usb_desc_init(dev);
-QTAILQ_INIT(&s->objects);
-if (s->desc == NULL) {
-if (s->root == NULL) {
-error_setg(errp, "usb-mtp: rootdir property must be configured");
-return;
-}
-s->desc = strrchr(s->root, '/');
-if (s->desc && s->desc[0]) {
-s->desc = g_strdup(s->desc + 1);
-} else {
-s->desc = g_strdup("none");
-}
+if ((s->root == NULL) || !g_path_is_absolute(s->root)) {
+error_setg(errp, "usb-mtp: rootdir must be configured and be an
absolute path");
+return;
}
+
+if (access(s->root, R_OK) != 0) {
+error_setg(errp, "usb-mtp: rootdir does not exist/not readable");
+return;
+} else if (!s->readonly && access(s->root, W_OK) != 0) {
+error_setg(errp, "usb-mtp: rootdir does not have write permissions");
+return;
+}
+
/* Mark store as RW */
if (!s->readonly) {
s->flags |= (1 << MTP_FLAG_WRITABLE);
}
+if (s->desc == NULL) {
+/*
+ * This does not check if path exists
+ * but we have the checks above
+ */
+s->desc = g_path_get_basename(s->root);
+}
+
+usb_desc_create_serial(dev);
+usb_desc_init(dev);
+QTAILQ_INIT(&s->objects);
+
}
static const VMStateDescription vmstate_usb_mtp = {
--
2.18.1
[Qemu-devel] [PULL 1/3] xhci: Fix memory leak in xhci_address_slot
From: Ying Fang Address Sanitizer shows memory leak in xhci_address_slot hw/usb/hcd-xhci.c:2156 and the stack is as bellow: Direct leak of 64 byte(s) in 4 object(s) allocated from: #0 0x91c6f5ab in realloc (/lib64/libasan.so.4+0xd35ab) #1 0x91987243 in g_realloc (/lib64/libglib-2.0.so.0+0x57243) #2 0xb0b26a1f in qemu_iovec_add util/iov.c:296 #3 0xb07e5ce3 in xhci_address_slot hw/usb/hcd-xhci.c:2156 #4 0xb07e5ce3 in xhci_process_commands hw/usb/hcd-xhci.c:2493 #5 0xb00058d7 in memory_region_write_accessor qemu/memory.c:507 #6 0xbd87 in access_with_adjusted_size memory.c:573 #7 0xb000abcf in memory_region_dispatch_write memory.c:1516 #8 0xaff59947 in flatview_write_continue exec.c:3367 #9 0xaff59c33 in flatview_write exec.c:3406 #10 0xaff63b3b in address_space_write exec.c:3496 #11 0xb002f263 in kvm_cpu_exec accel/kvm/kvm-all.c:2288 #12 0xaffee427 in qemu_kvm_cpu_thread_fn cpus.c:1290 #13 0xb0b1a943 in qemu_thread_start util/qemu-thread-posix.c:502 #14 0x908ce8bb in start_thread (/lib64/libpthread.so.0+0x78bb) #15 0x908165cb in thread_start (/lib64/libc.so.6+0xd55cb) Cc: zhanghailiang Signed-off-by: Ying Fang Reviewed-by: Li Qiang Message-id: 20190827080209.2365-1-fangyi...@huawei.com Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index f5782649482b..471759cd4cc0 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -2161,6 +2161,7 @@ static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, DeviceOutRequest | USB_REQ_SET_ADDRESS, slotid, 0, 0, NULL); assert(p.status != USB_RET_ASYNC); +usb_packet_cleanup(&p); } res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); -- 2.18.1
Re: [Qemu-devel] [PATCH] target/arm: Fix SMMLS argument order
Hi,
On Thu, Aug 29, 2019 at 3:33 AM Richard Henderson
wrote:
>
> The previous simplification got the order of operands to the
> subtraction wrong. Since the 64-bit product is the subtrahend,
> we must use a 64-bit subtract to properly compute the borrow
> from the low-part of the product.
>
> Fixes: 5f8cd06ebcf5 ("target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR")
> Reported-by: Laurent Desnogues
> Signed-off-by: Richard Henderson
Tested-by: Laurent Desnogues
Thanks,
Laurent
> ---
> target/arm/translate.c | 20 ++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index cbe19b7a62..a0f7577f47 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -8824,7 +8824,16 @@ static void disas_arm_insn(DisasContext *s, unsigned
> int insn)
> if (rd != 15) {
> tmp3 = load_reg(s, rd);
> if (insn & (1 << 6)) {
> -tcg_gen_sub_i32(tmp, tmp, tmp3);
> +/*
> + * For SMMLS, we need a 64-bit subtract.
> + * Borrow caused by a non-zero multiplicand
> + * lowpart, and the correct result lowpart
> + * for rounding.
> + */
> +TCGv_i32 zero = tcg_const_i32(0);
> +tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3,
> + tmp2, tmp);
> +tcg_temp_free_i32(zero);
> } else {
> tcg_gen_add_i32(tmp, tmp, tmp3);
> }
> @@ -10068,7 +10077,14 @@ static void disas_thumb2_insn(DisasContext *s,
> uint32_t insn)
> if (insn & (1 << 20)) {
> tcg_gen_add_i32(tmp, tmp, tmp3);
> } else {
> -tcg_gen_sub_i32(tmp, tmp, tmp3);
> +/*
> + * For SMMLS, we need a 64-bit subtract.
> + * Borrow caused by a non-zero multiplicand lowpart,
> + * and the correct result lowpart for rounding.
> + */
> +TCGv_i32 zero = tcg_const_i32(0);
> +tcg_gen_sub2_i32(tmp2, tmp, zero, tmp3, tmp2, tmp);
> +tcg_temp_free_i32(zero);
> }
> tcg_temp_free_i32(tmp3);
> }
> --
> 2.17.1
>
Re: [Qemu-devel] [RFC 2/3] intc/arm_gic: Support PPI injection for more than 256 vpus
Hi Zenghui,
On 8/29/19 4:53 AM, Zenghui Yu wrote:
> Hi Eric,
>
> On 2019/8/28 0:05, Eric Auger wrote:
>> Host kernels that expose the KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 capability
>> allow injection of PPIs along with vcpu ids larger than 255. Let's
>> encode the vpcu id on 12 bits according to the upgraded KVM_IRQ_LINE
>> ABI when needed.
>>
>> Without that patch qemu exits with "kvm_set_irq: Invalid argument"
>> message.
>>
>> Signed-off-by: Eric Auger
>> Reported-by: Zenghui Yu
>> ---
>> hw/intc/arm_gic_kvm.c | 10 +++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
>> index b56fda144f..889293e97f 100644
>> --- a/hw/intc/arm_gic_kvm.c
>> +++ b/hw/intc/arm_gic_kvm.c
>> @@ -56,6 +56,7 @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int irq,
>> int level)
>> * CPU number and interrupt number.
>> */
>> int kvm_irq, irqtype, cpu;
>> + int cpu_idx1 = 0, cpu_idx2 = 0;
>> if (irq < (num_irq - GIC_INTERNAL)) {
>> /* External interrupt. The kernel numbers these like the GIC
>> @@ -63,17 +64,20 @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int
>> irq, int level)
>> * internal ones.
>> */
>> irqtype = KVM_ARM_IRQ_TYPE_SPI;
>> - cpu = 0;
>> irq += GIC_INTERNAL;
>> } else {
>> /* Internal interrupt: decode into (cpu, interrupt id) */
>> irqtype = KVM_ARM_IRQ_TYPE_PPI;
>> irq -= (num_irq - GIC_INTERNAL);
>> cpu = irq / GIC_INTERNAL;
>> + cpu_idx2 = cpu / 256;
>> + cpu_idx1 = cpu % 256;
>> irq %= GIC_INTERNAL;
>> }
>> - kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT)
>> - | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq;
>> + kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) |
>> + (cpu_idx1 << KVM_ARM_IRQ_VCPU_SHIFT) |
>> + ((cpu_idx2 & KVM_ARM_IRQ_VCPU2_MASK) <<
>> KVM_ARM_IRQ_VCPU2_SHIFT) |
>> + irq;
>> kvm_set_irq(kvm_state, kvm_irq, !!level);
>> }
>>
>
> For confirmation, should we also adjust the vcpu_index in
> arm_cpu_kvm_set_irq(), just like above?
I am not familiar with this path. in arm_cpu_initfn(), there is a
comment saying "VIRQ and VFIQ are unused with KVM but we add them to
maintain the same interface as non-KVM CPUs." So I don't know when that
code gets executed.
But maybe it would be more cautious to implement your suggestion here as
well.
Maybe Peter can provide more info here?
Thanks
Eric
>
>
> Thanks,
> zenghui
>
>
Re: [Qemu-devel] [PATCH RFC 0/4] intel_iommu: Do sanity check of vfio-pci earlier
Hi Peter, On 8/29/19 3:18 AM, Peter Xu wrote: > On Wed, Aug 28, 2019 at 02:59:45PM +0200, Auger Eric wrote: >> Hi Peter, > > Hi, Eric, > > [...] > >> In >> [PATCH v4 2/5] memory: Add IOMMU_ATTR_HW_NESTED_PAGING IOMMU memory >> region attribute (https://patchwork.kernel.org/patch/11109701/) > > [1] > >> >> [PATCH v4 3/5] hw/vfio/common: Fail on VFIO/HW nested paging detection >> (https://patchwork.kernel.org/patch/11109697/) >> >> I proposed to introduce a new IOMMU MR attribute to retrieve whether the >> vIOMMU uses HW nested paging to integrate with VFIO. I wonder whether >> this kind of solution would fit your need too. >> >> Assuming we would rename the attribute (whose name is challenged by >> Peter anyway) into something like IOMMU_ATTR_PHYS_MAP_MODE >> taking the possible values: NONE, CM, HW_NESTED_PAGING. SMMUv3 would >> return HW_NESTED_PAGING, Intel IOMMU would return CM if CM is enabled or >> NONE in the negative. Then we could implement the check directly in VFIO >> common.c. That way I don't think you would need the new notifiers and >> this would satisfy both requirements? > > IMHO it'll suffer from the similar issue we have now with > flag_changed, because at the very beginning of x86 system boots DMAR > is not yet enabled, the intel-iommu device is using the same mode as > its passthrough mode so there's no IOMMU memory region at all in the > DMA address spaces of the devices. Ah OK I did not get this initially. We don't have this issue with SMMUv3 as the IOMMU MR exists from the very beginning and does not depend on its enablement by the guest. Also it stays there. So the detection can be made immediatly. Hence even with patch [1] above we > still can't really reach the get_attr() check until DMAR enabled? > > Maybe we can figure out a good way to expose IOMMU attributes rather > than the IOMMU memory region attributes then we let vfio to pick that > up, but I'm not very sure whether that's clean enough. > > Thanks, > Thanks Eric
Re: [Qemu-devel] [PATCH v2 5/7] mips/tcg: Call probe_write() for CONFIG_USER_ONLY as well
26.08.2019. 09.52, "David Hildenbrand" је написао/ла:
>
> Let's call it also for CONFIG_USER_ONLY. While at it, add a FIXME and get
> rid of one local variable.
>
> MIPS code probably needs a bigger refactoring in regards of
> ensure_writable_pages(), similar to s390x, so for example, watchpoints
> can be handled reliably later. The actually accessed addresses should
> be probed only, not full pages.
>
> Signed-off-by: David Hildenbrand
> ---
Reviewed-by: Aleksandar Markovic
> target/mips/op_helper.c | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
> index 34bcc8d884..08d9a4f9f1 100644
> --- a/target/mips/op_helper.c
> +++ b/target/mips/op_helper.c
> @@ -4537,16 +4537,14 @@ static inline void
ensure_writable_pages(CPUMIPSState *env,
> int mmu_idx,
> uintptr_t retaddr)
> {
> -#if !defined(CONFIG_USER_ONLY)
> -target_ulong page_addr;
> +/* FIXME: Probe the actual accesses (pass and use a size) */
> if (unlikely(MSA_PAGESPAN(addr))) {
> /* first page */
> probe_write(env, addr, 0, mmu_idx, retaddr);
> /* second page */
> -page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> -probe_write(env, page_addr, 0, mmu_idx, retaddr);
> +addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> +probe_write(env, addr, 0, mmu_idx, retaddr);
> }
> -#endif
> }
>
> void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
> --
> 2.21.0
>
>
Re: [Qemu-devel] [PATCH RFC 0/4] intel_iommu: Do sanity check of vfio-pci earlier
On Thu, Aug 29, 2019 at 10:05:27AM +0200, Auger Eric wrote: > Hi Peter, Hi, Eric, > On 8/29/19 3:18 AM, Peter Xu wrote: > > On Wed, Aug 28, 2019 at 02:59:45PM +0200, Auger Eric wrote: > >> Hi Peter, > > > > Hi, Eric, > > > > [...] > > > >> In > >> [PATCH v4 2/5] memory: Add IOMMU_ATTR_HW_NESTED_PAGING IOMMU memory > >> region attribute (https://patchwork.kernel.org/patch/11109701/) > > > > [1] > > > >> > >> [PATCH v4 3/5] hw/vfio/common: Fail on VFIO/HW nested paging detection > >> (https://patchwork.kernel.org/patch/11109697/) > >> > >> I proposed to introduce a new IOMMU MR attribute to retrieve whether the > >> vIOMMU uses HW nested paging to integrate with VFIO. I wonder whether > >> this kind of solution would fit your need too. > >> > >> Assuming we would rename the attribute (whose name is challenged by > >> Peter anyway) into something like IOMMU_ATTR_PHYS_MAP_MODE > >> taking the possible values: NONE, CM, HW_NESTED_PAGING. SMMUv3 would > >> return HW_NESTED_PAGING, Intel IOMMU would return CM if CM is enabled or > >> NONE in the negative. Then we could implement the check directly in VFIO > >> common.c. That way I don't think you would need the new notifiers and > >> this would satisfy both requirements? > > > > IMHO it'll suffer from the similar issue we have now with > > flag_changed, because at the very beginning of x86 system boots DMAR > > is not yet enabled, the intel-iommu device is using the same mode as > > its passthrough mode so there's no IOMMU memory region at all in the > > DMA address spaces of the devices. > > Ah OK I did not get this initially. We don't have this issue with SMMUv3 > as the IOMMU MR exists from the very beginning and does not depend on > its enablement by the guest. Also it stays there. So the detection can > be made immediatly. True. With that, I'm a bit curious on whether ARM should implement something like PT mode of Intel's. For example, have you tried to run a ARM guest with both a vSMMU and a vfio-pci inside, however keep DMAR disabled? IIUC in that case there will be no mapping at all for the assigned device, then would that work? Or is there any magic for ARM? Regards, -- Peter Xu
Re: [Qemu-devel] [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space configurable
On Thu, 15 Aug 2019 08:42:48 +
Shameerali Kolothum Thodi wrote:
> > -Original Message-
> > From: Linuxarm [mailto:linuxarm-boun...@huawei.com] On Behalf Of Shameer
> > Kolothum
> > Sent: 13 August 2019 22:05
> > To: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> > eric.au...@redhat.com; imamm...@redhat.com
> > Cc: peter.mayd...@linaro.org; sa...@linux.intel.com;
> > ard.biesheu...@linaro.org; Linuxarm ;
> > shannon.zha...@gmail.com; sebastien.bo...@intel.com; ler...@redhat.com
> > Subject: [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space
> > configurable
> >
> > This is in preparation for adding support for ARM64 platforms
> > where it doesn't use port mapped IO for ACPI IO space. We are
> > making changes so that MMIO region can be accommodated
> > and board can pass the base address into the aml build function.
>
> Looks like, this now breaks the "make check" on x86_64 and needs
> updating bios-tables-test-allowed-diff.h with DSDT entries. But I am
> not sure what changed now compared to v8(and older ones) that makes
> it to complain now!.
you could see diff of what's changed but running test manually with
V=1 env var if you have 'iasl' installed
V=1 QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64 tests/bios-tables-test
> Patchew URL:
> https://patchew.org/QEMU/20190813210539.31164-1-shameerali.kolothum.th...@huawei.com/
>
> ERROR:/tmp/qemu-test/src/tests/bios-tables-test.c:447:test_acpi_asl:
> assertion failed: (all_tables_match)
>
> Thanks,
> Shameer
>
> > Also move few MEMORY_* definitions to header so that other memory
> > hotplug event signalling mechanisms (eg. Generic Event Device on
> > HW-reduced acpi platforms) can use the same from their respective
> > event handler code.
> >
> > Signed-off-by: Shameer Kolothum
> > ---
> > v8 --> v9
> > -base address is an input into build_memory_hotplug_aml()
> > -Removed R-by tags from Igor and Eric for now.
> > ---
> > hw/acpi/memory_hotplug.c | 29 ++---
> > hw/i386/acpi-build.c | 4 +++-
> > hw/i386/pc.c | 3 +++
> > include/hw/acpi/memory_hotplug.h | 9 +++--
> > include/hw/i386/pc.h | 3 +++
> > 5 files changed, 30 insertions(+), 18 deletions(-)
> >
> > diff --git a/hw/acpi/memory_hotplug.c b/hw/acpi/memory_hotplug.c
> > index 297812d5f7..1734d4b44f 100644
> > --- a/hw/acpi/memory_hotplug.c
> > +++ b/hw/acpi/memory_hotplug.c
> > @@ -29,12 +29,7 @@
> > #define MEMORY_SLOT_PROXIMITY_METHOD "MPXM"
> > #define MEMORY_SLOT_EJECT_METHOD "MEJ0"
> > #define MEMORY_SLOT_NOTIFY_METHOD"MTFY"
> > -#define MEMORY_SLOT_SCAN_METHOD "MSCN"
> > #define MEMORY_HOTPLUG_DEVICE"MHPD"
> > -#define MEMORY_HOTPLUG_IO_LEN 24
> > -#define MEMORY_DEVICES_CONTAINER "\\_SB.MHPC"
> > -
> > -static uint16_t memhp_io_base;
> >
> > static ACPIOSTInfo *acpi_memory_device_status(int slot, MemStatus *mdev)
> > {
> > @@ -209,7 +204,7 @@ static const MemoryRegionOps
> > acpi_memory_hotplug_ops = {
> > };
> >
> > void acpi_memory_hotplug_init(MemoryRegion *as, Object *owner,
> > - MemHotplugState *state, uint16_t
> > io_base)
> > + MemHotplugState *state, hwaddr
> > io_base)
> > {
> > MachineState *machine = MACHINE(qdev_get_machine());
> >
> > @@ -218,12 +213,10 @@ void acpi_memory_hotplug_init(MemoryRegion *as,
> > Object *owner,
> > return;
> > }
> >
> > -assert(!memhp_io_base);
> > -memhp_io_base = io_base;
> > state->devs = g_malloc0(sizeof(*state->devs) * state->dev_count);
> > memory_region_init_io(&state->io, owner, &acpi_memory_hotplug_ops,
> > state,
> >"acpi-mem-hotplug",
> > MEMORY_HOTPLUG_IO_LEN);
> > -memory_region_add_subregion(as, memhp_io_base, &state->io);
> > +memory_region_add_subregion(as, io_base, &state->io);
> > }
> >
> > /**
> > @@ -342,7 +335,8 @@ const VMStateDescription vmstate_memory_hotplug
> > = {
> >
> > void build_memory_hotplug_aml(Aml *table, uint32_t nr_mem,
> >const char *res_root,
> > - const char *event_handler_method)
> > + const char *event_handler_method,
> > + AmlRegionSpace rs, hwaddr
> > memhp_io_base)
> > {
> > int i;
> > Aml *ifctx;
> > @@ -365,14 +359,19 @@ void build_memory_hotplug_aml(Aml *table,
> > uint32_t nr_mem,
> > aml_name_decl("_UID", aml_string("Memory hotplug
> > resources")));
> >
> > crs = aml_resource_template();
> > -aml_append(crs,
> > -aml_io(AML_DECODE16, memhp_io_base, memhp_io_base, 0,
> > - MEMORY_HOTPLUG_IO_LEN)
> > -);
> > +if (rs == AML_SYSTEM_IO) {
> > +aml_append(crs,
> > +aml_io(AML_DECODE16, memhp_io_base,
> > memhp_io_base, 0,
> > + MEMORY_HOTPLUG_IO_
Re: [Qemu-devel] [PATCH RFC 0/4] intel_iommu: Do sanity check of vfio-pci earlier
Hi Peter, On 8/29/19 10:21 AM, Peter Xu wrote: > On Thu, Aug 29, 2019 at 10:05:27AM +0200, Auger Eric wrote: >> Hi Peter, > > Hi, Eric, > >> On 8/29/19 3:18 AM, Peter Xu wrote: >>> On Wed, Aug 28, 2019 at 02:59:45PM +0200, Auger Eric wrote: Hi Peter, >>> >>> Hi, Eric, >>> >>> [...] >>> In [PATCH v4 2/5] memory: Add IOMMU_ATTR_HW_NESTED_PAGING IOMMU memory region attribute (https://patchwork.kernel.org/patch/11109701/) >>> >>> [1] >>> [PATCH v4 3/5] hw/vfio/common: Fail on VFIO/HW nested paging detection (https://patchwork.kernel.org/patch/11109697/) I proposed to introduce a new IOMMU MR attribute to retrieve whether the vIOMMU uses HW nested paging to integrate with VFIO. I wonder whether this kind of solution would fit your need too. Assuming we would rename the attribute (whose name is challenged by Peter anyway) into something like IOMMU_ATTR_PHYS_MAP_MODE taking the possible values: NONE, CM, HW_NESTED_PAGING. SMMUv3 would return HW_NESTED_PAGING, Intel IOMMU would return CM if CM is enabled or NONE in the negative. Then we could implement the check directly in VFIO common.c. That way I don't think you would need the new notifiers and this would satisfy both requirements? >>> >>> IMHO it'll suffer from the similar issue we have now with >>> flag_changed, because at the very beginning of x86 system boots DMAR >>> is not yet enabled, the intel-iommu device is using the same mode as >>> its passthrough mode so there's no IOMMU memory region at all in the >>> DMA address spaces of the devices. >> >> Ah OK I did not get this initially. We don't have this issue with SMMUv3 >> as the IOMMU MR exists from the very beginning and does not depend on >> its enablement by the guest. Also it stays there. So the detection can >> be made immediatly. > > True. With that, I'm a bit curious on whether ARM should implement > something like PT mode of Intel's. For example, have you tried to run > a ARM guest with both a vSMMU and a vfio-pci inside, however keep DMAR > disabled? IIUC in that case there will be no mapping at all for the > assigned device, then would that work? Or is there any magic for ARM? If I understand correctly PT mode is a bypass mode. With the ARM SMMUv3 the IOMMU MR translate() function gets called but implements a direct mapping. I understand that on your side, you destroy the IOMMU MR, right? At the moment since SMMUv3/VFIO integration is not ready I plan to forbid any usage of VFIO along with SMMUv3, whatever the enable state. When HW nested paging gets ready, the stage1 bypass state will be propagated to the HW config structure. Hope I answer your question. Thanks Eric > > Regards, >
Re: [Qemu-devel] [PATCH RFC 0/4] intel_iommu: Do sanity check of vfio-pci earlier
On Thu, Aug 29, 2019 at 10:46:42AM +0200, Auger Eric wrote: > If I understand correctly PT mode is a bypass mode. With the ARM SMMUv3 > the IOMMU MR translate() function gets called but implements a direct > mapping. I understand that on your side, you destroy the IOMMU MR, right? > > At the moment since SMMUv3/VFIO integration is not ready I plan to > forbid any usage of VFIO along with SMMUv3, whatever the enable state. > > When HW nested paging gets ready, the stage1 bypass state will be > propagated to the HW config structure. > > Hope I answer your question. Yes, nested page tables will be fine. :) Thanks, -- Peter Xu
[Qemu-devel] [RFC Patch] xen/pt: Emulate FLR capability
Currently, for a HVM on Xen, no reset method is virtualized. So in a VM's
perspective, assigned devices cannot be reset. But some devices rely on PCI
reset to recover from hardware hangs. When being assigned to a VM, those
devices cannot be reset and won't work any longer if a hardware hang occurs.
We have to reboot VM to trigger PCI reset on host to recover the device.
This patch exposes FLR capability to VMs if the assigned device can be reset on
host. When VM initiates an FLR to a device, qemu cleans up the device state,
(including disabling of intx and/or MSI and unmapping BARs from guest, deleting
emulated registers), then initiate PCI reset through 'reset' knob under the
device's sysfs, finally initialize the device again.
Signed-off-by: Chao Gao
---
Do we need to introduce an attribute, like "permissive" to explicitly
enable FLR capability emulation? During PCI reset, interrupts and BARs are
unmapped from the guest. It seems that guest cannot interact with the device
directly except access to device's configuration space which is emulated by
qemu. If proper method can be used to prevent qemu accessing the physical
device there is no new security hole caused by the FLR emulation.
VM's FLR may be backed by any reset function on host to the physical device,
for example: FLR, D3softreset, secondary bus reset. Not sure it is fine to mix
them. Given Linux kernel just uses an unified API to reset device and caller
cannot choose a specific one, it might be OK.
---
hw/xen/xen-host-pci-device.c | 30 ++
hw/xen/xen-host-pci-device.h | 3 +++
hw/xen/xen_pt.c | 9 +
hw/xen/xen_pt.h | 1 +
hw/xen/xen_pt_config_init.c | 30 +++---
5 files changed, 70 insertions(+), 3 deletions(-)
diff --git a/hw/xen/xen-host-pci-device.c b/hw/xen/xen-host-pci-device.c
index 1b44dcafaf..d549656f42 100644
--- a/hw/xen/xen-host-pci-device.c
+++ b/hw/xen/xen-host-pci-device.c
@@ -198,6 +198,35 @@ static bool xen_host_pci_dev_is_virtfn(XenHostPCIDevice *d)
return !stat(path, &buf);
}
+static bool xen_host_pci_resetable(XenHostPCIDevice *d)
+{
+char path[PATH_MAX];
+
+xen_host_pci_sysfs_path(d, "reset", path, sizeof(path));
+
+return !access(path, W_OK);
+}
+
+void xen_host_pci_reset(XenHostPCIDevice *d)
+{
+char path[PATH_MAX];
+int fd;
+
+xen_host_pci_sysfs_path(d, "reset", path, sizeof(path));
+
+fd = open(path, O_WRONLY);
+if (fd == -1) {
+XEN_HOST_PCI_LOG("Xen host pci reset: open error\n");
+return;
+}
+
+if (write(fd, "1", 1) != 1) {
+XEN_HOST_PCI_LOG("Xen host pci reset: write error\n");
+}
+
+return;
+}
+
static void xen_host_pci_config_open(XenHostPCIDevice *d, Error **errp)
{
char path[PATH_MAX];
@@ -377,6 +406,7 @@ void xen_host_pci_device_get(XenHostPCIDevice *d, uint16_t
domain,
d->class_code = v;
d->is_virtfn = xen_host_pci_dev_is_virtfn(d);
+d->is_resetable = xen_host_pci_resetable(d);
return;
diff --git a/hw/xen/xen-host-pci-device.h b/hw/xen/xen-host-pci-device.h
index 4d8d34ecb0..cacf9b3df8 100644
--- a/hw/xen/xen-host-pci-device.h
+++ b/hw/xen/xen-host-pci-device.h
@@ -32,6 +32,7 @@ typedef struct XenHostPCIDevice {
XenHostPCIIORegion rom;
bool is_virtfn;
+bool is_resetable;
int config_fd;
} XenHostPCIDevice;
@@ -55,4 +56,6 @@ int xen_host_pci_set_block(XenHostPCIDevice *d, int pos,
uint8_t *buf,
int xen_host_pci_find_ext_cap_offset(XenHostPCIDevice *s, uint32_t cap);
+void xen_host_pci_reset(XenHostPCIDevice *d);
+
#endif /* XEN_HOST_PCI_DEVICE_H */
diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c
index 8fbaf2eae9..d750367c0a 100644
--- a/hw/xen/xen_pt.c
+++ b/hw/xen/xen_pt.c
@@ -938,6 +938,15 @@ static void xen_pt_unregister_device(PCIDevice *d)
xen_pt_destroy(d);
}
+void xen_pt_reset(XenPCIPassthroughState *s)
+{
+PCIDevice *d = PCI_DEVICE(s);
+
+xen_pt_unregister_device(d);
+xen_host_pci_reset(&s->real_device);
+xen_pt_realize(d, NULL);
+}
+
static Property xen_pci_passthrough_properties[] = {
DEFINE_PROP_PCI_HOST_DEVADDR("hostaddr", XenPCIPassthroughState, hostaddr),
DEFINE_PROP_BOOL("permissive", XenPCIPassthroughState, permissive, false),
diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h
index 9167bbaf6d..ed05bc0d39 100644
--- a/hw/xen/xen_pt.h
+++ b/hw/xen/xen_pt.h
@@ -332,4 +332,5 @@ int xen_pt_register_vga_regions(XenHostPCIDevice *dev);
int xen_pt_unregister_vga_regions(XenHostPCIDevice *dev);
void xen_pt_setup_vga(XenPCIPassthroughState *s, XenHostPCIDevice *dev,
Error **errp);
+void xen_pt_reset(XenPCIPassthroughState *s);
#endif /* XEN_PT_H */
diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
index 31ec5add1d..435abd7286 100644
--- a/hw/xen/xen_pt_config_init.c
+++ b/hw/xen/xen_pt_config_init.c
@@ -852,6 +852,30 @@ static inline uint8_t
get_device_type(XenPCIPassthroughState *s,
return (
[Qemu-devel] [PATCH v5 1/2] memory: Add IOMMU_ATTR_NEED_HW_NESTED_PAGING IOMMU memory region attribute
We introduce a new IOMMU Memory Region attribute,
IOMMU_ATTR_NEED_HW_NESTED_PAGING that tells whether the
virtual IOMMU relies on physical IOMMU HW nested paging
capability when protecting host assigned devices.
Current Intel virtual IOMMU device supports "Caching
Mode" and does not require 2 stages at physical level to be
integrated with VFIO. However SMMUv3 does not implement such
"caching mode" and requires HW nested paging.
As such SMMUv3 is the first IOMMU device to advertise this
attribute.
This new attribute will allow the VFIO code to specialize
its handling.
Signed-off-by: Eric Auger
---
v4 -> v5:
- patches 1, 4, 5 were upstreamed separately
- s/IOMMU_ATTR_HW_NESTED_PAGING/IOMMU_ATTR_NEED_HW_NESTED_PAGING
v3 -> v4:
- s/IOMMU_ATTR_VFIO_NESTED/IOMMU_ATTR_HW_NESTED_PAGING
- add comments related to the existing attributes
- fix space after the cast
---
hw/arm/smmuv3.c | 12
include/exec/memory.h | 8 +++-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 2eaf07fb5f..a932bf7136 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1490,6 +1490,17 @@ static void smmuv3_notify_flag_changed(IOMMUMemoryRegion
*iommu,
}
}
+static int smmuv3_get_attr(IOMMUMemoryRegion *iommu,
+ enum IOMMUMemoryRegionAttr attr,
+ void *data)
+{
+if (attr == IOMMU_ATTR_NEED_HW_NESTED_PAGING) {
+*(bool *)data = true;
+return 0;
+}
+return -EINVAL;
+}
+
static void smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
void *data)
{
@@ -1497,6 +1508,7 @@ static void
smmuv3_iommu_memory_region_class_init(ObjectClass *klass,
imrc->translate = smmuv3_translate;
imrc->notify_flag_changed = smmuv3_notify_flag_changed;
+imrc->get_attr = smmuv3_get_attr;
}
static const TypeInfo smmuv3_type_info = {
diff --git a/include/exec/memory.h b/include/exec/memory.h
index fddc2ff48a..61493633fa 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -212,7 +212,13 @@ typedef struct MemoryRegionClass {
enum IOMMUMemoryRegionAttr {
-IOMMU_ATTR_SPAPR_TCE_FD
+/* Retrieve an integer corresponding to the TCE file descriptor */
+IOMMU_ATTR_SPAPR_TCE_FD,
+/*
+ * Retrieve a boolean that indicates whether the virtual IOMMU relies
+ * on physical IOMMU HW nested paging to protect host assigned devices
+ */
+IOMMU_ATTR_NEED_HW_NESTED_PAGING,
};
/**
--
2.20.1
[Qemu-devel] [PATCH v5 0/2] VFIO/SMMUv3: Fail on VFIO/HW nested paging detection
As of today when a guest is assigned with a host PCI device and an SMMUv3, VFIO calls memory_region_iommu_replay() default implementation. This translates the whole address range and completely stalls the execution. As VFIO/SMMUv3 integration is not supported yet (it requires SMMUv3 HW nested paging), let's recognize this situation and fail. Best Regards Eric This series can be found at: https://github.com/eauger/qemu/tree/v4.1.0_smmu_vfio_fail_v5 History: v4 -> v5: - v4 patches: 1, 4, 5 were upstreamed separately - IOMMU_ATTR_HW_NESTED_PAGING renamed into IOMMU_ATTR_NEED_HW_NESTED_PAGING v3 -> v4: - see individual patches v2 -> v3: - squash IOMMU_ATTR_VFIO_NESTED introduction and SMMUv3 usage - assert when recognizing VFIO/NESTED case - collect R-bs v1 -> v2: - Added "memory: Remove unused memory_region_iommu_replay_all()" & "hw/arm/smmuv3: Log a guest error when decoding an invalid STE" - do not attempt to implement replay Cb but rather remove the call in case it is not needed - explain why we do not remove other log messages on config decoding Eric Auger (2): memory: Add IOMMU_ATTR_NEED_HW_NESTED_PAGING IOMMU memory region attribute hw/vfio/common: Fail on VFIO/HW nested paging detection hw/arm/smmuv3.c | 12 hw/vfio/common.c | 10 ++ include/exec/memory.h | 8 +++- 3 files changed, 29 insertions(+), 1 deletion(-) -- 2.20.1
[Qemu-devel] [PATCH v5 2/2] hw/vfio/common: Fail on VFIO/HW nested paging detection
As of today, VFIO only works along with vIOMMU supporting
caching mode. The SMMUv3 does not support this mode and
requires HW nested paging to work properly with VFIO.
So any attempt to run a VFIO device protected by such IOMMU
would prevent the assigned device from working and at the
moment the guest does not even boot as the default
memory_region_iommu_replay() implementation attempts to
translate the whole address space and completely stalls
the guest.
So let's fail on that case.
Signed-off-by: Eric Auger
---
v3 -> v4:
- use IOMMU_ATTR_HW_NESTED_PAGING
- do not abort anymore but jump to fail
---
hw/vfio/common.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index 3e03c495d8..e8c009d019 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -606,9 +606,19 @@ static void vfio_listener_region_add(MemoryListener
*listener,
if (memory_region_is_iommu(section->mr)) {
VFIOGuestIOMMU *giommu;
IOMMUMemoryRegion *iommu_mr = IOMMU_MEMORY_REGION(section->mr);
+bool nested;
int iommu_idx;
trace_vfio_listener_region_add_iommu(iova, end);
+
+if (!memory_region_iommu_get_attr(iommu_mr,
+ IOMMU_ATTR_NEED_HW_NESTED_PAGING,
+ (void *)&nested) && nested) {
+error_report("VFIO/vIOMMU integration based on HW nested paging "
+ "is not yet supported");
+ret = -EINVAL;
+goto fail;
+}
/*
* FIXME: For VFIO iommu types which have KVM acceleration to
* avoid bouncing all map/unmaps through qemu this way, this
--
2.20.1
Re: [Qemu-devel] [PATCH v3 0/4] Introduce the microvm machine type
Hi Sergio, The idea is interesting and I tried to launch a guest by your guide but seems failed to me. I tried both legacy and normal modes, but the vncviewer connected and told me that: The vm has no graphic display device. All the screen in vnc is just black. kernel config: CONFIG_KVM_MMIO=y CONFIG_VIRTIO_MMIO=y I don't know if any specified kernel version/patch/config is needed or anything I missed. Could you kindly give some tips? Thanks very much. Jing A QEMU instance with the microvm machine type can be invoked this way: - Normal mode: qemu-system-x86_64 -M microvm -m 512m -smp 2 \ -kernel vmlinux -append "console=hvc0 root=/dev/vda" \ -nodefaults -no-user-config \ -chardev pty,id=virtiocon0,server \ -device virtio-serial-device \ -device virtconsole,chardev=virtiocon0 \ -drive id=test,file=test.img,format=raw,if=none \ -device virtio-blk-device,drive=test \ -netdev tap,id=tap0,script=no,downscript=no \ -device virtio-net-device,netdev=tap0 - Legacy mode: qemu-system-x86_64 -M microvm,legacy -m 512m -smp 2 \ -kernel vmlinux -append "console=ttyS0 root=/dev/vda" \ -nodefaults -no-user-config \ -drive id=test,file=test.img,format=raw,if=none \ -device virtio-blk-device,drive=test \ -netdev tap,id=tap0,script=no,downscript=no \ -device virtio-net-device,netdev=tap0 \ -serial stdio
[Qemu-devel] [PATCH v3] job: drop job_drain
In job_finish_sync job_enter should be enough for a job to make some
progress and draining is a wrong tool for it. So use job_enter directly
here and drop job_drain with all related staff not used more.
Suggested-by: Kevin Wolf
Signed-off-by: Vladimir Sementsov-Ogievskiy
Tested-by: John Snow
Reviewed-by: John Snow
---
v3: rebase on master
drop drain from test_simple_job_driver too
add John's r-b and t-b
include/block/blockjob_int.h | 19 ---
include/qemu/job.h | 13 -
block/backup.c | 19 +--
block/commit.c | 1 -
block/mirror.c | 28 +++-
block/stream.c | 1 -
blockjob.c | 13 -
job.c| 12 +---
tests/test-bdrv-drain.c | 3 ---
tests/test-block-iothread.c | 1 -
tests/test-blockjob-txn.c| 1 -
tests/test-blockjob.c| 2 --
12 files changed, 5 insertions(+), 108 deletions(-)
diff --git a/include/block/blockjob_int.h b/include/block/blockjob_int.h
index e4a318dd15..e2824a36a8 100644
--- a/include/block/blockjob_int.h
+++ b/include/block/blockjob_int.h
@@ -52,17 +52,6 @@ struct BlockJobDriver {
* besides job->blk to the new AioContext.
*/
void (*attached_aio_context)(BlockJob *job, AioContext *new_context);
-
-/*
- * If the callback is not NULL, it will be invoked when the job has to be
- * synchronously cancelled or completed; it should drain BlockDriverStates
- * as required to ensure progress.
- *
- * Block jobs must use the default implementation for job_driver.drain,
- * which will in turn call this callback after doing generic block job
- * stuff.
- */
-void (*drain)(BlockJob *job);
};
/**
@@ -107,14 +96,6 @@ void block_job_free(Job *job);
*/
void block_job_user_resume(Job *job);
-/**
- * block_job_drain:
- * Callback to be used for JobDriver.drain in all block jobs. Drains the main
- * block node associated with the block jobs and calls BlockJobDriver.drain for
- * job-specific actions.
- */
-void block_job_drain(Job *job);
-
/**
* block_job_ratelimit_get_delay:
*
diff --git a/include/qemu/job.h b/include/qemu/job.h
index 73c67d3175..bd59cd8944 100644
--- a/include/qemu/job.h
+++ b/include/qemu/job.h
@@ -220,13 +220,6 @@ struct JobDriver {
*/
void (*complete)(Job *job, Error **errp);
-/*
- * If the callback is not NULL, it will be invoked when the job has to be
- * synchronously cancelled or completed; it should drain any activities
- * as required to ensure progress.
- */
-void (*drain)(Job *job);
-
/**
* If the callback is not NULL, prepare will be invoked when all the jobs
* belonging to the same transaction complete; or upon this job's
completion
@@ -470,12 +463,6 @@ bool job_user_paused(Job *job);
*/
void job_user_resume(Job *job, Error **errp);
-/*
- * Drain any activities as required to ensure progress. This can be called in a
- * loop to synchronously complete a job.
- */
-void job_drain(Job *job);
-
/**
* Get the next element from the list of block jobs after @job, or the
* first one if @job is %NULL.
diff --git a/block/backup.c b/block/backup.c
index 2baf7bed65..2a81ed3d74 100644
--- a/block/backup.c
+++ b/block/backup.c
@@ -425,21 +425,6 @@ void backup_do_checkpoint(BlockJob *job, Error **errp)
bdrv_set_dirty_bitmap(backup_job->copy_bitmap, 0, backup_job->len);
}
-static void backup_drain(BlockJob *job)
-{
-BackupBlockJob *s = container_of(job, BackupBlockJob, common);
-
-/* Need to keep a reference in case blk_drain triggers execution
- * of backup_complete...
- */
-if (s->target) {
-BlockBackend *target = s->target;
-blk_ref(target);
-blk_drain(target);
-blk_unref(target);
-}
-}
-
static BlockErrorAction backup_error_action(BackupBlockJob *job,
bool read, int error)
{
@@ -588,13 +573,11 @@ static const BlockJobDriver backup_job_driver = {
.job_type = JOB_TYPE_BACKUP,
.free = block_job_free,
.user_resume= block_job_user_resume,
-.drain = block_job_drain,
.run= backup_run,
.commit = backup_commit,
.abort = backup_abort,
.clean = backup_clean,
-},
-.drain = backup_drain,
+}
};
static int64_t backup_calculate_cluster_size(BlockDriverState *target,
diff --git a/block/commit.c b/block/commit.c
index 408ae15389..bc8454463d 100644
--- a/block/commit.c
+++ b/block/commit.c
@@ -216,7 +216,6 @@ static const BlockJobDriver commit_job_driver = {
.job_type = JOB_TYPE_COMMIT,
.free = block_job_free,
.user_resume = block_job_user_resume,
-.drain
[Qemu-devel] [PATCH] qapi: Reintroduce CommandDisabled error class
If there was a disabled command, then qemu-ga used to report
CommandDisabled error class (among with human readable
description). This changed in v1.2.0-rc0~28^2~16 in favor of
GenericError class. While the change might work for other
classes, this one should not have been dropped because it helps
callers distinguish the root cause of the error.
A bit of background: up until very recently libvirt used qemu-ga
in all or nothing way. It didn't care why a qemu-ga command
failed. But very recently a new API was introduced which
implements 'best effort' approach (in some cases) and thus
libvirt must differentiate between: {CommandNotFound,
CommandDisabled} and some generic error. While the former classes
mean the API can issue some other commands the latter raises a
red flag causing the API to fail.
This reverts df1e608a01 partially.
Signed-off-by: Michal Privoznik
---
include/qapi/error.h | 1 +
qapi/error.json | 4 +++-
qapi/qmp-dispatch.c | 5 +++--
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/include/qapi/error.h b/include/qapi/error.h
index 3f95141a01..7116b86a92 100644
--- a/include/qapi/error.h
+++ b/include/qapi/error.h
@@ -129,6 +129,7 @@
typedef enum ErrorClass {
ERROR_CLASS_GENERIC_ERROR = QAPI_ERROR_CLASS_GENERICERROR,
ERROR_CLASS_COMMAND_NOT_FOUND = QAPI_ERROR_CLASS_COMMANDNOTFOUND,
+ERROR_CLASS_COMMAND_DISABLED = QAPI_ERROR_CLASS_COMMANDDISABLED,
ERROR_CLASS_DEVICE_NOT_ACTIVE = QAPI_ERROR_CLASS_DEVICENOTACTIVE,
ERROR_CLASS_DEVICE_NOT_FOUND = QAPI_ERROR_CLASS_DEVICENOTFOUND,
ERROR_CLASS_KVM_MISSING_CAP = QAPI_ERROR_CLASS_KVMMISSINGCAP,
diff --git a/qapi/error.json b/qapi/error.json
index 3fad08f506..334d481399 100644
--- a/qapi/error.json
+++ b/qapi/error.json
@@ -14,6 +14,8 @@
#
# @CommandNotFound: the requested command has not been found
#
+# @CommandDisabled: the requested command has been disabled
+#
# @DeviceNotActive: a device has failed to be become active
#
# @DeviceNotFound: the requested device has not been found
@@ -25,5 +27,5 @@
##
{ 'enum': 'QapiErrorClass',
# Keep this in sync with ErrorClass in error.h
- 'data': [ 'GenericError', 'CommandNotFound',
+ 'data': [ 'GenericError', 'CommandNotFound', 'CommandDisabled',
'DeviceNotActive', 'DeviceNotFound', 'KVMMissingCap' ] }
diff --git a/qapi/qmp-dispatch.c b/qapi/qmp-dispatch.c
index 3037d353a4..913b3363cb 100644
--- a/qapi/qmp-dispatch.c
+++ b/qapi/qmp-dispatch.c
@@ -104,8 +104,9 @@ static QObject *do_qmp_dispatch(QmpCommandList *cmds,
QObject *request,
return NULL;
}
if (!cmd->enabled) {
-error_setg(errp, "The command %s has been disabled for this instance",
- command);
+error_set(errp, ERROR_CLASS_COMMAND_DISABLED,
+ "The command %s has been disabled for this instance",
+ command);
return NULL;
}
if (oob && !(cmd->options & QCO_ALLOW_OOB)) {
--
2.21.0
Re: [Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
On Thu, Aug 29, 2019 at 04:53:02PM +0800, zhe...@windriver.com wrote:
> From: He Zhe
>
> libgcrypt may also be controlled by pkg-config, this patch adds pkg-config
> handling for libgcrypt.
Where are you seeing pkg-config files for libgcrypt ?
The upstream project has (frustratingly) been hostile to any proposal to
add pkg-config support saying people should stick with their custom
libgcrypt-config tool
https://dev.gnupg.org/T2037
Even if this is something added by some distro downstream, what is the
benefit in using it, compared with libgcrypt-confg which should already
work & is portable.
>
> Signed-off-by: He Zhe
> ---
> configure | 48
> 1 file changed, 40 insertions(+), 8 deletions(-)
>
> diff --git a/configure b/configure
> index e44e454..0f362a7 100755
> --- a/configure
> +++ b/configure
> @@ -2875,6 +2875,30 @@ has_libgcrypt() {
> return 0
> }
>
> +has_libgcrypt_pkgconfig() {
> +if ! has $pkg_config ; then
> +return 1
> +fi
> +
> +if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then
> +return 1
> +fi
> +
> +if test -n "$cross_prefix" ; then
> +host=$($pkg_config --variable=host libgcrypt)
> +if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then
> +print_error "host($host) does not match
> cross_prefix($cross_prefix)"
> +return 1
> +fi
> +fi
> +
> +if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then
> +print_error "libgcrypt version is $($pkg_config --modversion
> libgcrypt)"
> +return 1
> +fi
> +
> +return 0
> +}
>
> if test "$nettle" != "no"; then
> pass="no"
> @@ -2902,7 +2926,14 @@ fi
>
> if test "$gcrypt" != "no"; then
> pass="no"
> -if has_libgcrypt; then
> +if has_libgcrypt_pkgconfig; then
> +gcrypt_cflags=$($pkg_config --cflags libgcrypt)
> +if test "$static" = "yes" ; then
> +gcrypt_libs=$($pkg_config --libs --static libgcrypt)
> +else
> +gcrypt_libs=$($pkg_config --libs libgcrypt)
> +fi
> +elif has_libgcrypt; then
> gcrypt_cflags=$(libgcrypt-config --cflags)
> gcrypt_libs=$(libgcrypt-config --libs)
> # Debian has removed -lgpg-error from libgcrypt-config
> @@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then
> then
> gcrypt_libs="$gcrypt_libs -lgpg-error"
> fi
> +fi
>
> -# Link test to make sure the given libraries work (e.g for static).
> -write_c_skeleton
> -if compile_prog "" "$gcrypt_libs" ; then
> -LIBS="$gcrypt_libs $LIBS"
> -QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
> -pass="yes"
> -fi
> +# Link test to make sure the given libraries work (e.g for static).
> +write_c_skeleton
> +if compile_prog "" "$gcrypt_libs" ; then
> + LIBS="$gcrypt_libs $LIBS"
> + QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
> + pass="yes"
> fi
> +
> if test "$pass" = "yes"; then
> gcrypt="yes"
> cat > $TMPC << EOF
> --
> 2.7.4
>
Regards,
Daniel
--
|: https://berrange.com -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [Qemu-devel] [PATCH v9 11/13] block: add lock/unlock range functions
28.08.2019 20:02, Max Reitz wrote: > On 26.08.19 18:13, Vladimir Sementsov-Ogievskiy wrote: >> From: Vladimir Sementsov-Ogievskiy > > Hm. :-) > > Do you want to fix that? Yes.. Hmm seems like I was working from home at some moment > >> Introduce lock/unlock range functionality, based on serialized >> requests. This is needed to refactor backup, dropping local >> tracked-request-like synchronization. >> >> Signed-off-by: Vladimir Sementsov-Ogievskiy >> --- >> include/block/block_int.h | 4 >> block/io.c| 44 ++- >> 2 files changed, 47 insertions(+), 1 deletion(-) > > Apart from that, I can’t see any changes from v8, so: > > Reviewed-by: Max Reitz > -- Best regards, Vladimir
Re: [Qemu-devel] [RFC 2/3] intc/arm_gic: Support PPI injection for more than 256 vpus
Hi,
On 8/29/19 9:58 AM, Auger Eric wrote:
> Hi Zenghui,
>
> On 8/29/19 4:53 AM, Zenghui Yu wrote:
>> Hi Eric,
>>
>> On 2019/8/28 0:05, Eric Auger wrote:
>>> Host kernels that expose the KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 capability
>>> allow injection of PPIs along with vcpu ids larger than 255. Let's
>>> encode the vpcu id on 12 bits according to the upgraded KVM_IRQ_LINE
>>> ABI when needed.
>>>
>>> Without that patch qemu exits with "kvm_set_irq: Invalid argument"
>>> message.
>>>
>>> Signed-off-by: Eric Auger
>>> Reported-by: Zenghui Yu
>>> ---
>>> hw/intc/arm_gic_kvm.c | 10 +++---
>>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
>>> index b56fda144f..889293e97f 100644
>>> --- a/hw/intc/arm_gic_kvm.c
>>> +++ b/hw/intc/arm_gic_kvm.c
>>> @@ -56,6 +56,7 @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int irq,
>>> int level)
>>> * CPU number and interrupt number.
>>> */
>>> int kvm_irq, irqtype, cpu;
>>> + int cpu_idx1 = 0, cpu_idx2 = 0;
>>> if (irq < (num_irq - GIC_INTERNAL)) {
>>> /* External interrupt. The kernel numbers these like the GIC
>>> @@ -63,17 +64,20 @@ void kvm_arm_gic_set_irq(uint32_t num_irq, int
>>> irq, int level)
>>> * internal ones.
>>> */
>>> irqtype = KVM_ARM_IRQ_TYPE_SPI;
>>> - cpu = 0;
>>> irq += GIC_INTERNAL;
>>> } else {
>>> /* Internal interrupt: decode into (cpu, interrupt id) */
>>> irqtype = KVM_ARM_IRQ_TYPE_PPI;
>>> irq -= (num_irq - GIC_INTERNAL);
>>> cpu = irq / GIC_INTERNAL;
>>> + cpu_idx2 = cpu / 256;
>>> + cpu_idx1 = cpu % 256;
>>> irq %= GIC_INTERNAL;
>>> }
>>> - kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT)
>>> - | (cpu << KVM_ARM_IRQ_VCPU_SHIFT) | irq;
>>> + kvm_irq = (irqtype << KVM_ARM_IRQ_TYPE_SHIFT) |
>>> + (cpu_idx1 << KVM_ARM_IRQ_VCPU_SHIFT) |
>>> + ((cpu_idx2 & KVM_ARM_IRQ_VCPU2_MASK) <<
>>> KVM_ARM_IRQ_VCPU2_SHIFT) |
>>> + irq;
>>> kvm_set_irq(kvm_state, kvm_irq, !!level);
>>> }
>>>
>>
>> For confirmation, should we also adjust the vcpu_index in
>> arm_cpu_kvm_set_irq(), just like above?
>
> I am not familiar with this path. in arm_cpu_initfn(), there is a
> comment saying "VIRQ and VFIQ are unused with KVM but we add them to
> maintain the same interface as non-KVM CPUs." So I don't know when that
> code gets executed.
>
> But maybe it would be more cautious to implement your suggestion here as
> well.
>
> Maybe Peter can provide more info here?
If this is supposed to get used along with kernel_irqchip=off, it seems
this latter is not supported with GICv3 anyway. So max number of vcpus
with GICv2 is 8.
Thanks
Eric
>
> Thanks
>
> Eric
>
>
>>
>>
>> Thanks,
>> zenghui
>>
>>
>
Re: [Qemu-devel] Cryptic errors from PIP install if missing openssl-devel
On 8/29/19 5:27 AM, Cleber Rosa wrote:
> On Thu, Aug 29, 2019 at 11:51:17AM +1000, David Gibson wrote:
>> On Thu, Aug 29, 2019 at 11:31:25AM +1000, David Gibson wrote:
>>> If I attempt to run "make check-acceptance" on my POWER9, RHEL8.1
>>> machine when the openssl-devel package isn't installed, I get the
>>> following very cryptic error:
>>>
>>> VENV/home/dwg/qemu/build/rhel8/tests/venv
>>> PIP /home/dwg/qemu/tests/requirements.txt
>>> Command "/home/dwg/qemu/build/rhel8/tests/venv/bin/python -u -c "import
>>> setuptools,
>>> tokenize;__file__='/tmp/pip-build-la4el5r5/cryptography/setup.py';f=getattr(tokenize,
>>> 'open', open)(__file__);code=f.read().replace('\r\n',
>>> '\n');f.close();exec(compile(code, __file__, 'exec'))" install --record
>>> /tmp/pip-1efs22iz-record/install-record.txt
>>> --single-version-externally-managed --compile --install-headers
>>> /home/dwg/qemu/build/rhel8/tests/venv/include/site/python3.6/cryptography"
>>> failed with error code 1 in /tmp/pip-build-la4el5r5/cryptography/
>>>
>>> Using V=1 doesn't give any more useful information, and it's not
>>> (easily) possible to manually re-run the given command since it relies
>>> on things in /tmp that are removed once the attempt finishes.
>>>
>>> I only figured out it was openssl-devel being missing that was the
>>> problem by (mostly) guesswork. It would be really great if we could
>>> generate a more helpful error here.
>>>
>>> In addition, if I rerun "make check-acceptance" it no longer even
>>> attempts the PIP install, since tests/venv already exists in my build
>>> environment. It then sort of works, but I think it might be hitting
>>> other errors because of the missing python packages. Sorry that's a
>>> bit vague - I also seem to be getting unrelated errors that I'm still
>>> trying to figure out.
>>
>> Fwiw, I also get an equally cryptic error that I haven't figured out
>> the cause for on my 32-bit Fedora container environment:
>>
>> VENV/home/dwg/src/qemu/build/i386/tests/venv
>> PIP /home/dwg/src/qemu/tests/requirements.txt
>> Failed building wheel for bcrypt
>> Could not build wheels for bcrypt which use PEP 517 and cannot be installed
>> directly
>> You are using pip version 19.0.3, however version 19.2.3 is available.
>> You should consider upgrading via the 'pip install --upgrade pip' command.
>>
>
> This is certainly caused by pip not being able to install paramiko on
> those systems. I have dealt with paramiko (and its many dependencies)
> before on the avocado remote runner plugin (which is not being used
> here) and it was not fun.
>
> My personal goal was to rely on the ssh binary as an ssh client, which
> should be more ubiquitous, and with that I added a simple wrapper to
> Avocado:
>
>
> https://avocado-framework.readthedocs.io/en/71.0/api/utils/avocado.utils.html#module-avocado.utils.ssh
I did not know this module.
> I guess we should consider changing the (few) tests that require
> paramiko to use that module instead.
Clean way to resolve this issue.
>> In this case the check definitely doesn't work - it doesn't appear to
>> have installed avocado in the venv.
>>
>> AVOCADO tests/acceptance
>> /home/dwg/src/qemu/build/i386/tests/venv/bin/python: No module named avocado
>>
>
> My hope is that with pure Python modules in requirements.txt, failures
> will be much harder to come by. Either way, it'd be nice to improve
Is there a way to check for this before submitting/merging patches?
Some checkpatch.py lines that report:
The 'paramiko' module is not pure Python and can
not be added in requirements.txt.
> the venv creation, at the very least add a cleanup if it fails to
> complete successfully.
>
> As a workaround I'd suggest two things:
>
> 1) remove paramiko from requirements.txt
> 2) set the env var CONTINUOUS_INTEGRATION=1 before running `make
> check-acceptace` (the tests in linux_ssh_mips_malta.py check for
> that and don't run if it's set).
>
> But, we'll need to address those failures definitely ASAP. Anyway,
> thanks for reporting it.
>
> - Cleber.
>
>> --
>> David Gibson | I'll have my music baroque, and my code
>> david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_
>> _other_
>> | _way_ _around_!
>> http://www.ozlabs.org/~dgibson
>
>
>
Re: [Qemu-devel] [PATCH v1 8/9] accel/stubs: reduce headers from tcg-stub
Alex Bennée writes:
> We don't need much for these. However I do wonder why these aren't
> just null inlines in exec-all.h
>
> Signed-off-by: Alex Bennée
> Reviewed-by: Richard Henderson
> ---
> accel/stubs/tcg-stub.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
> index e2d23edafe0..75b10ab54be 100644
> --- a/accel/stubs/tcg-stub.c
> +++ b/accel/stubs/tcg-stub.c
> @@ -11,10 +11,8 @@
> */
>
> #include "qemu/osdep.h"
> -#include "qemu-common.h"
> #include "cpu.h"
> #include "tcg/tcg.h"
> -#include "exec/exec-all.h"
>
> void tb_flush(CPUState *cpu)
> {
I'll drop this one as it doesn't merge build cleanly against master on
Travis (but oddly built on my machine).
--
Alex Bennée
Re: [Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
On Thu, Aug 29, 2019 at 05:26:49PM +0800, He Zhe wrote: > > > On 8/29/19 5:15 PM, Daniel P. Berrangé wrote: > > On Thu, Aug 29, 2019 at 04:53:02PM +0800, zhe...@windriver.com wrote: > >> From: He Zhe > >> > >> libgcrypt may also be controlled by pkg-config, this patch adds pkg-config > >> handling for libgcrypt. > > Where are you seeing pkg-config files for libgcrypt ? > > > > The upstream project has (frustratingly) been hostile to any proposal to > > add pkg-config support saying people should stick with their custom > > libgcrypt-config tool > > > >https://dev.gnupg.org/T2037 > > > > Even if this is something added by some distro downstream, what is the > > benefit in using it, compared with libgcrypt-confg which should already > > work & is portable. > > IMHO, it could be easy for people to use pkg-config as a center to control > configurations for many different packages. > > This is just an addition for qemu to be able to work in both cases. It does > not > remove libgcrypt-confg and can fall back to libgcrypt-confg when pkg-config > does > not work. The addition has a maint cost associated with it, since we have have two different ways to achieve the same thing. When only one of the approaches is provided by upstream, the other is not going to be widely tested. In maintaining packages in Fedora which rely on pkg-config files that are not upstream, we've seen frequent breakage when. So my preference is stick with what we have that is supported by upstream gcrypt. Regards, Daniel -- |: https://berrange.com -o-https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o-https://fstop138.berrange.com :| |: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|
Re: [Qemu-devel] Cryptic errors from PIP install if missing openssl-devel
Hi Cleber, Lukáš, On 8/29/19 11:24 AM, Philippe Mathieu-Daudé wrote: > On 8/29/19 5:27 AM, Cleber Rosa wrote: >> On Thu, Aug 29, 2019 at 11:51:17AM +1000, David Gibson wrote: [...] >>> Fwiw, I also get an equally cryptic error that I haven't figured out >>> the cause for on my 32-bit Fedora container environment: >>> >>> VENV/home/dwg/src/qemu/build/i386/tests/venv >>> PIP /home/dwg/src/qemu/tests/requirements.txt >>> Failed building wheel for bcrypt >>> Could not build wheels for bcrypt which use PEP 517 and cannot be installed >>> directly >>> You are using pip version 19.0.3, however version 19.2.3 is available. >>> You should consider upgrading via the 'pip install --upgrade pip' command. >>> >> >> This is certainly caused by pip not being able to install paramiko on >> those systems. I have dealt with paramiko (and its many dependencies) >> before on the avocado remote runner plugin (which is not being used >> here) and it was not fun. >> >> My personal goal was to rely on the ssh binary as an ssh client, which >> should be more ubiquitous, and with that I added a simple wrapper to >> Avocado: >> >> >> https://avocado-framework.readthedocs.io/en/71.0/api/utils/avocado.utils.html#module-avocado.utils.ssh > > I did not know this module. class avocado.utils.ssh.Session(address, credentials) Parameters: credentials (tuple) username and path to a key for authentication purposes The current test uses username + password. Can we use this credentials with the Avocado module? (The image used is prebuilt). >> I guess we should consider changing the (few) tests that require >> paramiko to use that module instead. > > Clean way to resolve this issue.
Re: [Qemu-devel] [RFC Patch] xen/pt: Emulate FLR capability
On 29.08.2019 11:02, Chao Gao wrote:
> Currently, for a HVM on Xen, no reset method is virtualized. So in a VM's
> perspective, assigned devices cannot be reset. But some devices rely on PCI
> reset to recover from hardware hangs. When being assigned to a VM, those
> devices cannot be reset and won't work any longer if a hardware hang occurs.
> We have to reboot VM to trigger PCI reset on host to recover the device.
Did you consider a hot-unplug, reset (by host), hot-plug cycle instead?
> +static int xen_pt_devctl_reg_write(XenPCIPassthroughState *s,
> + XenPTReg *cfg_entry, uint16_t *val,
> + uint16_t dev_value, uint16_t valid_mask)
> +{
> +if (s->real_device.is_resetable && (*val & PCI_EXP_DEVCTL_BCR_FLR)) {
> +xen_pt_reset(s);
> +}
> +return xen_pt_word_reg_write(s, cfg_entry, val, dev_value, valid_mask);
I think you also need to clear the bit before handing on the request,
such that reads will always observe it clear.
Jan
[Qemu-devel] [PATCH 0/2] git.orderfile: Order Python/shell scripts before unordered files
This series update the git.orderfile to order Python and shell scripts before unordered files. This is particularly useful for changes in tests/qemu-iotests. Regards, Phil. Philippe Mathieu-Daudé (2): scripts/git.orderfile: Order Python files before unordered ones scripts/git.orderfile: Order shell scripts before unordered files scripts/git.orderfile | 5 + 1 file changed, 5 insertions(+) -- 2.20.1
[Qemu-devel] [PATCH 1/2] scripts/git.orderfile: Order Python files before unordered ones
Order Python source files before the rest of unordered files. This helps in particular while reviewing iotests. Signed-off-by: Philippe Mathieu-Daudé --- scripts/git.orderfile | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/git.orderfile b/scripts/git.orderfile index ac699700b1..0ad5b9b8a8 100644 --- a/scripts/git.orderfile +++ b/scripts/git.orderfile @@ -26,4 +26,5 @@ Makefile* # code *.c +*.py -- 2.20.1
[Qemu-devel] [PATCH 2/2] scripts/git.orderfile: Order shell scripts before unordered files
Order shell scripts before the rest of unordered files. This helps in particular while reviewing iotests. Signed-off-by: Philippe Mathieu-Daudé --- scripts/git.orderfile | 4 1 file changed, 4 insertions(+) diff --git a/scripts/git.orderfile b/scripts/git.orderfile index 0ad5b9b8a8..4d25153ea4 100644 --- a/scripts/git.orderfile +++ b/scripts/git.orderfile @@ -28,3 +28,7 @@ Makefile* *.c *.py +# shell scripts +*.rc +*.sh + -- 2.20.1
Re: [Qemu-devel] [patch-for-4.2 PATCH v11 0/6] target-ppc/spapr: Add FWNMI support in QEMU for PowerKVM guests
On Wed, 14 Aug 2019 11:40:50 +0530 Aravinda Prasad wrote: > This patch set adds support for FWNMI in PowerKVM guests. > > System errors such as SLB multihit and memory errors > that cannot be corrected by hardware is passed on to > the kernel for handling by raising machine check > exception (an NMI). Upon such machine check exceptions, > if the address in error belongs to guest then KVM > invokes guests' 0x200 interrupt vector if the guest > is not FWNMI capable. For FWNMI capable guest > KVM passes the control to QEMU by exiting the guest. > > This patch series adds functionality to QEMU to pass > on such machine check exceptions to the FWNMI capable > guest kernel by building an error log and invoking > the guest registered machine check handling routine. > > The KVM changes are now part of the upstream kernel > (commit e20bbd3d). This series contain QEMU changes. > > Change Log v11: > - Moved FWNMI SPAPR cap defaults to 4.2 class option > - Fixed issues with handling fwnmi KVM capability > Hi Aravinda, I'm afraid this series needs rebasing. It doesn't apply cleanly on current ppc-for-4.2 (SHA1 b1e8156743). Cheers, -- Greg > Change Log v10: > - Reshuffled the patch sequence + minor fixes > > Change Log v9: > - Fixed kvm cap and spapr cap issues > > Change Log v8: > - Added functionality to check FWNMI capability during > VM migration > --- > > Aravinda Prasad (6): > Wrapper function to wait on condition for the main loop mutex > ppc: spapr: Introduce FWNMI capability > target/ppc: Handle NMI guest exit > target/ppc: Build rtas error log upon an MCE > ppc: spapr: Handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS calls > migration: Include migration support for machine check handling > > > cpus.c |5 + > hw/ppc/spapr.c | 78 + > hw/ppc/spapr_caps.c | 29 + > hw/ppc/spapr_events.c| 268 > ++ > hw/ppc/spapr_rtas.c | 78 + > include/hw/ppc/spapr.h | 25 > include/qemu/main-loop.h |8 + > target/ppc/cpu.h |1 > target/ppc/kvm.c | 38 +++ > target/ppc/kvm_ppc.h | 13 ++ > target/ppc/trace-events |1 > 11 files changed, 542 insertions(+), 2 deletions(-) > > -- > Signature
Re: [Qemu-devel] [RFC Patch] xen/pt: Emulate FLR capability
On Thu, Aug 29, 2019 at 05:02:27PM +0800, Chao Gao wrote: > Currently, for a HVM on Xen, no reset method is virtualized. So in a VM's > perspective, assigned devices cannot be reset. But some devices rely on PCI > reset to recover from hardware hangs. When being assigned to a VM, those > devices cannot be reset and won't work any longer if a hardware hang occurs. > We have to reboot VM to trigger PCI reset on host to recover the device. > > This patch exposes FLR capability to VMs if the assigned device can be reset > on > host. When VM initiates an FLR to a device, qemu cleans up the device state, > (including disabling of intx and/or MSI and unmapping BARs from guest, > deleting > emulated registers), then initiate PCI reset through 'reset' knob under the > device's sysfs, finally initialize the device again. I think you likely need to deassign the device from the VM, perform the reset, and then assign the device again, so that there's no Xen internal state carried over prior to the reset? Thanks, Roger.
Re: [Qemu-devel] [patch-for-4.2 PATCH v11 3/6] target/ppc: Handle NMI guest exit
On Wed, 14 Aug 2019 11:41:16 +0530
Aravinda Prasad wrote:
> Memory error such as bit flips that cannot be corrected
> by hardware are passed on to the kernel for handling.
> If the memory address in error belongs to guest then
> the guest kernel is responsible for taking suitable action.
> Patch [1] enhances KVM to exit guest with exit reason
> set to KVM_EXIT_NMI in such cases. This patch handles
> KVM_EXIT_NMI exit.
>
> [1] https://www.spinics.net/lists/kvm-ppc/msg12637.html
> (e20bbd3d and related commits)
>
> Signed-off-by: Aravinda Prasad
> Reviewed-by: David Gibson
> ---
> hw/ppc/spapr.c |8
> hw/ppc/spapr_events.c | 23 +++
> include/hw/ppc/spapr.h | 10 ++
> target/ppc/kvm.c| 14 ++
> target/ppc/kvm_ppc.h|2 ++
> target/ppc/trace-events |1 +
> 6 files changed, 58 insertions(+)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 07714cb..99def34 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1813,6 +1813,12 @@ static void spapr_machine_reset(MachineState *machine)
> first_ppc_cpu->env.gpr[5] = 0;
>
> spapr->cas_reboot = false;
> +
> +spapr->mc_status = -1;
> +spapr->guest_machine_check_addr = -1;
> +
> +/* Signal all vCPUs waiting on this condition */
> +qemu_cond_broadcast(&spapr->mc_delivery_cond);
> }
>
> static void spapr_create_nvram(SpaprMachineState *spapr)
> @@ -3089,6 +3095,8 @@ static void spapr_machine_init(MachineState *machine)
>
> kvmppc_spapr_enable_inkernel_multitce();
> }
> +
> +qemu_cond_init(&spapr->mc_delivery_cond);
> }
>
> static int spapr_kvm_type(MachineState *machine, const char *vm_type)
> diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
> index ae0f093..a0c66d7 100644
> --- a/hw/ppc/spapr_events.c
> +++ b/hw/ppc/spapr_events.c
> @@ -620,6 +620,29 @@ void
> spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
> RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id);
> }
>
> +void spapr_mce_req_event(PowerPCCPU *cpu)
> +{
> +SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
> +
> +while (spapr->mc_status != -1) {
> +/*
> + * Check whether the same CPU got machine check error
> + * while still handling the mc error (i.e., before
> + * that CPU called "ibm,nmi-interlock")
> + */
> +if (spapr->mc_status == cpu->vcpu_id) {
> +qemu_system_guest_panicked(NULL);
> +return;
> +}
> +qemu_cond_wait_iothread(&spapr->mc_delivery_cond);
hw/ppc/spapr_events.c: In function ‘spapr_mce_req_event’:
hw/ppc/spapr_events.c:638:9: error: implicit declaration of function
‘qemu_cond_wait_iothread’; did you mean ‘qemu_cond_wait_impl’?
[-Werror=implicit-function-declaration]
qemu_cond_wait_iothread(&spapr->mc_delivery_cond);
^~~
qemu_cond_wait_impl
hw/ppc/spapr_events.c:638:9: error: nested extern declaration of
‘qemu_cond_wait_iothread’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
It looks like hw/ppc/spapr_events.c is missing:
#include "qemu/main-loop.h"
> +/* Meanwhile if the system is reset, then just return */
> +if (spapr->guest_machine_check_addr == -1) {
> +return;
> +}
> +}
> +spapr->mc_status = cpu->vcpu_id;
> +}
> +
> static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr,
> uint32_t token, uint32_t nargs,
> target_ulong args,
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index 01c106f..619677a 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -191,6 +191,15 @@ struct SpaprMachineState {
> * occurs during the unplug process. */
> QTAILQ_HEAD(, SpaprDimmState) pending_dimm_unplugs;
>
> +/* State related to "ibm,nmi-register" and "ibm,nmi-interlock" calls */
> +target_ulong guest_machine_check_addr;
> +/*
> + * mc_status is set to -1 if mc is not in progress, else is set to the
> CPU
> + * handling the mc.
> + */
> +int mc_status;
> +QemuCond mc_delivery_cond;
> +
> /*< public >*/
> char *kvm_type;
> char *host_model;
> @@ -804,6 +813,7 @@ void spapr_clear_pending_events(SpaprMachineState *spapr);
> int spapr_max_server_number(SpaprMachineState *spapr);
> void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex,
>uint64_t pte0, uint64_t pte1);
> +void spapr_mce_req_event(PowerPCCPU *cpu);
>
> /* DRC callbacks. */
> void spapr_core_release(DeviceState *dev);
> diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
> index c922bcb..375dc09 100644
> --- a/target/ppc/kvm.c
> +++ b/target/ppc/kvm.c
> @@ -1702,6 +1702,11 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run
> *run)
> ret = 0;
> break;
>
> +case KVM_EXIT_NMI:
> +
[Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0
From: Aleksandar Markovic
Clean up handling of CP0 register 0.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-2-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 3 +++
target/mips/translate.c | 40
2 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 1fd4a18..42d0e44 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -277,6 +277,9 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 00 */
#define CP0_REG00__INDEX 0
+#define CP0_REG00__MVPCONTROL 1
+#define CP0_REG00__MVPCONF02
+#define CP0_REG00__MVPCONF13
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
/* CP0 Register 02 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8ebde6f..c3fcfb4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6813,26 +6813,26 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
-case 0:
+case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
-case 1:
+case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
-case 2:
+case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
-case 3:
+case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
-case 4:
+case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -7573,26 +7573,26 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
-case 0:
+case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
-case 1:
+case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
-case 2:
+case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
-case 3:
+case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
-case 4:
+case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
@@ -8319,26 +8319,26 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
-case 0:
+case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
-case 1:
+case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
-case 2:
+case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
-case 3:
+case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
-case 4:
+case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -9033,26 +9033,26 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
-case 0:
+case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
-case 1:
+case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
-
[Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14
From: Aleksandar Markovic
Clean up handling of CP0 register 14.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-16-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 8
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 4fce05a..2a9c6d5 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -361,6 +361,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG13__NESTEDEXC 5
/* CP0 Register 14 */
#define CP0_REG14__EPC 0
+#define CP0_REG14__NESTEDEPC 2
/* CP0 Register 15 */
#define CP0_REG15__PRID0
#define CP0_REG15__EBASE 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4da08e1..efedced 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7212,7 +7212,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
-case 0:
+case CP0_REG14__EPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EPC";
@@ -7946,7 +7946,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
-case 0:
+case CP0_REG14__EPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
@@ -8687,7 +8687,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
-case 0:
+case CP0_REG14__EPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
@@ -9409,7 +9409,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
-case 0:
+case CP0_REG14__EPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
--
2.7.4
[Qemu-devel] [PULL 03/31] target/mips: Clean up handling of CP0 register 2
From: Aleksandar Markovic
Clean up handling of CP0 register 2.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-4-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 7 ++
target/mips/translate.c | 64 -
2 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 36e983a..466f72a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -292,6 +292,13 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO00
+#define CP0_REG02__TCSTATUS1
+#define CP0_REG02__TCBIND 2
+#define CP0_REG02__TCRESTART 3
+#define CP0_REG02__TCHALT 4
+#define CP0_REG02__TCCONTEXT 5
+#define CP0_REG02__TCSCHEDULE 6
+#define CP0_REG02__TCSCHEFBACK 7
/* CP0 Register 03 */
#define CP0_REG03__ENTRYLO10
#define CP0_REG03__GLOBALNUM 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 97e0aec..66c6207 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6889,7 +6889,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
-case 0:
+case CP0_REG02__ENTRYLO0:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env,
@@ -6906,37 +6906,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
}
register_name = "EntryLo0";
break;
-case 1:
+case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
-case 2:
+case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
-case 3:
+case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
-case 4:
+case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
-case 5:
+case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
-case 6:
+case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
-case 7:
+case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -7650,41 +7650,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
-case 0:
+case CP0_REG02__ENTRYLO0:
gen_helper_mtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
-case 1:
+case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
-case 2:
+case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
-case 3:
+case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
-case 4:
+case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
-case 5:
+case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
-case 6:
+case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
-case 7:
+case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TC
[Qemu-devel] [PULL 02/31] target/mips: Clean up handling of CP0 register 1
From: Aleksandar Markovic
Clean up handling of CP0 register 1.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-3-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 8 +++
target/mips/translate.c | 64 -
2 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 42d0e44..36e983a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -282,6 +282,14 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG00__MVPCONF13
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
+#define CP0_REG01__RANDOM 0
+#define CP0_REG01__VPECONTROL 1
+#define CP0_REG01__VPECONF02
+#define CP0_REG01__VPECONF13
+#define CP0_REG01__YQMASK 4
+#define CP0_REG01__VPESCHEDULE 5
+#define CP0_REG01__VPESCHEFBACK6
+#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO00
/* CP0 Register 03 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c3fcfb4..97e0aec 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6843,42 +6843,42 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
-case 0:
+case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
-case 1:
+case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
-case 2:
+case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
-case 3:
+case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
-case 4:
+case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
-case 5:
+case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
-case 6:
+case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
-case 7:
+case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
@@ -7603,43 +7603,43 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
-case 0:
+case CP0_REG01__RANDOM:
/* ignored */
register_name = "Random";
break;
-case 1:
+case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(cpu_env, arg);
register_name = "VPEControl";
break;
-case 2:
+case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(cpu_env, arg);
register_name = "VPEConf0";
break;
-case 3:
+case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(cpu_env, arg);
register_name = "VPEConf1";
break;
-case 4:
+case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(cpu_env, arg);
register_name = "YQMask";
break;
-case 5:
+case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
-case 6:
+case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
-case 7:
+case CP0_RE
[Qemu-devel] [PULL 07/31] target/mips: Clean up handling of CP0 register 6
From: Aleksandar Markovic
Clean up handling of CP0 register 6.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-8-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 6 ++
target/mips/translate.c | 56 -
2 files changed, 34 insertions(+), 28 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index ed1a974..a0c6a6f 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -321,6 +321,12 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
+#define CP0_REG06__SRSCONF01
+#define CP0_REG06__SRSCONF12
+#define CP0_REG06__SRSCONF23
+#define CP0_REG06__SRSCONF34
+#define CP0_REG06__SRSCONF45
+#define CP0_REG06__PWCTL 6
/* CP0 Register 07 */
#define CP0_REG07__HWRENA 0
/* CP0 Register 08 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 19f86f2..a914fe4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7046,36 +7046,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
-case 0:
+case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
-case 1:
+case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
-case 2:
+case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
-case 3:
+case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
-case 4:
+case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
-case 5:
+case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
-case 6:
+case CP0_REG06__PWCTL:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl";
@@ -7778,36 +7778,36 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
-case 0:
+case CP0_REG06__WIRED:
gen_helper_mtc0_wired(cpu_env, arg);
register_name = "Wired";
break;
-case 1:
+case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
-case 2:
+case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
-case 3:
+case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
-case 4:
+case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
-case 5:
+case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
-case 6:
+case CP0_REG06__PWCTL:
check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg);
register_name = "PWCtl";
@@ -8523,36 +8523,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
-case 0:
+case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
-case 1:
+case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
-case 2:
+case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS
[Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9
From: Aleksandar Markovic
Clean up handling of CP0 register 9.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-11-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d4faa75..b79c58c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6658,7 +6658,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
-case 7:
+case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mfhc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -6740,7 +6740,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
-case 7:
+case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mthc0_saar(cpu_env, arg);
register_name = "SAAR";
@@ -7124,7 +7124,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
-case 0:
+case CP0_REG09__COUNT:
/* Mark as an IO operation because we read the time. */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -7139,12 +7139,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
-case 6:
+case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
register_name = "SAARI";
break;
-case 7:
+case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mfc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -7852,16 +7852,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
-case 0:
+case CP0_REG09__COUNT:
gen_helper_mtc0_count(cpu_env, arg);
register_name = "Count";
break;
-case 6:
+case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saari(cpu_env, arg);
register_name = "SAARI";
break;
-case 7:
+case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
register_name = "SAAR";
@@ -8600,7 +8600,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
-case 0:
+case CP0_REG09__COUNT:
/* Mark as an IO operation because we read the time. */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -8615,12 +8615,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
-case 6:
+case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
register_name = "SAARI";
break;
-case 7:
+case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_dmfc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -9311,16 +9311,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
-case 0:
+case CP0_REG09__COUNT:
gen_helper_mtc0_count(cpu_env, arg);
register_name = "Count";
break;
-case 6:
+case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saari(cpu_env, arg);
register_name = "SAARI";
break;
-case 7:
+case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
register_name = "SAAR";
--
2.7.4
[Qemu-devel] [PULL 04/31] target/mips: Clean up handling of CP0 register 3
From: Aleksandar Markovic
Clean up handling of CP0 register 3.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-5-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 20 ++--
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 466f72a..d5b7103 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -302,6 +302,7 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 03 */
#define CP0_REG03__ENTRYLO10
#define CP0_REG03__GLOBALNUM 1
+#define CP0_REG03__TCOPT 7
/* CP0 Register 04 */
#define CP0_REG04__CONTEXT 0
#define CP0_REG04__USERLOCAL 2
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 66c6207..059f53e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6647,7 +6647,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
-case 0:
+case CP0_REG03__ENTRYLO1:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
register_name = "EntryLo1";
@@ -6728,7 +6728,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
-case 0:
+case CP0_REG03__ENTRYLO1:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
@@ -6947,7 +6947,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
-case 0:
+case CP0_REG03__ENTRYLO1:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env,
@@ -6964,7 +6964,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
}
register_name = "EntryLo1";
break;
-case 1:
+case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
register_name = "GlobalNumber";
@@ -7695,11 +7695,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
-case 0:
+case CP0_REG03__ENTRYLO1:
gen_helper_mtc0_entrylo1(cpu_env, arg);
register_name = "EntryLo1";
break;
-case 1:
+case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "GlobalNumber";
@@ -8440,11 +8440,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
-case 0:
+case CP0_REG03__ENTRYLO1:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
register_name = "EntryLo1";
break;
-case 1:
+case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
register_name = "GlobalNumber";
@@ -9153,11 +9153,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
-case 0:
+case CP0_REG03__ENTRYLO1:
gen_helper_dmtc0_entrylo1(cpu_env, arg);
register_name = "EntryLo1";
break;
-case 1:
+case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "GlobalNumber";
--
2.7.4
[Qemu-devel] [PULL 09/31] target/mips: Clean up handling of CP0 register 8
From: Aleksandar Markovic
Clean up handling of CP0 register 8.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-10-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 32
2 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a0c6a6f..50a7205 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -333,6 +333,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG08__BADVADDR0
#define CP0_REG08__BADINSTR1
#define CP0_REG08__BADINSTRP 2
+#define CP0_REG08__BADINSTRX 3
/* CP0 Register 09 */
#define CP0_REG09__COUNT 0
#define CP0_REG09__SAARI 6
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cf2ba5a..d4faa75 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7097,22 +7097,22 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
-case 0:
+case CP0_REG08__BADVADDR:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
tcg_gen_ext32s_tl(arg, arg);
register_name = "BadVAddr";
break;
-case 1:
+case CP0_REG08__BADINSTR:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
register_name = "BadInstr";
break;
-case 2:
+case CP0_REG08__BADINSTRP:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
register_name = "BadInstrP";
break;
-case 3:
+case CP0_REG08__BADINSTRX:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0x);
@@ -7830,19 +7830,19 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
-case 0:
+case CP0_REG08__BADVADDR:
/* ignored */
register_name = "BadVAddr";
break;
-case 1:
+case CP0_REG08__BADINSTR:
/* ignored */
register_name = "BadInstr";
break;
-case 2:
+case CP0_REG08__BADINSTRP:
/* ignored */
register_name = "BadInstrP";
break;
-case 3:
+case CP0_REG08__BADINSTRX:
/* ignored */
register_name = "BadInstrX";
break;
@@ -8574,21 +8574,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
-case 0:
+case CP0_REG08__BADVADDR:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
register_name = "BadVAddr";
break;
-case 1:
+case CP0_REG08__BADINSTR:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
register_name = "BadInstr";
break;
-case 2:
+case CP0_REG08__BADINSTRP:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
register_name = "BadInstrP";
break;
-case 3:
+case CP0_REG08__BADINSTRX:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0x);
@@ -9289,19 +9289,19 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
-case 0:
+case CP0_REG08__BADVADDR:
/* ignored */
register_name = "BadVAddr";
break;
-case 1:
+case CP0_REG08__BADINSTR:
/* ignored */
register_name = "BadInstr";
break;
-case 2:
+case CP0_REG08__BADINSTRP:
/* ignored */
register_name = "BadInstrP";
break;
-case 3:
+case CP0_REG08__BADINSTRX:
/* ignored */
register_name = "BadInstrX";
break;
--
2.7.4
[Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019
From: Aleksandar Markovic The following changes since commit 1b142da5f82a8fcdc7783a418592de654d5c6052: target/mips: Clean up handling of CP0 register 0 (2019-08-29 11:50:18 +0200) are available in the git repository at: https://github.com/AMarkovic/qemu tags/mips-queue-aug-29-2019 for you to fetch changes up to abd4393d769d9fe2333b2e83e00f911a78475943: target/mips: Fix emulation of ST.W in system mode (2019-08-29 12:11:14 +0200) MIPS queue for August 29th, 2019 Highlights: - cleanup of handling of configuration register CP0 - fix for ST.W emulation (in system mode only) Aleksandar Markovic (31): target/mips: Clean up handling of CP0 register 0 target/mips: Clean up handling of CP0 register 1 target/mips: Clean up handling of CP0 register 2 target/mips: Clean up handling of CP0 register 3 target/mips: Clean up handling of CP0 register 4 target/mips: Clean up handling of CP0 register 5 target/mips: Clean up handling of CP0 register 6 target/mips: Clean up handling of CP0 register 7 target/mips: Clean up handling of CP0 register 8 target/mips: Clean up handling of CP0 register 9 target/mips: Clean up handling of CP0 register 10 target/mips: Clean up handling of CP0 register 11 target/mips: Clean up handling of CP0 register 12 target/mips: Clean up handling of CP0 register 13 target/mips: Clean up handling of CP0 register 14 target/mips: Clean up handling of CP0 register 15 target/mips: Clean up handling of CP0 register 16 target/mips: Clean up handling of CP0 register 17 target/mips: Clean up handling of CP0 register 18 target/mips: Clean up handling of CP0 register 19 target/mips: Clean up handling of CP0 register 20 target/mips: Clean up handling of CP0 register 23 target/mips: Clean up handling of CP0 register 24 target/mips: Clean up handling of CP0 register 25 target/mips: Clean up handling of CP0 register 26 target/mips: Clean up handling of CP0 register 27 target/mips: Clean up handling of CP0 register 28 target/mips: Clean up handling of CP0 register 29 target/mips: Clean up handling of CP0 register 30 target/mips: Clean up handling of CP0 register 31 target/mips: Fix emulation of ST.W in system mode target/mips/cpu.h | 113 - target/mips/op_helper.c | 16 +- target/mips/translate.c | 1142 --- 3 files changed, 685 insertions(+), 586 deletions(-) -- 2.7.4
[Qemu-devel] [PULL 11/31] target/mips: Clean up handling of CP0 register 10
From: Aleksandar Markovic
Clean up handling of CP0 register 10.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-12-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 8
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 50a7205..3797bdc 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -342,6 +342,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG10__ENTRYHI 0
#define CP0_REG10__GUESTCTL1 4
#define CP0_REG10__GUESTCTL2 5
+#define CP0_REG10__GUESTCTL3 6
/* CP0 Register 11 */
#define CP0_REG11__COMPARE 0
#define CP0_REG11__GUESTCTL0EXT4
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b79c58c..50863cf 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7155,7 +7155,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
-case 0:
+case CP0_REG10__ENTRYHI:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EntryHi";
@@ -7872,7 +7872,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
-case 0:
+case CP0_REG10__ENTRYHI:
gen_helper_mtc0_entryhi(cpu_env, arg);
register_name = "EntryHi";
break;
@@ -8631,7 +8631,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
-case 0:
+case CP0_REG10__ENTRYHI:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
register_name = "EntryHi";
break;
@@ -9333,7 +9333,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
-case 0:
+case CP0_REG10__ENTRYHI:
gen_helper_mtc0_entryhi(cpu_env, arg);
register_name = "EntryHi";
break;
--
2.7.4
[Qemu-devel] [PULL 08/31] target/mips: Clean up handling of CP0 register 7
From: Aleksandar Markovic
Clean up handling of CP0 register 7.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-9-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a914fe4..cf2ba5a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7086,7 +7086,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
-case 0:
+case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
@@ -7818,7 +7818,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
-case 0:
+case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
@@ -8563,7 +8563,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
-case 0:
+case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
@@ -9277,7 +9277,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
-case 0:
+case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
--
2.7.4
[Qemu-devel] [PULL 16/31] target/mips: Clean up handling of CP0 register 15
From: Aleksandar Markovic
Clean up handling of CP0 register 15.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-17-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 1 +
target/mips/translate.c | 20 ++--
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 2a9c6d5..8ecfdb3 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -367,6 +367,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG15__EBASE 1
#define CP0_REG15__CDMMBASE2
#define CP0_REG15__CMGCRBASE 3
+#define CP0_REG15__BEVVA 4
/* CP0 Register 16 */
#define CP0_REG16__CONFIG 0
#define CP0_REG16__CONFIG1 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index efedced..238066f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7223,17 +7223,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
-case 0:
+case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
-case 1:
+case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
-case 3:
+case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -7956,11 +7956,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
-case 0:
+case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
-case 1:
+case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
@@ -8697,16 +8697,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
-case 0:
+case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
-case 1:
+case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
-case 3:
+case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -9419,11 +9419,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
-case 0:
+case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
-case 1:
+case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
--
2.7.4
[Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4
From: Aleksandar Markovic
Clean up handling of CP0 register 4.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-6-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 2 ++
target/mips/translate.c | 36
2 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d5b7103..496872e 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -305,7 +305,9 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG03__TCOPT 7
/* CP0 Register 04 */
#define CP0_REG04__CONTEXT 0
+#define CP0_REG04__CONTEXTCONFIG 1
#define CP0_REG04__USERLOCAL 2
+#define CP0_REG04__XCONTEXTCONFIG 3
#define CP0_REG04__DBGCONTEXTID4
#define CP0_REG00__MMID5
/* CP0 Register 05 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 059f53e..9df59f1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6975,16 +6975,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
-case 0:
+case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
tcg_gen_ext32s_tl(arg, arg);
register_name = "Context";
break;
-case 1:
-/* gen_helper_mfc0_contextconfig(arg); - SmartMIPS ASE */
+case CP0_REG04__CONTEXTCONFIG:
+/* SmartMIPS ASE */
+/* gen_helper_mfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
-case 2:
+case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -7710,15 +7711,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
-case 0:
+case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
-case 1:
-//gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+case CP0_REG04__CONTEXTCONFIG:
+/* SmartMIPS ASE */
+/* gen_helper_mtc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
-case 2:
+case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -8455,15 +8457,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
-case 0:
+case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
register_name = "Context";
break;
-case 1:
-//gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
+case CP0_REG04__CONTEXTCONFIG:
+/* SmartMIPS ASE */
+/* gen_helper_dmfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
-case 2:
+case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -9168,15 +9171,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
-case 0:
+case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
-case 1:
-// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+case CP0_REG04__CONTEXTCONFIG:
+/* SmartMIPS ASE */
+/* gen_helper_dmtc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
-case 2:
+case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
--
2.7.4
[Qemu-devel] [PULL 13/31] target/mips: Clean up handling of CP0 register 12
From: Aleksandar Markovic
Clean up handling of CP0 register 12.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-14-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 3 +++
target/mips/translate.c | 32
2 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 3797bdc..061effb 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -350,6 +350,9 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG12__STATUS 0
#define CP0_REG12__INTCTL 1
#define CP0_REG12__SRSCTL 2
+#define CP0_REG12__SRSMAP 3
+#define CP0_REG12__VIEW_IPL4
+#define CP0_REG12__SRSMAP2 5
#define CP0_REG12__GUESTCTL0 6
#define CP0_REG12__GTOFFSET7
/* CP0 Register 13 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b5d5994..fb9c719 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7177,21 +7177,21 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
-case 0:
+case CP0_REG12__STATUS:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
-case 1:
+case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
-case 2:
+case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
-case 3:
+case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@@ -7893,7 +7893,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
-case 0:
+case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
@@ -7901,21 +7901,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Status";
break;
-case 1:
+case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
-case 2:
+case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
-case 3:
+case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
@@ -8652,21 +8652,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
-case 0:
+case CP0_REG12__STATUS:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
-case 1:
+case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
-case 2:
+case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
-case 3:
+case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@@ -9356,7 +9356,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
-case 0:
+case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
@@ -9364,21 +9364,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
ctx->base.is_jmp = DISAS_E
[Qemu-devel] [PULL 19/31] target/mips: Clean up handling of CP0 register 18
From: Aleksandar Markovic
Clean up handling of CP0 register 18.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-20-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 20 +---
target/mips/translate.c | 64 -
2 files changed, 44 insertions(+), 40 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d6405ad..d6ea111 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -192,14 +192,14 @@ typedef struct mips_def_t mips_def_t;
* Register 16 Register 17 Register 18 Register 19
* --- --- --- ---
*
- * 0 ConfigLLAddrWatchLo WatchHi
- * 1 Config1 MAAR WatchLo WatchHi
- * 2 Config2 MAARI WatchLo WatchHi
- * 3 Config3 WatchLo WatchHi
- * 4 Config4 WatchLo WatchHi
- * 5 Config5 WatchLo WatchHi
- * 6 WatchLo WatchHi
- * 7 WatchLo WatchHi
+ * 0 ConfigLLAddrWatchLo0 WatchHi
+ * 1 Config1 MAAR WatchLo1 WatchHi
+ * 2 Config2 MAARI WatchLo2 WatchHi
+ * 3 Config3 WatchLo3 WatchHi
+ * 4 Config4 WatchLo4 WatchHi
+ * 5 Config5 WatchLo5 WatchHi
+ * 6 WatchLo6 WatchHi
+ * 7 WatchLo7 WatchHi
*
*
* Register 20 Register 21 Register 22 Register 23
@@ -386,6 +386,10 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG18__WATCHLO11
#define CP0_REG18__WATCHLO22
#define CP0_REG18__WATCHLO33
+#define CP0_REG18__WATCHLO44
+#define CP0_REG18__WATCHLO55
+#define CP0_REG18__WATCHLO66
+#define CP0_REG18__WATCHLO77
/* CP0 Register 19 */
#define CP0_REG19__WATCHHI00
#define CP0_REG19__WATCHHI11
diff --git a/target/mips/translate.c b/target/mips/translate.c
index edeaaad..6a11e8d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7305,14 +7305,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG18__WATCHLO0:
+case CP0_REG18__WATCHLO1:
+case CP0_REG18__WATCHLO2:
+case CP0_REG18__WATCHLO3:
+case CP0_REG18__WATCHLO4:
+case CP0_REG18__WATCHLO5:
+case CP0_REG18__WATCHLO6:
+case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8040,14 +8040,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG18__WATCHLO0:
+case CP0_REG18__WATCHLO1:
+case CP0_REG18__WATCHLO2:
+case CP0_REG18__WATCHLO3:
+case CP0_REG18__WATCHLO4:
+case CP0_REG18__WATCHLO5:
+case CP0_REG18__WATCHLO6:
+case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8777,14 +8777,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG18__WATCHLO0:
+case CP0_REG18__WATCHLO1:
+case CP0_REG18__WATCHLO2:
+case CP0_REG18__WATCHLO3:
+case CP0_REG18__WATCHLO4:
+case CP0_REG18__WATCHLO5:
+case CP0_REG18__WATCHLO6:
+case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -9494,14 +9494,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-
[Qemu-devel] [PULL 21/31] target/mips: Clean up handling of CP0 register 20
From: Aleksandar Markovic
Clean up handling of CP0 register 20.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-22-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6d617f4..55b0005 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7341,7 +7341,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
-case 0:
+case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
@@ -8076,7 +8076,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
-case 0:
+case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
@@ -8813,7 +8813,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
-case 0:
+case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
register_name = "XContext";
@@ -9530,7 +9530,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
-case 0:
+case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
register_name = "XContext";
--
2.7.4
[Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5
From: Aleksandar Markovic
Clean up handling of CP0 register 5.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-7-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 6 +
target/mips/translate.c | 64 -
2 files changed, 38 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 496872e..ed1a974 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -313,6 +313,12 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 05 */
#define CP0_REG05__PAGEMASK0
#define CP0_REG05__PAGEGRAIN 1
+#define CP0_REG05__SEGCTL0 2
+#define CP0_REG05__SEGCTL1 3
+#define CP0_REG05__SEGCTL2 4
+#define CP0_REG05__PWBASE 5
+#define CP0_REG05__PWFIELD 6
+#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
/* CP0 Register 07 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9df59f1..19f86f2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6998,44 +6998,44 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
-case 0:
+case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
-case 1:
+case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
-case 2:
+case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl0";
break;
-case 3:
+case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl1";
break;
-case 4:
+case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl2";
break;
-case 5:
+case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
-case 6:
+case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
-case 7:
+case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@@ -7732,42 +7732,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
-case 0:
+case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask";
break;
-case 1:
+case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
break;
-case 2:
+case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0";
break;
-case 3:
+case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1";
break;
-case 4:
+case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2";
break;
-case 5:
+case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
-case 6:
+case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField";
break;
-case 7:
+case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize";
@@ -8478,41 +8478,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_05:
[Qemu-devel] [PULL 14/31] target/mips: Clean up handling of CP0 register 13
From: Aleksandar Markovic
Clean up handling of CP0 register 13.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-15-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 2 ++
target/mips/translate.c | 8
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 061effb..4fce05a 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -357,6 +357,8 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG12__GTOFFSET7
/* CP0 Register 13 */
#define CP0_REG13__CAUSE 0
+#define CP0_REG13__VIEW_RIPL 4
+#define CP0_REG13__NESTEDEXC 5
/* CP0 Register 14 */
#define CP0_REG14__EPC 0
/* CP0 Register 15 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fb9c719..4da08e1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7202,7 +7202,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
-case 0:
+case CP0_REG13__CAUSE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
register_name = "Cause";
break;
@@ -7928,7 +7928,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
-case 0:
+case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
/*
@@ -8677,7 +8677,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
-case 0:
+case CP0_REG13__CAUSE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
register_name = "Cause";
break;
@@ -9391,7 +9391,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
-case 0:
+case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
/*
--
2.7.4
[Qemu-devel] [PULL 26/31] target/mips: Clean up handling of CP0 register 27
From: Aleksandar Markovic
Clean up handling of CP0 register 27.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-27-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 20
1 file changed, 4 insertions(+), 16 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a8ea952..c969c25 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7466,10 +7466,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
+case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@@ -8224,10 +8221,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
+case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
@@ -8955,10 +8949,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
case CP0_REGISTER_27:
switch (sel) {
/* ignored */
-case 0:
-case 1:
-case 2:
-case 3:
+case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@@ -9694,10 +9685,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
+case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
--
2.7.4
[Qemu-devel] [PULL 25/31] target/mips: Clean up handling of CP0 register 26
From: Aleksandar Markovic
Clean up handling of CP0 register 26.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-26-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 2 +-
target/mips/translate.c | 8
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 168a6d7..40b7cc6 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -423,7 +423,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG25__PERFCTL36
#define CP0_REG25__PERFCNT37
/* CP0 Register 26 */
-#define CP0_REG00__ERRCTL 0
+#define CP0_REG26__ERRCTL 0
/* CP0 Register 27 */
#define CP0_REG27__CACHERR 0
/* CP0 Register 28 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 84aabf6..a8ea952 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7456,7 +7456,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
-case 0:
+case CP0_REG26__ERRCTL:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
register_name = "ErrCtl";
break;
@@ -8213,7 +8213,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
-case 0:
+case CP0_REG26__ERRCTL:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
@@ -8944,7 +8944,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
-case 0:
+case CP0_REG26__ERRCTL:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
register_name = "ErrCtl";
break;
@@ -9683,7 +9683,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
-case 0:
+case CP0_REG26__ERRCTL:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
--
2.7.4
[Qemu-devel] [PULL 22/31] target/mips: Clean up handling of CP0 register 23
From: Aleksandar Markovic
Clean up handling of CP0 register 23.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-23-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 6 +++
target/mips/translate.c | 126 +++-
2 files changed, 89 insertions(+), 43 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index b4866a5..168a6d7 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -405,6 +405,12 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 22 */
/* CP0 Register 23 */
#define CP0_REG23__DEBUG 0
+#define CP0_REG23__TRACECONTROL1
+#define CP0_REG23__TRACECONTROL2 2
+#define CP0_REG23__USERTRACEDATA1 3
+#define CP0_REG23__TRACEIBPC 4
+#define CP0_REG23__TRACEDBPC 5
+#define CP0_REG23__DEBUG2 6
/* CP0 Register 24 */
#define CP0_REG24__DEPC0
/* CP0 Register 25 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 55b0005..610631f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7371,25 +7371,34 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
-case 0:
+case CP0_REG23__DEBUG:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
register_name = "Debug";
break;
-case 1:
-//gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
+case CP0_REG23__TRACECONTROL:
+/* PDtrace support */
+/* gen_helper_mfc0_tracecontrol(arg); */
register_name = "TraceControl";
goto cp0_unimplemented;
-case 2:
-//gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
+case CP0_REG23__TRACECONTROL2:
+/* PDtrace support */
+/* gen_helper_mfc0_tracecontrol2(arg); */
register_name = "TraceControl2";
goto cp0_unimplemented;
-case 3:
-//gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
-register_name = "UserTraceData";
+case CP0_REG23__USERTRACEDATA1:
+/* PDtrace support */
+/* gen_helper_mfc0_usertracedata1(arg);*/
+register_name = "UserTraceData1";
goto cp0_unimplemented;
-case 4:
-//gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
-register_name = "TraceBPC";
+case CP0_REG23__TRACEIBPC:
+/* PDtrace support */
+/* gen_helper_mfc0_traceibpc(arg); */
+register_name = "TraceIBPC";
+goto cp0_unimplemented;
+case CP0_REG23__TRACEDBPC:
+/* PDtrace support */
+/* gen_helper_mfc0_tracedbpc(arg); */
+register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8105,38 +8114,49 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
-case 0:
+case CP0_REG23__DEBUG:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Debug";
break;
-case 1:
-//gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
+case CP0_REG23__TRACECONTROL:
+/* PDtrace support */
+/* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
register_name = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
-case 2:
-//gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support
*/
+case CP0_REG23__TRACECONTROL2:
+/* PDtrace support */
+/* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
register_name = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
-case 3:
+case CP0_REG23__USERTRACEDATA1:
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
-//gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support
*/
+/* PDtrace support */
+/* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
register_name = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
-case 4:
-//
[Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11
From: Aleksandar Markovic
Clean up handling of CP0 register 11.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-13-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 50863cf..b5d5994 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7166,7 +7166,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
-case 0:
+case CP0_REG11__COMPARE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
register_name = "Compare";
break;
@@ -7882,7 +7882,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
-case 0:
+case CP0_REG11__COMPARE:
gen_helper_mtc0_compare(cpu_env, arg);
register_name = "Compare";
break;
@@ -8641,7 +8641,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
-case 0:
+case CP0_REG11__COMPARE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
register_name = "Compare";
break;
@@ -9343,7 +9343,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
-case 0:
+case CP0_REG11__COMPARE:
gen_helper_mtc0_compare(cpu_env, arg);
register_name = "Compare";
break;
--
2.7.4
[Qemu-devel] [PULL 23/31] target/mips: Clean up handling of CP0 register 24
From: Aleksandar Markovic
Clean up handling of CP0 register 24.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-24-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 610631f..515d04c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7406,7 +7406,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
-case 0:
+case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
tcg_gen_ext32s_tl(arg, arg);
@@ -8164,7 +8164,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
-case 0:
+case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
@@ -8895,7 +8895,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
-case 0:
+case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
@@ -9634,7 +9634,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
-case 0:
+case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
--
2.7.4
[Qemu-devel] [PULL 17/31] target/mips: Clean up handling of CP0 register 16
From: Aleksandar Markovic
Clean up handling of CP0 register 16.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-18-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 3 ++-
target/mips/translate.c | 60 -
2 files changed, 32 insertions(+), 31 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 8ecfdb3..d6405ad 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -375,7 +375,8 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG16__CONFIG3 3
#define CP0_REG16__CONFIG4 4
#define CP0_REG16__CONFIG5 5
-#define CP0_REG00__CONFIG7 7
+#define CP0_REG16__CONFIG6 6
+#define CP0_REG16__CONFIG7 7
/* CP0 Register 17 */
#define CP0_REG17__LLADDR 0
#define CP0_REG17__MAAR1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 238066f..4808640 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7246,36 +7246,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
-case 0:
+case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
-case 1:
+case CP0_REG16__CONFIG1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
-case 2:
+case CP0_REG16__CONFIG2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
-case 3:
+case CP0_REG16__CONFIG3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
-case 4:
+case CP0_REG16__CONFIG4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
-case 5:
+case CP0_REG16__CONFIG5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
-case 6:
+case CP0_REG16__CONFIG6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
-case 7:
+case CP0_REG16__CONFIG7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@@ -7971,45 +7971,45 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
-case 0:
+case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
-case 1:
+case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
-case 2:
+case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
-case 3:
+case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
-case 4:
+case CP0_REG16__CONFIG4:
gen_helper_mtc0_config4(cpu_env, arg);
register_name = "Config4";
ctx->base.is_jmp = DISAS_STOP;
break;
-case 5:
+case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
-case 6:
+case CP0_REG16__CONFIG6:
/* ignored */
register_name = "Config6";
break;
-case 7:
+case CP0_REG16__CONFIG7:
/* ignored */
register_name = "Config7";
break;
@@ -8718,36 +8718,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
-case 0:
+case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
[Qemu-devel] [PULL 28/31] target/mips: Clean up handling of CP0 register 29
From: Aleksandar Markovic
Clean up handling of CP0 register 29.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-29-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 22 ++---
target/mips/translate.c | 64 -
2 files changed, 46 insertions(+), 40 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index de9e850..6defbea 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -233,12 +233,12 @@ typedef struct mips_def_t mips_def_t;
*
* 0 DataLoDataHiErrorEPC DESAVE
* 1 TagLo TagHi
- * 2 DataLo1 DataHi KScratch
- * 3 TagLo1TagHi KScratch
- * 4 DataLo2 DataHi KScratch
- * 5 TagLo2TagHi KScratch
- * 6 DataLo3 DataHi KScratch
- * 7 TagLo3TagHi KScratch
+ * 2 DataLo1 DataHi1 KScratch
+ * 3 TagLo1TagHi1 KScratch
+ * 4 DataLo2 DataHi2 KScratch
+ * 5 TagLo2TagHi2 KScratch
+ * 6 DataLo3 DataHi3 KScratch
+ * 7 TagLo3TagHi3 KScratch
*
*/
#define CP0_REGISTER_00 0
@@ -436,8 +436,14 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG28__TAGLO3 6
#define CP0_REG28__DATALO3 7
/* CP0 Register 29 */
-#define CP0_REG29__IDATAHI 1
-#define CP0_REG29__DDATAHI 3
+#define CP0_REG29__TAGHI 0
+#define CP0_REG29__DATAHI 1
+#define CP0_REG29__TAGHI1 2
+#define CP0_REG29__DATAHI1 3
+#define CP0_REG29__TAGHI2 4
+#define CP0_REG29__DATAHI2 5
+#define CP0_REG29__TAGHI3 6
+#define CP0_REG29__DATAHI3 7
/* CP0 Register 30 */
#define CP0_REG30__ERROREPC0
/* CP0 Register 31 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 032e3b0..6d6fda6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7501,17 +7501,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG29__TAGHI:
+case CP0_REG29__TAGHI1:
+case CP0_REG29__TAGHI2:
+case CP0_REG29__TAGHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG29__DATAHI:
+case CP0_REG29__DATAHI1:
+case CP0_REG29__DATAHI2:
+case CP0_REG29__DATAHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@@ -8251,17 +8251,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG29__TAGHI:
+case CP0_REG29__TAGHI1:
+case CP0_REG29__TAGHI2:
+case CP0_REG29__TAGHI3:
gen_helper_mtc0_taghi(cpu_env, arg);
register_name = "TagHi";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG29__DATAHI:
+case CP0_REG29__DATAHI1:
+case CP0_REG29__DATAHI2:
+case CP0_REG29__DATAHI3:
gen_helper_mtc0_datahi(cpu_env, arg);
register_name = "DataHi";
break;
@@ -8979,17 +8979,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG29__TAGHI:
+case CP0_REG29__TAGHI1:
+case CP0_REG29__TAGHI2:
+case CP0_REG29__TAGHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG29__DATAHI:
+case CP0_REG29__DATAHI1:
+case CP0_REG29__DATAHI2:
+case CP0_REG29__DATAHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@@ -9715,17 +9715,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
-case 0:
-case 2:
-case 4:
-
[Qemu-devel] [PULL 20/31] target/mips: Clean up handling of CP0 register 19
From: Aleksandar Markovic
Clean up handling of CP0 register 19.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-21-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 4
target/mips/translate.c | 64 -
2 files changed, 36 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index d6ea111..b4866a5 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -395,6 +395,10 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG19__WATCHHI11
#define CP0_REG19__WATCHHI22
#define CP0_REG19__WATCHHI33
+#define CP0_REG19__WATCHHI44
+#define CP0_REG19__WATCHHI55
+#define CP0_REG19__WATCHHI66
+#define CP0_REG19__WATCHHI77
/* CP0 Register 20 */
#define CP0_REG20__XCONTEXT0
/* CP0 Register 21 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6a11e8d..6d617f4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7323,14 +7323,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG19__WATCHHI0:
+case CP0_REG19__WATCHHI1:
+case CP0_REG19__WATCHHI2:
+case CP0_REG19__WATCHHI3:
+case CP0_REG19__WATCHHI4:
+case CP0_REG19__WATCHHI5:
+case CP0_REG19__WATCHHI6:
+case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -8058,14 +8058,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG19__WATCHHI0:
+case CP0_REG19__WATCHHI1:
+case CP0_REG19__WATCHHI2:
+case CP0_REG19__WATCHHI3:
+case CP0_REG19__WATCHHI4:
+case CP0_REG19__WATCHHI5:
+case CP0_REG19__WATCHHI6:
+case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -8795,14 +8795,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG19__WATCHHI0:
+case CP0_REG19__WATCHHI1:
+case CP0_REG19__WATCHHI2:
+case CP0_REG19__WATCHHI3:
+case CP0_REG19__WATCHHI4:
+case CP0_REG19__WATCHHI5:
+case CP0_REG19__WATCHHI6:
+case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -9512,14 +9512,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
-case 0:
-case 1:
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG19__WATCHHI0:
+case CP0_REG19__WATCHHI1:
+case CP0_REG19__WATCHHI2:
+case CP0_REG19__WATCHHI3:
+case CP0_REG19__WATCHHI4:
+case CP0_REG19__WATCHHI5:
+case CP0_REG19__WATCHHI6:
+case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi";
--
2.7.4
[Qemu-devel] [PULL 31/31] target/mips: Fix emulation of ST.W in system mode
From: Aleksandar Markovic
Order of arguments in helper_ret_stl_mmu() invocations was wrong,
apparently caused by a misplaced multiline copy-and-paste.
Fixes: 6decc57 ("target/mips: Fix MSA instructions ST. on big endian
host")
Signed-off-by: Aleksandar Markovic
Reviewed-by: Aleksandar Rikalo
Message-Id: <1567009239-11273-1-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/op_helper.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index f88a3ab..5b8bb20 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4692,15 +4692,15 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
ensure_writable_pages(env, addr, mmu_idx, GETPC());
#if !defined(CONFIG_USER_ONLY)
#if !defined(HOST_WORDS_BIGENDIAN)
-helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[0]);
-helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[1]);
-helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[2]);
-helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[3]);
+helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
#else
-helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[0]);
-helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[1]);
-helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[2]);
-helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[3]);
+helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
+helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
#endif
#else
#if !defined(HOST_WORDS_BIGENDIAN)
--
2.7.4
[Qemu-devel] [PULL 27/31] target/mips: Clean up handling of CP0 register 28
From: Aleksandar Markovic
Clean up handling of CP0 register 28.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-28-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 24 +++
target/mips/translate.c | 64 -
2 files changed, 46 insertions(+), 42 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 40b7cc6..de9e850 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -233,12 +233,12 @@ typedef struct mips_def_t mips_def_t;
*
* 0 DataLoDataHiErrorEPC DESAVE
* 1 TagLo TagHi
- * 2 DataLoDataHi KScratch
- * 3 TagLo TagHi KScratch
- * 4 DataLoDataHi KScratch
- * 5 TagLo TagHi KScratch
- * 6 DataLoDataHi KScratch
- * 7 TagLo TagHi KScratch
+ * 2 DataLo1 DataHi KScratch
+ * 3 TagLo1TagHi KScratch
+ * 4 DataLo2 DataHi KScratch
+ * 5 TagLo2TagHi KScratch
+ * 6 DataLo3 DataHi KScratch
+ * 7 TagLo3TagHi KScratch
*
*/
#define CP0_REGISTER_00 0
@@ -427,10 +427,14 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 27 */
#define CP0_REG27__CACHERR 0
/* CP0 Register 28 */
-#define CP0_REG28__ITAGLO 0
-#define CP0_REG28__IDATALO 1
-#define CP0_REG28__DTAGLO 2
-#define CP0_REG28__DDATALO 3
+#define CP0_REG28__TAGLO 0
+#define CP0_REG28__DATALO 1
+#define CP0_REG28__TAGLO1 2
+#define CP0_REG28__DATALO1 3
+#define CP0_REG28__TAGLO2 4
+#define CP0_REG28__DATALO2 5
+#define CP0_REG28__TAGLO3 6
+#define CP0_REG28__DATALO3 7
/* CP0 Register 29 */
#define CP0_REG29__IDATAHI 1
#define CP0_REG29__DDATAHI 3
diff --git a/target/mips/translate.c b/target/mips/translate.c
index c969c25..032e3b0 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7476,10 +7476,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG28__TAGLO:
+case CP0_REG28__TAGLO1:
+case CP0_REG28__TAGLO2:
+case CP0_REG28__TAGLO3:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState,
CP0_TagLo));
@@ -7488,10 +7488,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
}
register_name = "TagLo";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG28__DATALO:
+case CP0_REG28__DATALO1:
+case CP0_REG28__DATALO2:
+case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
register_name = "DataLo";
break;
@@ -8231,17 +8231,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG28__TAGLO:
+case CP0_REG28__TAGLO1:
+case CP0_REG28__TAGLO2:
+case CP0_REG28__TAGLO3:
gen_helper_mtc0_taglo(cpu_env, arg);
register_name = "TagLo";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG28__DATALO:
+case CP0_REG28__DATALO1:
+case CP0_REG28__DATALO2:
+case CP0_REG28__DATALO3:
gen_helper_mtc0_datalo(cpu_env, arg);
register_name = "DataLo";
break;
@@ -8959,17 +8959,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
-case 0:
-case 2:
-case 4:
-case 6:
+case CP0_REG28__TAGLO:
+case CP0_REG28__TAGLO1:
+case CP0_REG28__TAGLO2:
+case CP0_REG28__TAGLO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
register_name = "TagLo";
break;
-case 1:
-case 3:
-case 5:
-case 7:
+case CP0_REG28__DATALO:
+case CP0_REG28__DATALO1:
+case CP0_REG28__DATALO2:
+case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
[Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25
From: Aleksandar Markovic
Clean up handling of CP0 register 25.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-25-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 64 -
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 515d04c..84aabf6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7418,35 +7418,35 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
-case 0:
+case CP0_REG25__PERFCTL0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
register_name = "Performance0";
break;
-case 1:
+case CP0_REG25__PERFCNT0:
/* gen_helper_mfc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
-case 2:
+case CP0_REG25__PERFCTL1:
/* gen_helper_mfc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
-case 3:
+case CP0_REG25__PERFCNT1:
/* gen_helper_mfc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
-case 4:
+case CP0_REG25__PERFCTL2:
/* gen_helper_mfc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
-case 5:
+case CP0_REG25__PERFCNT2:
/* gen_helper_mfc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
-case 6:
+case CP0_REG25__PERFCTL3:
/* gen_helper_mfc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
-case 7:
+case CP0_REG25__PERFCNT3:
/* gen_helper_mfc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -8175,35 +8175,35 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
-case 0:
+case CP0_REG25__PERFCTL0:
gen_helper_mtc0_performance0(cpu_env, arg);
register_name = "Performance0";
break;
-case 1:
+case CP0_REG25__PERFCNT0:
/* gen_helper_mtc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
-case 2:
+case CP0_REG25__PERFCTL1:
/* gen_helper_mtc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
-case 3:
+case CP0_REG25__PERFCNT1:
/* gen_helper_mtc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
-case 4:
+case CP0_REG25__PERFCTL2:
/* gen_helper_mtc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
-case 5:
+case CP0_REG25__PERFCNT2:
/* gen_helper_mtc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
-case 6:
+case CP0_REG25__PERFCTL3:
/* gen_helper_mtc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
-case 7:
+case CP0_REG25__PERFCNT3:
/* gen_helper_mtc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -8906,35 +8906,35 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
-case 0:
+case CP0_REG25__PERFCTL0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
register_name = "Performance0";
break;
-case 1:
+case CP0_REG25__PERFCNT0:
/* gen_helper_dmfc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
-case 2:
+case CP0_REG25__PERFCTL1:
/* gen_helper_dmfc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
-case 3:
+case CP0_REG25__PERFCNT1:
/* gen_helper_dmfc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
-case 4:
+case CP0_REG25__PERFCTL2:
/* gen_helper_dmfc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
-case 5:
+case CP0_REG25__PERFCNT2:
Re: [Qemu-devel] [Qemu-ppc] [patch-for-4.2 PATCH v11 0/6] target-ppc/spapr: Add FWNMI support in QEMU for PowerKVM guests
On Thursday 29 August 2019 03:51 PM, Greg Kurz wrote: > On Wed, 14 Aug 2019 11:40:50 +0530 > Aravinda Prasad wrote: > >> This patch set adds support for FWNMI in PowerKVM guests. >> >> System errors such as SLB multihit and memory errors >> that cannot be corrected by hardware is passed on to >> the kernel for handling by raising machine check >> exception (an NMI). Upon such machine check exceptions, >> if the address in error belongs to guest then KVM >> invokes guests' 0x200 interrupt vector if the guest >> is not FWNMI capable. For FWNMI capable guest >> KVM passes the control to QEMU by exiting the guest. >> >> This patch series adds functionality to QEMU to pass >> on such machine check exceptions to the FWNMI capable >> guest kernel by building an error log and invoking >> the guest registered machine check handling routine. >> >> The KVM changes are now part of the upstream kernel >> (commit e20bbd3d). This series contain QEMU changes. >> >> Change Log v11: >> - Moved FWNMI SPAPR cap defaults to 4.2 class option >> - Fixed issues with handling fwnmi KVM capability >> > > Hi Aravinda, > > I'm afraid this series needs rebasing. It doesn't apply > cleanly on current ppc-for-4.2 (SHA1 b1e8156743). This was based on the latest 4.2 at the time of posting (14th Aug). Meanwhile may be due to changes to 4.2 it is not applying cleanly. I will rebase it to the latest 4.2 and post it again. Regards, Aravinda > > Cheers, > > -- > Greg > >> Change Log v10: >> - Reshuffled the patch sequence + minor fixes >> >> Change Log v9: >> - Fixed kvm cap and spapr cap issues >> >> Change Log v8: >> - Added functionality to check FWNMI capability during >> VM migration >> --- >> >> Aravinda Prasad (6): >> Wrapper function to wait on condition for the main loop mutex >> ppc: spapr: Introduce FWNMI capability >> target/ppc: Handle NMI guest exit >> target/ppc: Build rtas error log upon an MCE >> ppc: spapr: Handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS >> calls >> migration: Include migration support for machine check handling >> >> >> cpus.c |5 + >> hw/ppc/spapr.c | 78 + >> hw/ppc/spapr_caps.c | 29 + >> hw/ppc/spapr_events.c| 268 >> ++ >> hw/ppc/spapr_rtas.c | 78 + >> include/hw/ppc/spapr.h | 25 >> include/qemu/main-loop.h |8 + >> target/ppc/cpu.h |1 >> target/ppc/kvm.c | 38 +++ >> target/ppc/kvm_ppc.h | 13 ++ >> target/ppc/trace-events |1 >> 11 files changed, 542 insertions(+), 2 deletions(-) >> >> -- >> Signature > > -- Regards, Aravinda
[Qemu-devel] [PULL 18/31] target/mips: Clean up handling of CP0 register 17
From: Aleksandar Markovic
Clean up handling of CP0 register 17.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-19-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4808640..edeaaad 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6669,12 +6669,12 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr),
ctx->CP0_LLAddr_shift);
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfhc0_maar(arg, cpu_env);
register_name = "MAAR";
@@ -6751,7 +6751,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
/*
* LLAddr is read-only (the only exception is bit 0 if LLB is
* supported); the CP0_LLAddr_rw_bitmask does not seem to be
@@ -6760,7 +6760,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
*/
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mthc0_maar(cpu_env, arg);
register_name = "MAAR";
@@ -7285,16 +7285,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
gen_helper_mfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
-case 2:
+case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -8020,16 +8020,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
-case 2:
+case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
@@ -8757,16 +8757,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
gen_helper_dmfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_dmfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
-case 2:
+case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -9474,16 +9474,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
-case 0:
+case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
-case 1:
+case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
-case 2:
+case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
--
2.7.4
Re: [Qemu-devel] [PATCH 0/2] git.orderfile: Order Python/shell scripts before unordered files
On 8/29/19 5:05 AM, Philippe Mathieu-Daudé wrote: > This series update the git.orderfile to order Python and shell > scripts before unordered files. > This is particularly useful for changes in tests/qemu-iotests. > > Regards, > > Phil. > > Philippe Mathieu-Daudé (2): > scripts/git.orderfile: Order Python files before unordered ones > scripts/git.orderfile: Order shell scripts before unordered files > Reviewed-by: Eric Blake -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3226 Virtualization: qemu.org | libvirt.org signature.asc Description: OpenPGP digital signature
Re: [Qemu-devel] [Qemu-ppc] [patch-for-4.2 PATCH v11 0/6] target-ppc/spapr: Add FWNMI support in QEMU for PowerKVM guests
On Thu, 29 Aug 2019 16:08:53 +0530 Aravinda Prasad wrote: > > > On Thursday 29 August 2019 03:51 PM, Greg Kurz wrote: > > On Wed, 14 Aug 2019 11:40:50 +0530 > > Aravinda Prasad wrote: > > > >> This patch set adds support for FWNMI in PowerKVM guests. > >> > >> System errors such as SLB multihit and memory errors > >> that cannot be corrected by hardware is passed on to > >> the kernel for handling by raising machine check > >> exception (an NMI). Upon such machine check exceptions, > >> if the address in error belongs to guest then KVM > >> invokes guests' 0x200 interrupt vector if the guest > >> is not FWNMI capable. For FWNMI capable guest > >> KVM passes the control to QEMU by exiting the guest. > >> > >> This patch series adds functionality to QEMU to pass > >> on such machine check exceptions to the FWNMI capable > >> guest kernel by building an error log and invoking > >> the guest registered machine check handling routine. > >> > >> The KVM changes are now part of the upstream kernel > >> (commit e20bbd3d). This series contain QEMU changes. > >> > >> Change Log v11: > >> - Moved FWNMI SPAPR cap defaults to 4.2 class option > >> - Fixed issues with handling fwnmi KVM capability > >> > > > > Hi Aravinda, > > > > I'm afraid this series needs rebasing. It doesn't apply > > cleanly on current ppc-for-4.2 (SHA1 b1e8156743). > > This was based on the latest 4.2 at the time of posting (14th Aug). I was on vacation at that time but you're probably right. > Meanwhile may be due to changes to 4.2 it is not applying cleanly. I > will rebase it to the latest 4.2 and post it again. > Thanks ! > Regards, > Aravinda > > > > > Cheers, > > > > -- > > Greg > > > >> Change Log v10: > >> - Reshuffled the patch sequence + minor fixes > >> > >> Change Log v9: > >> - Fixed kvm cap and spapr cap issues > >> > >> Change Log v8: > >> - Added functionality to check FWNMI capability during > >> VM migration > >> --- > >> > >> Aravinda Prasad (6): > >> Wrapper function to wait on condition for the main loop mutex > >> ppc: spapr: Introduce FWNMI capability > >> target/ppc: Handle NMI guest exit > >> target/ppc: Build rtas error log upon an MCE > >> ppc: spapr: Handle "ibm,nmi-register" and "ibm,nmi-interlock" RTAS > >> calls > >> migration: Include migration support for machine check handling > >> > >> > >> cpus.c |5 + > >> hw/ppc/spapr.c | 78 + > >> hw/ppc/spapr_caps.c | 29 + > >> hw/ppc/spapr_events.c| 268 > >> ++ > >> hw/ppc/spapr_rtas.c | 78 + > >> include/hw/ppc/spapr.h | 25 > >> include/qemu/main-loop.h |8 + > >> target/ppc/cpu.h |1 > >> target/ppc/kvm.c | 38 +++ > >> target/ppc/kvm_ppc.h | 13 ++ > >> target/ppc/trace-events |1 > >> 11 files changed, 542 insertions(+), 2 deletions(-) > >> > >> -- > >> Signature > > > > >
[Qemu-devel] [PULL 29/31] target/mips: Clean up handling of CP0 register 30
From: Aleksandar Markovic
Clean up handling of CP0 register 30.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-30-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6d6fda6..93f7a20 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7521,7 +7521,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
-case 0:
+case CP0_REG30__ERROREPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "ErrorEPC";
@@ -8272,7 +8272,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
-case 0:
+case CP0_REG30__ERROREPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
@@ -8999,7 +8999,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
-case 0:
+case CP0_REG30__ERROREPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
@@ -9736,7 +9736,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
-case 0:
+case CP0_REG30__ERROREPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
--
2.7.4
[Qemu-devel] [PATCH] virtiofsd: add man page
Signed-off-by: Stefan Hajnoczi
---
Makefile | 7 +++
contrib/virtiofsd/virtiofsd.texi | 85
2 files changed, 92 insertions(+)
create mode 100644 contrib/virtiofsd/virtiofsd.texi
diff --git a/Makefile b/Makefile
index a3dfdd6fa8..cc18025753 100644
--- a/Makefile
+++ b/Makefile
@@ -334,6 +334,9 @@ DOCS+=docs/qemu-cpu-models.7
ifdef CONFIG_VIRTFS
DOCS+=fsdev/virtfs-proxy-helper.1
endif
+ifdef CONFIG_LINUX
+DOCS+=contrib/virtiofsd/virtiofsd.1
+endif
ifdef CONFIG_TRACE_SYSTEMTAP
DOCS+=scripts/qemu-trace-stap.1
endif
@@ -834,6 +837,9 @@ ifdef CONFIG_VIRTFS
$(INSTALL_DIR) "$(DESTDIR)$(mandir)/man1"
$(INSTALL_DATA) fsdev/virtfs-proxy-helper.1 "$(DESTDIR)$(mandir)/man1"
endif
+ifdef CONFIG_LINUX
+ $(INSTALL_DATA) contrib/virtiofsd.1 "$(DESTDIR)$(mandir)/man1"
+endif
install-datadir:
$(INSTALL_DIR) "$(DESTDIR)$(qemu_datadir)"
@@ -1018,6 +1024,7 @@ qemu.1: qemu-doc.texi qemu-options.texi qemu-monitor.texi
qemu-monitor-info.texi
qemu.1: qemu-option-trace.texi
qemu-img.1: qemu-img.texi qemu-option-trace.texi qemu-img-cmds.texi
fsdev/virtfs-proxy-helper.1: fsdev/virtfs-proxy-helper.texi
+contrib/virtiofsd/virtiofsd.1: contrib/virtiofsd/virtiofsd.texi
qemu-nbd.8: qemu-nbd.texi qemu-option-trace.texi
qemu-ga.8: qemu-ga.texi
docs/qemu-block-drivers.7: docs/qemu-block-drivers.texi
diff --git a/contrib/virtiofsd/virtiofsd.texi b/contrib/virtiofsd/virtiofsd.texi
new file mode 100644
index 00..eec7fbf4e6
--- /dev/null
+++ b/contrib/virtiofsd/virtiofsd.texi
@@ -0,0 +1,85 @@
+@example
+@c man begin SYNOPSIS
+@command{virtiofsd} [OPTION]
@option{--socket-path=}@var{path}|@option{--fd=}@var{fdnum} @option{-o
source=}@var{path}
+@c man end
+@end example
+
+@c man begin DESCRIPTION
+
+Share a host directory tree with a guest through a virtio-fs device. This
+program is a vhost-user backend that implements the virtio-fs device. Each
+virtio-fs device instance requires its own virtiofsd process.
+
+This program is designed to work with QEMU's @code{--device vhost-user-fs-pci}
+but should work with any virtual machine monitor (VMM) that supports
+vhost-user. See the EXAMPLES section below.
+
+This program must be run as the root user. Upon startup the program will
+switch into a new file system namespace with the shared directory tree as its
+root. This prevents "file system escapes" due to symlinks and other file
+system objects that might lead to files outside the shared directory. The
+program also sandboxes itself using seccomp(2) to prevent ptrace(2) and other
+vectors that could allow an attacker to compromise the system after gaining
+control of the virtiofsd process.
+
+@c man end
+
+@c man begin OPTIONS
+@table @option
+@item -h, --help
+Print help.
+@item -V, --version
+Print version.
+@item -d, -o debug
+Enable debug output.
+@item --syslog
+Print log messages to syslog instead of stderr.
+@item -o log_level=@var{level}
+Print only log messages matching @var{level} or more severe. @var{level} is
+one of @code{err}, @code{warn}, @code{info}, or @code{debug}. The default is
+@var{info}.
+@item -o source=@var{path}
+Share host directory tree located at @var{path}. This option is required.
+@item --socket-path=@var{path}, -o vhost_user_socket=@var{path}
+Listen on vhost-user UNIX domain socket at @var{path}.
+@item --fd=@var{fdnum}
+Accept connections from vhost-user UNIX domain socket file descriptor
@var{fdnum}. The file descriptor must already be listening for connections.
+@item --thread-pool-size=@var{num}
+Restrict the number of worker threads per request queue to @var{num}. The
default is 64.
+@item --cache=@code{none}|@code{auto}|@code{always}
+Select the desired trade-off between coherency and performance. @code{none}
+forbids the FUSE client from caching to achieve best coherency at the cost of
+performance. @code{auto} acts similar to NFS with a 1 second metadata cache
+timeout. @code{always} sets a long cache lifetime at the expense of coherency.
+@item --writeback
+Enable writeback cache, allowing the FUSE client to buffer and merge write
requests.
+@end table
+@c man end
+
+@c man begin EXAMPLES
+Export @code{/var/lib/fs/vm001/} on vhost-user UNIX domain socket
@code{/var/run/vm001-vhost-fs.sock}:
+
+@example
+host# virtiofsd --socket-path=/var/run/vm001-vhost-fs.sock -o
source=/var/lib/fs/vm001
+host# qemu-system-x86_64 \
+-chardev socket,id=char0,path=/var/run/vm001-vhost-fs.sock \
+-device vhost-user-fs-pci,chardev=char0,tag=myfs \
+-object memory-backend-file,id=mem,size=4G,mem-path=/dev/shm,share=on \
+-numa node,memdev=mem \
+...
+guest# mount -t virtio_fs \
+-o
default_permissions,allow_other,user_id=0,group_id=0,rootmode=04,dax \
+myfs /mnt
+@end example
+@c man end
+
+@ignore
+@setfilename virtiofsd
+@settitle QEMU virtio-fs shared file system daemon
+
+@c man begin AUTHOR
+Copyright (C) 2019 Red Hat, Inc.
+This is free software; see the
[Qemu-devel] [PULL 30/31] target/mips: Clean up handling of CP0 register 31
From: Aleksandar Markovic
Clean up handling of CP0 register 31.
Reviewed-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Message-Id: <1567009614-12438-31-git-send-email-aleksandar.marko...@rt-rk.com>
---
target/mips/cpu.h | 2 +-
target/mips/translate.c | 56 -
2 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 6defbea..ca00f41 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -613,7 +613,6 @@ struct CPUMIPSState {
* CP0 Register 4
*/
target_ulong CP0_Context;
-target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
int32_t CP0_MemoryMapID;
/*
* CP0 Register 5
@@ -1024,6 +1023,7 @@ struct CPUMIPSState {
* CP0 Register 31
*/
int32_t CP0_DESAVE;
+target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
/* We waste some space so we can handle shadow registers like TCs. */
TCState tcs[MIPS_SHADOW_SET_MAX];
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 93f7a20..f6d1424 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7532,17 +7532,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
-case 0:
+case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG31__KSCRATCH1:
+case CP0_REG31__KSCRATCH2:
+case CP0_REG31__KSCRATCH3:
+case CP0_REG31__KSCRATCH4:
+case CP0_REG31__KSCRATCH5:
+case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -8282,17 +8282,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
-case 0:
+case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG31__KSCRATCH1:
+case CP0_REG31__KSCRATCH2:
+case CP0_REG31__KSCRATCH3:
+case CP0_REG31__KSCRATCH4:
+case CP0_REG31__KSCRATCH5:
+case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -9009,17 +9009,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
-case 0:
+case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG31__KSCRATCH1:
+case CP0_REG31__KSCRATCH2:
+case CP0_REG31__KSCRATCH3:
+case CP0_REG31__KSCRATCH4:
+case CP0_REG31__KSCRATCH5:
+case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -9746,17 +9746,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
-case 0:
+case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
-case 2:
-case 3:
-case 4:
-case 5:
-case 6:
-case 7:
+case CP0_REG31__KSCRATCH1:
+case CP0_REG31__KSCRATCH2:
+case CP0_REG31__KSCRATCH3:
+case CP0_REG31__KSCRATCH4:
+case CP0_REG31__KSCRATCH5:
+case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
--
2.7.4
Re: [Qemu-devel] [PATCH v6 1/6] iotests: allow Valgrind checking all QEMU processes
On 29/08/2019 03:30, Eric Blake wrote:
> On 8/28/19 5:58 PM, John Snow wrote:
>
>>> +++ b/tests/qemu-iotests/common.rc
>>> @@ -60,61 +60,132 @@ if ! . ./common.config
>>> exit 1
>>> fi
>>>
>>> +# Unset the variables to turn Valgrind off for specific processes, e.g.
>
> That's not unsetting, that's setting to the empty string.
>
Thanks Eric, I will make the correction of the comment. Any string other
than "y", including the empty one, fits.
>>> +# $ VALGRIND_QEMU_IO= ./check -qcow2 -valgrind 015
>>> +
>>> +: ${VALGRIND_QEMU_VM='y'}
>>> +: ${VALGRIND_QEMU_IMG='y'}
>>> +: ${VALGRIND_QEMU_IO='y'}
>>> +: ${VALGRIND_QEMU_NBD='y'}
>>> +: ${VALGRIND_QEMU_VXHS='y'}
>>> +
>>
I am going to make the change:
: ${VALGRIND_QEMU_VM=$VALGRIND_QEMU}
: ${VALGRIND_QEMU_IMG=$VALGRIND_QEMU}
: ${VALGRIND_QEMU_IO=$VALGRIND_QEMU}
: ${VALGRIND_QEMU_NBD=$VALGRIND_QEMU}
: ${VALGRIND_QEMU_VXHS=$VALGRIND_QEMU}
and get rid of the local VALGRIND_ON="${VALGRIND_QEMU}"
so that the code will be optimized.
>> I have to admit to you that I'm not familiar with this trick. I'm
>> looking it up and I see := documented, but not = alone.
>
> It's been a repeated complaint to the bash developer that the manual is
> doing a disservice to its users by not documenting ${var=val} in an
> easily searchable form. It IS documented, but only by virtue of
> ${var:=val} occurring under a section header that states:
>
> When not performing substring expansion, using the forms
> documented
> below (e.g., :-), bash tests for a parameter that is unset or
> null.
> Omitting the colon results in a test only for a parameter
> that is
> unset.
>
> So the choice is whether you want to special case a variable set to an
> empty string the same as an unset variable, or the same as a variable
> with a non-empty value.
>
Thank you all for your reviews and comments. The purpose why I omitted
the colon is to allow a user writing the shorter command syntax like
$ VALGRIND_QEMU_IO= ./check -valgrind
rather than
$ VALGRIND_QEMU_IO=" 'no' or 'off' or else anything other than 'y' "
./check -valgrind
so, no need to strike the Shift key twice and guess at what else is
acceptable to type )))
The variable default value 'y' looks good to me to implement the new
functionality that is compatible with the existing one when we just set
the '-valgrind' switch. The general idea behind using the Valgrind is to
make a careful search for memory issues. Once found, a user can tune the
particular test with extra variables to save their development/testing
time as John suggested. Also, no need to specify all the five long name
variables each time a user writes the command if default values aren't set.
I am flexible to make a change that is good for all. So, what solution
will we come to?
Andrey
>>
>> It doesn't seem documented here at all:
>> https://www.gnu.org/software/bash/manual/html_node/Shell-Parameter-Expansion.html
>>
>> I see it here, though:
>> https://www.tldp.org/LDP/abs/html/parameter-substitution.html
>>
>> And it seems to work, but I'm not sure if this works with BSD or OSX's
>> sh. I see Eric comment on that compatibility a lot, so maybe I'll let
>> him chime in.
>
> It's quite portable; POSIX requires it, and autoconf relies on it.
>
--
With the best regards,
Andrey Shinkevich
[Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
From: He Zhe
libgcrypt may also be controlled by pkg-config, this patch adds pkg-config
handling for libgcrypt.
Signed-off-by: He Zhe
---
configure | 48
1 file changed, 40 insertions(+), 8 deletions(-)
diff --git a/configure b/configure
index e44e454..0f362a7 100755
--- a/configure
+++ b/configure
@@ -2875,6 +2875,30 @@ has_libgcrypt() {
return 0
}
+has_libgcrypt_pkgconfig() {
+if ! has $pkg_config ; then
+return 1
+fi
+
+if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then
+return 1
+fi
+
+if test -n "$cross_prefix" ; then
+host=$($pkg_config --variable=host libgcrypt)
+if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then
+print_error "host($host) does not match
cross_prefix($cross_prefix)"
+return 1
+fi
+fi
+
+if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then
+print_error "libgcrypt version is $($pkg_config --modversion
libgcrypt)"
+return 1
+fi
+
+return 0
+}
if test "$nettle" != "no"; then
pass="no"
@@ -2902,7 +2926,14 @@ fi
if test "$gcrypt" != "no"; then
pass="no"
-if has_libgcrypt; then
+if has_libgcrypt_pkgconfig; then
+gcrypt_cflags=$($pkg_config --cflags libgcrypt)
+if test "$static" = "yes" ; then
+gcrypt_libs=$($pkg_config --libs --static libgcrypt)
+else
+gcrypt_libs=$($pkg_config --libs libgcrypt)
+fi
+elif has_libgcrypt; then
gcrypt_cflags=$(libgcrypt-config --cflags)
gcrypt_libs=$(libgcrypt-config --libs)
# Debian has removed -lgpg-error from libgcrypt-config
@@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then
then
gcrypt_libs="$gcrypt_libs -lgpg-error"
fi
+fi
-# Link test to make sure the given libraries work (e.g for static).
-write_c_skeleton
-if compile_prog "" "$gcrypt_libs" ; then
-LIBS="$gcrypt_libs $LIBS"
-QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
-pass="yes"
-fi
+# Link test to make sure the given libraries work (e.g for static).
+write_c_skeleton
+if compile_prog "" "$gcrypt_libs" ; then
+ LIBS="$gcrypt_libs $LIBS"
+ QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
+ pass="yes"
fi
+
if test "$pass" = "yes"; then
gcrypt="yes"
cat > $TMPC << EOF
--
2.7.4
Re: [Qemu-devel] [Qemu-block] [PATCH 0/2] git.orderfile: Order Python/shell scripts before unordered files
On Thu, Aug 29, 2019 at 12:05:19PM +0200, Philippe Mathieu-Daudé wrote: > This series update the git.orderfile to order Python and shell > scripts before unordered files. > This is particularly useful for changes in tests/qemu-iotests. > > Regards, > > Phil. > > Philippe Mathieu-Daudé (2): > scripts/git.orderfile: Order Python files before unordered ones > scripts/git.orderfile: Order shell scripts before unordered files > > scripts/git.orderfile | 5 + > 1 file changed, 5 insertions(+) Reviewed-by: Stefano Garzarella Thanks, Stefano
Re: [Qemu-devel] [PATCH v9 03/13] block/backup: introduce BlockCopyState
Thanks for reviewing!
28.08.2019 18:59, Max Reitz wrote:
> On 26.08.19 18:13, Vladimir Sementsov-Ogievskiy wrote:
>> Split copying code part from backup to "block-copy", including separate
>> state structure and function renaming. This is needed to share it with
>> backup-top filter driver in further commits.
>>
>> Notes:
>>
>> 1. As BlockCopyState keeps own BlockBackend objects, remaining
>
> I suppose these should be BdrvChild objects at some point, but doing it
> now would just mean effectively duplicating code from block-backend.c.
> (“now” = before we have a backup-top filter to attach the children to.)
How much is it bad to not do it, but leave them to be block-backends in
block-copy
state? They'll connected anyway through the job, as they all are in job.nodes.
We have block-backends in jobs currently, is it bad?
>
>> job->common.blk users only use it to get bs by blk_bs() call, so clear
>> job->commen.blk permissions set in block_job_create.
>>
>> 2. Rename s/initializing_bitmap/skip_unallocated/ to sound a bit better
>> as interface to BlockCopyState
>>
>> 3. Split is not very clean: there left some duplicated fields, backup
>
> Are there any but cluster_size and len (and source, in a sense)?
Seems no more
>
>> code uses some BlockCopyState fields directly, let's postpone it for
>> further improvements and keep this comment simpler for review.
>>
>> Signed-off-by: Vladimir Sementsov-Ogievskiy
>> ---
>> block/backup.c | 324 +++--
>> block/trace-events | 12 +-
>> 2 files changed, 200 insertions(+), 136 deletions(-)
>>
>> diff --git a/block/backup.c b/block/backup.c
>> index 13a1d80157..f52ac622e0 100644
>> --- a/block/backup.c
>> +++ b/block/backup.c
>> @@ -35,12 +35,35 @@ typedef struct CowRequest {
>> CoQueue wait_queue; /* coroutines blocked on this request */
>> } CowRequest;
>>
>> +/*
>> + * ProgressCallbackFunc
>> + *
>> + * Called when some progress is done in context of BlockCopyState:
>> + * 1. When some bytes copied, called with @bytes > 0.
>> + * 2. When some bytes resetted from copy_bitmap, called with @bytes = 0
>> (user
>
> *reset
>
>> + * may recalculate remaining bytes from copy_bitmap dirty count.
>> + */
>> +typedef void (*ProgressCallbackFunc)(int64_t bytes, void *opaque);
>
> Maybe there should be two callbacks instead, one for “We’ve actively
> made progress” (bytes > 0) and one for “The expected length has changed”
> (bytes == 0)?
I thought, that there are already too many parameters in block_copy_state_new().
But I agree with you, as actually it led to two callbacks in a one with just
if-else to distinguish them. Will do.
>
>> +typedef struct BlockCopyState {
>> +BlockBackend *source;
>> +BlockBackend *target;
>> +BdrvDirtyBitmap *copy_bitmap;
>> +int64_t cluster_size;
>> +bool use_copy_range;
>> +int64_t copy_range_size;
>> +uint64_t len;
>> +
>> +BdrvRequestFlags write_flags;
>> +bool skip_unallocated;
>
> The rename seems reasonable, although I think this should get a comment,
> because it doesn’t mean just to skip unallocated clusters; it also means
> to clear unallocated clusters from the bitmap.
>
>> +
>> +ProgressCallbackFunc progress_callback;
>> +void *progress_opaque;
>> +} BlockCopyState;
>> +
>> typedef struct BackupBlockJob {
>> BlockJob common;
>> -BlockBackend *target;
>>
>> BdrvDirtyBitmap *sync_bitmap;
>> -BdrvDirtyBitmap *copy_bitmap;
>>
>> MirrorSyncMode sync_mode;
>> BitmapSyncMode bitmap_mode;
>
> [...]
>
>> @@ -99,9 +118,83 @@ static void cow_request_end(CowRequest *req)
>> qemu_co_queue_restart_all(&req->wait_queue);
>> }
>>
>> +static void block_copy_state_free(BlockCopyState *s)
>> +{
>> +if (!s) {
>> +return;
>> +}
>> +
>> +bdrv_release_dirty_bitmap(blk_bs(s->source), s->copy_bitmap);
>> +blk_unref(s->source);
>> +s->source = NULL;
>> +blk_unref(s->target);
>> +s->target = NULL;
>
> I’m not quite sure why you NULL these pointers when you free the whole
> object next anyway.
it is for backup_drain, I'm afraid of some yield during blk_unref (and seems
it's unsafe
anyway, as I zero reference after calling blk_unref). Anyway,
backup_drain will be dropped in "[PATCH v3] job: drop job_drain", I'll drop
"= NULL" here now and workaround backup_drain in backup_clean with corresponding
comment.
>
>> +g_free(s);
>> +}
>> +
>> +static BlockCopyState *block_copy_state_new(
>> +BlockDriverState *source, BlockDriverState *target,
>> +int64_t cluster_size, BdrvRequestFlags write_flags,
>> +ProgressCallbackFunc progress_callback, void *progress_opaque,
>> +Error **errp)
>> +{
>> +BlockCopyState *s;
>> +int ret;
>> +uint64_t no_resize = BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE |
>> + BLK_PERM_WRITE_UNCHANGED | BLK_PERM_GRAPH_MOD;
>> +BdrvDirtyBitmap *copy_bitmap =
>> +
[Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
From: He Zhe
libgcrypt may also be controlled by pkg-config, this patch adds pkg-config
handling for libgcrypt.
Signed-off-by: He Zhe
---
configure | 48
1 file changed, 40 insertions(+), 8 deletions(-)
diff --git a/configure b/configure
index e44e454..0f362a7 100755
--- a/configure
+++ b/configure
@@ -2875,6 +2875,30 @@ has_libgcrypt() {
return 0
}
+has_libgcrypt_pkgconfig() {
+if ! has $pkg_config ; then
+return 1
+fi
+
+if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then
+return 1
+fi
+
+if test -n "$cross_prefix" ; then
+host=$($pkg_config --variable=host libgcrypt)
+if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then
+print_error "host($host) does not match
cross_prefix($cross_prefix)"
+return 1
+fi
+fi
+
+if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then
+print_error "libgcrypt version is $($pkg_config --modversion
libgcrypt)"
+return 1
+fi
+
+return 0
+}
if test "$nettle" != "no"; then
pass="no"
@@ -2902,7 +2926,14 @@ fi
if test "$gcrypt" != "no"; then
pass="no"
-if has_libgcrypt; then
+if has_libgcrypt_pkgconfig; then
+gcrypt_cflags=$($pkg_config --cflags libgcrypt)
+if test "$static" = "yes" ; then
+gcrypt_libs=$($pkg_config --libs --static libgcrypt)
+else
+gcrypt_libs=$($pkg_config --libs libgcrypt)
+fi
+elif has_libgcrypt; then
gcrypt_cflags=$(libgcrypt-config --cflags)
gcrypt_libs=$(libgcrypt-config --libs)
# Debian has removed -lgpg-error from libgcrypt-config
@@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then
then
gcrypt_libs="$gcrypt_libs -lgpg-error"
fi
+fi
-# Link test to make sure the given libraries work (e.g for static).
-write_c_skeleton
-if compile_prog "" "$gcrypt_libs" ; then
-LIBS="$gcrypt_libs $LIBS"
-QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
-pass="yes"
-fi
+# Link test to make sure the given libraries work (e.g for static).
+write_c_skeleton
+if compile_prog "" "$gcrypt_libs" ; then
+ LIBS="$gcrypt_libs $LIBS"
+ QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
+ pass="yes"
fi
+
if test "$pass" = "yes"; then
gcrypt="yes"
cat > $TMPC << EOF
--
2.7.4
Re: [Qemu-devel] [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space configurable
Hi Igor,
> -Original Message-
> From: Igor Mammedov [mailto:imamm...@redhat.com]
> Sent: 29 August 2019 09:45
> To: Shameerali Kolothum Thodi
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> eric.au...@redhat.com; peter.mayd...@linaro.org; sa...@linux.intel.com;
> ard.biesheu...@linaro.org; Linuxarm ;
> shannon.zha...@gmail.com; sebastien.bo...@intel.com; ler...@redhat.com
> Subject: Re: [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space
> configurable
>
> On Thu, 15 Aug 2019 08:42:48 +
> Shameerali Kolothum Thodi wrote:
>
> > > -Original Message-
> > > From: Linuxarm [mailto:linuxarm-boun...@huawei.com] On Behalf Of
> Shameer
> > > Kolothum
> > > Sent: 13 August 2019 22:05
> > > To: qemu-devel@nongnu.org; qemu-...@nongnu.org;
> > > eric.au...@redhat.com; imamm...@redhat.com
> > > Cc: peter.mayd...@linaro.org; sa...@linux.intel.com;
> > > ard.biesheu...@linaro.org; Linuxarm ;
> > > shannon.zha...@gmail.com; sebastien.bo...@intel.com;
> ler...@redhat.com
> > > Subject: [PATCH-for-4.2 v9 01/12] hw/acpi: Make ACPI IO address space
> > > configurable
> > >
> > > This is in preparation for adding support for ARM64 platforms
> > > where it doesn't use port mapped IO for ACPI IO space. We are
> > > making changes so that MMIO region can be accommodated
> > > and board can pass the base address into the aml build function.
> >
> > Looks like, this now breaks the "make check" on x86_64 and needs
> > updating bios-tables-test-allowed-diff.h with DSDT entries. But I am
> > not sure what changed now compared to v8(and older ones) that makes
> > it to complain now!.
>
> you could see diff of what's changed but running test manually with
> V=1 env var if you have 'iasl' installed
>
> V=1 QTEST_QEMU_BINARY=x86_64-softmmu/qemu-system-x86_64
> tests/bios-tables-test
Thanks for that tip and please find below output.
/x86_64/acpi/piix4: Could not access KVM kernel module: No such file or
directory
qemu-system-x86_64: failed to initialize KVM: No such file or directory
qemu-system-x86_64: Back to tcg accelerator
acpi-test: Warning! DSDT binary file mismatch. Actual [aml:/tmp/aml-RGE76Z],
Expected [aml:tests/data/acpi/pc/DSDT].
acpi-test: Warning! DSDT mismatch. Actual [asl:/tmp/asl-TAE76Z.dsl,
aml:/tmp/aml-RGE76Z], Expected [asl:/tmp/asl-O6B76Z.dsl,
aml:tests/data/acpi/pc/DSDT].
diff --git a/tmp/asl-O6B76Z.dsl b/tmp/asl-TAE76Z.dsl
index 823ff002ec..4de5bd3221 100644
--- a/tmp/asl-O6B76Z.dsl
+++ b/tmp/asl-TAE76Z.dsl
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of tests/data/acpi/pc/DSDT, Thu Aug 29 10:40:40 2019
+ * Disassembly of /tmp/aml-RGE76Z, Thu Aug 29 10:40:40 2019
*
* Original Table Header:
* Signature"DSDT"
- * Length 0x140B (5131)
+ * Length 0x17E4 (6116)
* Revision 0x01 32-bit table (V1), no 64-bit math support
- * Checksum 0xB1
+ * Checksum 0x8B
* OEM ID "BOCHS "
* OEM Table ID "BXPCDSDT"
* OEM Revision 0x0001 (1)
@@ -787,6 +787,206 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT",
0x0001)
\_SB.CPUS.CSCN ()
}
+Device (\_SB.PCI0.MHPD)
+{
+Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID:
Hardware ID
+Name (_UID, "Memory hotplug resources") // _UID: Unique ID
+Name (_CRS, Reso
I think what happens is since we are now passing the memhp_io_base directly
into the
build_memory_hotplug_aml() and removed the "static uint16_t memhp_io_base", on
x86, memory hotplug aml code is always built by default irrespective of whether
acpi_memory_hotplug_init() is invoked or not.
I could either reintroduce a check in build_memory_hotplug_aml() to make sure
acpi_memory_hotplug_init() is called, or could do something like below,
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 3995f9a40f..17756c2191 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1873,9 +1873,12 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
"\\_SB.PCI0", "\\_GPE._E02");
}
-build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
- "\\_GPE._E03", AML_SYSTEM_IO,
- pcms->memhp_io_base);
+
+if (acpi_enabled && pcms->acpi_dev && nr_mem) {
+build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
+ "\\_GPE._E03", AML_SYSTEM_IO,
+ pcms->memhp_io_base);
+}
I prefer the latter if there are no other issues with that. Please let me know.
Thanks,
Shameer
>
> > Patchew URL:
> https://patchew.org/QEMU/20190813210539.31164-1-shameerali.kolothum.t
> h...@huawei.com/
> >
> > ERROR:/tmp/qemu-test/src/tests/bios-tables-test.c:447:test_acpi_asl:
> assertion failed: (all_tables_match)
> >
> > Thanks,
> > Shameer
> >
> > >
Re: [Qemu-devel] [PATCH] configure: Add pkg-config handling for libgcrypt
On 8/29/19 5:15 PM, Daniel P. Berrangé wrote:
> On Thu, Aug 29, 2019 at 04:53:02PM +0800, zhe...@windriver.com wrote:
>> From: He Zhe
>>
>> libgcrypt may also be controlled by pkg-config, this patch adds pkg-config
>> handling for libgcrypt.
> Where are you seeing pkg-config files for libgcrypt ?
>
> The upstream project has (frustratingly) been hostile to any proposal to
> add pkg-config support saying people should stick with their custom
> libgcrypt-config tool
>
>https://dev.gnupg.org/T2037
>
> Even if this is something added by some distro downstream, what is the
> benefit in using it, compared with libgcrypt-confg which should already
> work & is portable.
IMHO, it could be easy for people to use pkg-config as a center to control
configurations for many different packages.
This is just an addition for qemu to be able to work in both cases. It does not
remove libgcrypt-confg and can fall back to libgcrypt-confg when pkg-config does
not work.
Zhe
>
>> Signed-off-by: He Zhe
>> ---
>> configure | 48
>> 1 file changed, 40 insertions(+), 8 deletions(-)
>>
>> diff --git a/configure b/configure
>> index e44e454..0f362a7 100755
>> --- a/configure
>> +++ b/configure
>> @@ -2875,6 +2875,30 @@ has_libgcrypt() {
>> return 0
>> }
>>
>> +has_libgcrypt_pkgconfig() {
>> +if ! has $pkg_config ; then
>> +return 1
>> +fi
>> +
>> +if ! $pkg_config --list-all | grep libgcrypt > /dev/null 2>&1 ; then
>> +return 1
>> +fi
>> +
>> +if test -n "$cross_prefix" ; then
>> +host=$($pkg_config --variable=host libgcrypt)
>> +if test "${host%-gnu}-" != "${cross_prefix%-gnu}" ; then
>> +print_error "host($host) does not match
>> cross_prefix($cross_prefix)"
>> +return 1
>> +fi
>> +fi
>> +
>> +if ! $pkg_config --atleast-version=1.5.0 libgcrypt ; then
>> +print_error "libgcrypt version is $($pkg_config --modversion
>> libgcrypt)"
>> +return 1
>> +fi
>> +
>> +return 0
>> +}
>>
>> if test "$nettle" != "no"; then
>> pass="no"
>> @@ -2902,7 +2926,14 @@ fi
>>
>> if test "$gcrypt" != "no"; then
>> pass="no"
>> -if has_libgcrypt; then
>> +if has_libgcrypt_pkgconfig; then
>> +gcrypt_cflags=$($pkg_config --cflags libgcrypt)
>> +if test "$static" = "yes" ; then
>> +gcrypt_libs=$($pkg_config --libs --static libgcrypt)
>> +else
>> +gcrypt_libs=$($pkg_config --libs libgcrypt)
>> +fi
>> +elif has_libgcrypt; then
>> gcrypt_cflags=$(libgcrypt-config --cflags)
>> gcrypt_libs=$(libgcrypt-config --libs)
>> # Debian has removed -lgpg-error from libgcrypt-config
>> @@ -2912,15 +2943,16 @@ if test "$gcrypt" != "no"; then
>> then
>> gcrypt_libs="$gcrypt_libs -lgpg-error"
>> fi
>> +fi
>>
>> -# Link test to make sure the given libraries work (e.g for static).
>> -write_c_skeleton
>> -if compile_prog "" "$gcrypt_libs" ; then
>> -LIBS="$gcrypt_libs $LIBS"
>> -QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
>> -pass="yes"
>> -fi
>> +# Link test to make sure the given libraries work (e.g for static).
>> +write_c_skeleton
>> +if compile_prog "" "$gcrypt_libs" ; then
>> +LIBS="$gcrypt_libs $LIBS"
>> +QEMU_CFLAGS="$QEMU_CFLAGS $gcrypt_cflags"
>> +pass="yes"
>> fi
>> +
>> if test "$pass" = "yes"; then
>> gcrypt="yes"
>> cat > $TMPC << EOF
>> --
>> 2.7.4
>>
> Regards,
> Daniel
Re: [Qemu-devel] [Slirp] [PATCH 1/2] Do not reassemble fragments pointing outside of the original payload
+-- On Mon, 26 Aug 2019, Samuel Thibault wrote --+
| Philippe Mathieu-Daudé, le ven. 23 août 2019 17:15:32 +0200, a ecrit:
| > > Did you make your test with commit 126c04acbabd ("Fix heap overflow in
| > > ip_reass on big packet input") applied?
| >
| > Yes, unfortunately it doesn't fix the issue.
|
| Ok.
|
| Could you try the attached patch? There was a use-after-free. Without
| it, I can indeed crash qemu with the given exploit. With it I don't
| seem to be able to crash it (trying in a loop for several minutes).
Considering that earlier fix was released/pulled into upstream QEMU v4.1.0, we
need to treat this one as a separate issue.
commit c59279437eda91841b9d26079c70b8a540d41204
Author: Samuel Thibault
Date: Mon Aug 26 00:55:03 2019 +0200
ip_reass: Fix use after free
Using ip_deq after m_free might read pointers from an allocation reuse.
I'll follow-up on that.
Thank you.
--
Prasad J Pandit / Red Hat Product Security Team
47AF CE69 3A90 54AA 9045 1053 DD13 3D32 FE5B 041F
Re: [Qemu-devel] [PATCH v9 04/13] block/backup: adjust block-copy functions style
28.08.2019 19:06, Max Reitz wrote: > On 26.08.19 18:13, Vladimir Sementsov-Ogievskiy wrote: >> Fix comment style and reflow arguments in same manner like >> block_copy_state_new. > > I like the current function header style better. > OK, not critical at all for me, let's keep current. I'll instead fix all comments style here. -- Best regards, Vladimir
Re: [Qemu-devel] [PATCH v8 01/37] target/mips: Add support for DSPRAM
Hi Aleksandar,
On 8/19/19 2:07 PM, Aleksandar Markovic wrote:
> From: Yongbok Kim
>
> The optional Data Scratch Pad RAM (DSPRAM) block provides a general scratch
> pad RAM
> used for temporary storage of data. The DSPRAM provides a connection to
> on-chip
> memory or memory-mapped registers, which are accessed in parallel with the L1
> data
> cache to minimize access latency
Can you point me to a vm/kernel image using this feature?
> Signed-off-by: Yongbok Kim
> Signed-off-by: Aleksandar Markovic
> ---
> hw/mips/cps.c| 29 +++-
> hw/misc/Makefile.objs| 1 +
> hw/misc/mips_dspram.c| 153
> +++
> include/hw/mips/cps.h| 2 +
> include/hw/misc/mips_dspram.h| 46
> target/mips/cpu.h| 9 ++-
> target/mips/internal.h | 3 +-
I suggest you to install scripts/git.orderfile, having files ordered
eases reviews.
> target/mips/op_helper.c | 18 +
> target/mips/translate.c | 8 ++
> target/mips/translate_init.inc.c | 2 +
> 10 files changed, 266 insertions(+), 5 deletions(-)
> create mode 100644 hw/misc/mips_dspram.c
> create mode 100644 include/hw/misc/mips_dspram.h
>
> diff --git a/hw/mips/cps.c b/hw/mips/cps.c
> index 0d459c4..c84bc64 100644
> --- a/hw/mips/cps.c
> +++ b/hw/mips/cps.c
> @@ -18,6 +18,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "qemu/error-report.h"
> #include "qapi/error.h"
> #include "qemu/module.h"
> #include "hw/mips/cps.h"
> @@ -91,7 +92,8 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
>
> cpu = MIPS_CPU(first_cpu);
> env = &cpu->env;
> -saar_present = (bool)env->saarp;
> +saar_present = env->saarp;
> +bool dspram_present = env->dspramp;
>
> /* Inter-Thread Communication Unit */
> if (itu_present) {
> @@ -102,7 +104,8 @@ static void mips_cps_realize(DeviceState *dev, Error
> **errp)
> object_property_set_bool(OBJECT(&s->itu), saar_present,
> "saar-present",
> &err);
> if (saar_present) {
> -qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void
> *)&env->CP0_SAAR);
> +qdev_prop_set_ptr(DEVICE(&s->itu), "saar",
> + (void *) &env->CP0_SAAR[0]);
> }
> object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
> if (err != NULL) {
> @@ -113,6 +116,28 @@ static void mips_cps_realize(DeviceState *dev, Error
> **errp)
> memory_region_add_subregion(&s->container, 0,
> sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu),
> 0));
> }
> +env->dspram = g_new0(MIPSDSPRAMState, 1);
Why not allocated this only if dspram_present?
> +
> +/* Data Scratch Pad RAM */
> +if (dspram_present) {
> +if (!saar_present) {
> +error_report("%s: DSPRAM requires SAAR registers", __func__);
> +return;
> +}
> +object_initialize(&s->dspram, sizeof(MIPSDSPRAMState),
> + TYPE_MIPS_DSPRAM);
> +qdev_set_parent_bus(DEVICE(&s->dspram), sysbus_get_default());
> +qdev_prop_set_ptr(DEVICE(&s->dspram), "saar",
> + &env->CP0_SAAR[1]);
> +object_property_set_bool(OBJECT(&s->dspram), true, "realized", &err);
> +if (err != NULL) {
> +error_report("%s: DSPRAM initialisation failed", __func__);
> +error_propagate(errp, err);
> +return;
> +}
> +memory_region_add_subregion(&s->container, 0,
> +sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dspram), 0));
> +}
>
> /* Cluster Power Controller */
> sysbus_init_child_obj(OBJECT(dev), "cpc", &s->cpc, sizeof(s->cpc),
> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
> index e9aab51..5fcb4db 100644
> --- a/hw/misc/Makefile.objs
> +++ b/hw/misc/Makefile.objs
> @@ -60,6 +60,7 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
> obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o
> obj-$(CONFIG_MIPS_CPS) += mips_cpc.o
> obj-$(CONFIG_MIPS_ITU) += mips_itu.o
> +obj-$(CONFIG_MIPS_DSPRAM) += mips_dspram.o
> obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o
> obj-$(CONFIG_MPS2_SCC) += mps2-scc.o
>
> diff --git a/hw/misc/mips_dspram.c b/hw/misc/mips_dspram.c
> new file mode 100644
> index 000..9bc155b
> --- /dev/null
> +++ b/hw/misc/mips_dspram.c
> @@ -0,0 +1,153 @@
> +/*
> + * Data Scratch Pad RAM
> + *
> + * Copyright (c) 2017 Imagination Technologies
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied war
Re: [Qemu-devel] [PATCH v9 05/13] block: move block_copy from block/backup.c to separate file
28.08.2019 19:16, Max Reitz wrote: > On 26.08.19 18:13, Vladimir Sementsov-Ogievskiy wrote: >> Split block_copy to separate file, to be cleanly shared with backup-top >> filter driver in further commits. >> >> It's a clean movement, the only change is drop "static" from interface >> functions. >> >> Signed-off-by: Vladimir Sementsov-Ogievskiy >> --- >> include/block/block-copy.h | 59 +++ >> block/backup.c | 313 + >> block/block-copy.c | 307 >> block/Makefile.objs| 1 + >> block/trace-events | 2 + >> 5 files changed, 370 insertions(+), 312 deletions(-) >> create mode 100644 include/block/block-copy.h >> create mode 100644 block/block-copy.c > > May change depending on changes to the preceding patches, but FWIW > > Reviewed-by: Max Reitz > If you don't mind, I'll keep it until the patch doing simple nochange movement. -- Best regards, Vladimir
Re: [Qemu-devel] [PATCH for-4.2 v5 1/2] kvm: s390: split too big memory section on several memslots
On Thu, 29 Aug 2019 08:47:49 +0200
Christian Borntraeger wrote:
> On 27.08.19 14:56, Igor Mammedov wrote:
> > On Tue, 20 Aug 2019 18:07:27 +0200
> > Cornelia Huck wrote:
> >
> >> On Wed, 7 Aug 2019 11:32:41 -0400
> >> Igor Mammedov wrote:
> >>
> >>> Max memslot size supported by kvm on s390 is 8Tb,
> >>> move logic of splitting RAM in chunks upto 8T to KVM code.
> >>>
> >>> This way it will hide KVM specific restrictions in KVM code
> >>> and won't affect baord level design decisions. Which would allow
> >>> us to avoid misusing memory_region_allocate_system_memory() API
> >>> and eventually use a single hostmem backend for guest RAM.
> >>>
> >>> Signed-off-by: Igor Mammedov
> >>> ---
> >>> v5:
> >>> * move computation 'size -= slot_size' inside of loop body
> >>> (David Hildenbrand )
> >>> v4:
> >>> * fix compilation issue
> >>> (Christian Borntraeger )
> >>> * advance HVA along with GPA in kvm_set_phys_mem()
> >>> (Christian Borntraeger )
> >>>
> >>> patch prepares only KVM side for switching to single RAM memory region
> >>> another patch will take care of dropping manual RAM partitioning in
> >>> s390 code.
> >>
> >> I may have lost track a bit -- what is the status of this patch (and
> >> the series)?
> >
> > Christian,
> >
> > could you test it on a host that have sufficient amount of RAM?
>
>
> This version looks good. I was able to start a 9TB guest.
> [pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=0, flags=0,
> guest_phys_addr=0, memory_size=8796091973632, userspace_addr=0x3ffee70})
> = 0
> [pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=1, flags=0,
> guest_phys_addr=0x7f0, memory_size=1099512676352,
> userspace_addr=0xbffee60}) = 0
>
> The only question is if we want to fix the weird alignment (0x7f0)
> when
> we already add a migration barrier for uber-large guests.
> Maybe we could split at 4TB to avoid future problem with larger page sizes?
That probably should be a separate patch on top.
Re: [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
On 2019/8/29 上午5:34, Alistair Francis wrote: On Wed, Aug 28, 2019 at 12:04 AM liuzhiwei wrote: Change-Id: I3cf891bc400713b95f47ecca82b1bf773f3dcb25 Signed-off-by: liuzhiwei --- fpu/softfloat.c | 119 + include/fpu/softfloat.h | 4 + linux-user/riscv/cpu_loop.c | 8 +- target/riscv/Makefile.objs | 2 +- target/riscv/cpu.h |30 + target/riscv/cpu_bits.h |15 + target/riscv/cpu_helper.c | 7 + target/riscv/csr.c |65 +- target/riscv/helper.h | 354 + target/riscv/insn32.decode | 374 +- target/riscv/insn_trans/trans_rvv.inc.c | 484 + target/riscv/translate.c| 1 + target/riscv/vector_helper.c| 26563 ++ 13 files changed, 28017 insertions(+), 9 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c create mode 100644 target/riscv/vector_helper.c Hello, Thanks for the patch! As others have pointed out you will need to split the patch up into multiple smaller patches, otherwise it is too hard to review almost 30,000 lines of code. Hi, Alistair I'm so sorry for the inconvenience. It will be a patch set with a cover letter in V2. Can you also include a cover letter with your patch series describing how you are testing this? AFAIK vector extension support isn't in any compiler so I'm assuming you are handwriting the assembly or have toolchain patches. Either way it will help if you can share that so others can test your implementation. Yes, it's handwriting assembly. The assembler in Binutils has support Vector extension. First define an function test_vadd_vv_8 in assembly and then it can be called from a C program. The function is something like /* vadd.vv */ TEST_FUNC(test_vadd_vv_8) vsetvli t1, x0, e8, m2 vlb.v v6, (a4) vsb.v v6, (a3) vsetvli t1, a0, e8, m2 vlb.v v0, (a1) vlb.v v2, (a2) vadd.vv v4, v0, v2 vsb.v v4, (a3) ret .size test_vadd_vv_8, .-test_vadd_vv_8 It takes more time to test than to implement the instructions. Maybe there is some better test method or some forced test cases in QEMU. Could you give me some advice for testing? Best Regards, Zhiwei Alex and Richard have kindly started the review. Once you have addressed their comments and split this patch up into smaller patches you can send a v2 and we can go from there. Once again thanks for doing this implementation for QEMU! Alistair
Re: [Qemu-devel] [qemu-s390x] [PATCH for-4.2 v5 1/2] kvm: s390: split too big memory section on several memslots
On 29.08.19 14:04, Igor Mammedov wrote:
> On Thu, 29 Aug 2019 08:47:49 +0200
> Christian Borntraeger wrote:
>
>> On 27.08.19 14:56, Igor Mammedov wrote:
>>> On Tue, 20 Aug 2019 18:07:27 +0200
>>> Cornelia Huck wrote:
>>>
On Wed, 7 Aug 2019 11:32:41 -0400
Igor Mammedov wrote:
> Max memslot size supported by kvm on s390 is 8Tb,
> move logic of splitting RAM in chunks upto 8T to KVM code.
>
> This way it will hide KVM specific restrictions in KVM code
> and won't affect baord level design decisions. Which would allow
> us to avoid misusing memory_region_allocate_system_memory() API
> and eventually use a single hostmem backend for guest RAM.
>
> Signed-off-by: Igor Mammedov
> ---
> v5:
> * move computation 'size -= slot_size' inside of loop body
> (David Hildenbrand )
> v4:
> * fix compilation issue
> (Christian Borntraeger )
> * advance HVA along with GPA in kvm_set_phys_mem()
> (Christian Borntraeger )
>
> patch prepares only KVM side for switching to single RAM memory region
> another patch will take care of dropping manual RAM partitioning in
> s390 code.
I may have lost track a bit -- what is the status of this patch (and
the series)?
>>>
>>> Christian,
>>>
>>> could you test it on a host that have sufficient amount of RAM?
>>
>>
>> This version looks good. I was able to start a 9TB guest.
>> [pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=0, flags=0,
>> guest_phys_addr=0, memory_size=8796091973632, userspace_addr=0x3ffee70})
>> = 0
>> [pid 215723] ioctl(10, KVM_SET_USER_MEMORY_REGION, {slot=1, flags=0,
>> guest_phys_addr=0x7f0, memory_size=1099512676352,
>> userspace_addr=0xbffee60}) = 0
>>
>> The only question is if we want to fix the weird alignment (0x7f0)
>> when
>> we already add a migration barrier for uber-large guests.
>> Maybe we could split at 4TB to avoid future problem with larger page sizes?
> That probably should be a separate patch on top.
Right. The split in KVM code is transparent to migration and other parts of
QEMU, correct?
