Re: venv for python qtest bits? (was: Re: [PATCH 11/12] acpi/tests/bits: add README file for bits qtests)

[Ani Sinha]

On Fri, Jul 1, 2022 at 12:23 PM Michael S. Tsirkin  wrote:
>
> On Fri, Jul 01, 2022 at 06:12:14AM +0200, Thomas Huth wrote:
> > I even wouldn't mind if you put your python stuff in a new directory like
> > tests/pytests/ for example, as long as it downloads your binaries separately
> > - as I wrote in another mail, the avocado framework rather looks like an
> > oddball in our test framework nowadays since it uses a separate test runner
> > and not the meson test harness, so having a new approach for python-based
> > tests is maybe even a good idea. I just really want to avoid that this goes
> > into tests/qtest (since it really does not belong there), and please don't
> > add more external stuff via git submodules, that's really the wrong approach
> > for this.
>
> I get it, people hate submodules with passion.  I think trying another
> approach for testing that is neither avocado nor qtest is
> not too bad. As long as this is not user visible, we can
> allow ourselves space to experiment.
>
> OK so, how about this:
> - put it in a new directory: tests/roms?
> - create repo for a fork of biosbits under git.qemu.org
> - roll our own analog to git submodules: a script
>   that clones the repo

No need to clone the whole repo. We can simply download the binaries
that the girlab CI job would generate from the bits sources in that
repo.
We need to clone if we are always building bits from source for every
test. That is not necessary IMHO since much of the bits package would
remain as is without modification.

> - new target make check-roms,

I think make pytest or some such is better and more generic if other
such tests in other areas follow suit.

if the clone exists locally -
>   run the test, if not - skip it

if download of the bits binaries fail, skip it.

> - as for using pre-generates ISOs as an optimization,
>   I'm not sure how important that is, if yes -
>   we can add another repo and another make target along the
>   same lines
>
>
>
> --
> MST
>

Re: [PATCH 3/9] hw/arm/aspeed: qcom-dc-scm-v1: add block backed FRU device

[Cédric Le Goater]

Adding Markus,

On 6/23/22 19:37, Patrick Venture wrote:



On Thu, Jun 23, 2022 at 10:16 AM Cédric Le Goater mailto:c...@kaod.org>> wrote:

On 6/23/22 17:28, Patrick Venture wrote:
 >
 >
 > On Wed, Jun 22, 2022 at 10:48 AM Jae Hyun Yoo mailto:quic_jaeh...@quicinc.com> >> wrote:
 >
 >     From: Graeme Gregory mailto:quic_ggreg...@quicinc.com> 
>>
 >
 >     The FRU device uses the index 0 device on bus IF_NONE.
 >
 >     -drive file=$FRU,format=raw,if=none
 >
 >     file must match FRU size of 128k
 >
 >     Signed-off-by: Graeme Gregory mailto:quic_ggreg...@quicinc.com> >>
 >     ---
 >       hw/arm/aspeed.c | 22 +-
 >       1 file changed, 17 insertions(+), 5 deletions(-)
 >
 >     diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
 >     index 785cc543d046..36d6b2c33e48 100644
 >     --- a/hw/arm/aspeed.c
 >     +++ b/hw/arm/aspeed.c
 >     @@ -992,17 +992,29 @@ static void fby35_i2c_init(AspeedMachineState 
*bmc)
 >            */
 >       }
 >
 >     +static void qcom_dc_scm_fru_init(I2CBus *bus, uint8_t addr, 
uint32_t rsize)
 >     +{
 >     +    I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
 >     +    DeviceState *dev = DEVICE(i2c_dev);
 >     +    /* Use First Index for DC-SCM FRU */
 >     +    DriveInfo *dinfo = drive_get(IF_NONE, 0, 0);
 >     +
 >     +    qdev_prop_set_uint32(dev, "rom-size", rsize);
 >     +
 >     +    if (dinfo) {
 >     +        qdev_prop_set_drive(dev, "drive", 
blk_by_legacy_dinfo(dinfo));
 >     +    }
 >     +
 >     +    i2c_slave_realize_and_unref(i2c_dev, bus, _abort);
 >     +}
 >
 >
 > We've sent a similar patch up for the at24c but in its own file -- but 
looking at this, we could likely expand it to suite our cases as well - is there a 
reason it's named qcom_dc_scm_fru_init?  Presumably that's to handle the drive_get 
parameters.  If you make it use `drive_get(IF_NONE, bus, unit);` You'll be able to 
associate a drive via parameters like you aim to.


I have seen various attempts to populate the Aspeed eeproms with
data. The simplest is the g220a_bmc_i2c_init() approach. Some are
generating C code from the .bin files and compiling the result in
QEMU. Some were generating elf sections, linking them in QEMU and
passing the pointer as an eeprom buf.

The drive approach is the best I think, but the device/drive
association depends on the drive order on the command line when
devices are created by the platform.

We could may be extend the GenericLoaderState for eeproms ?
or introduce a routine which would look for a file under a (pc-bios)
per-machine directory and fill the eeprom buf with its contents ?

Any idea ?


So we have this in our eeprom_at24c module because we use it with Aspeed and 
Nuvoton:

void at24c_eeprom_init_one(I2CBus *i2c_bus, int bus, uint8_t addr,
                            uint32_t rsize, int unit_number)
{
     I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
     DeviceState *dev = DEVICE(i2c_dev);
     BlockInterfaceType type = IF_NONE;
     DriveInfo *dinfo;

     dinfo = drive_get(type, bus, unit_number);
     if (dinfo) {
         qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
     }
     qdev_prop_set_uint32(dev, "rom-size", rsize);
     i2c_slave_realize_and_unref(i2c_dev, i2c_bus, _abort);
}

With this style call in the board:

snippet from downstream version of 
https://github.com/qemu/qemu/blob/master/hw/arm/npcm7xx_boards.c#L305 
 that we 
still need to finish upstreaming:


      /* mb_fru */
     at24c_eeprom_init_one(npcm7xx_i2c_get_bus(soc, 5), 5, 0x50, 8192, 0);

     /* fan_fru */
     at24c_eeprom_init_one(pca954x_i2c_get_bus(i2c_mux, 2), 5, 0x51, 8192, 1);
     /* hsbp_fru */
     at24c_eeprom_init_one(pca954x_i2c_get_bus(i2c_mux, 3), 5, 0x52, 8192, 2);


And then we call it with the bus and unit, the pair of those has to be unique 
for the drive parameter to work:

-drive 
file=/export/hda3/tmp/mb_fru@50,if=none,bus=5,unit=0,snapshot=off,format=raw
-drive 
file=/export/hda3/tmp/fan_fru@51,if=none,bus=5,unit=1,snapshot=off,format=raw
-drive 
file=/export/hda3/tmp/hsbp_fru@52,if=none,bus=5,unit=2,snapshot=off,format=raw

The above code snippet is what, I'm fairly certain we had sent up for review 
before, and we can send it again if you want.


You could. I am not sure this is the good direction but it would restart
the -drive topic.


Thanks,

C.

[RFC v1] util/aio: Keep notification disabled as much as possible

[Chao Gao]

When measuring FIO read performance (cache=writethrough, bs=4k, iodepth=64) in
VMs, we observe ~80K/s notifications (e.g., EPT_MISCONFIG) from guest to qemu.

Currently, poll_set_started(ctx,false) is called in try_poll_mode() to enable
virtqueue notification in below 4 cases:

1. ctx->poll_ns is 0
2. a zero timeout is passed to try_poll_mode()
3. polling succeeded but reported as no progress
4. polling failed and reported as no progress

To minimize unnecessary guest notifications, keep notification disabled when
it is possible, i.e., polling is enabled and last polling doesn't fail.

Keep notification disabled for case #2 and #3; handle case #2 simply by a call
of run_poll_handlers_once() and for case #3, differentiate successful/failed
polling and skip the call of poll_set_started(ctx,false) for successful ones.

With this patch applied, FIO seq-read performance (bs=4k, iodepth=64,
cache=writethrough) in VMs increases from 330K/s to 413K/s IOPS.

Below are changes in VM-exit statistics:
w/o this patch (duration:10s):
   VM-EXITSamples  Samples% Time%Min TimeMax Time   
  Avg time

 EPT_MISCONFIG 79744099.34%98.58%  0.39us 57.92us  
0.60us ( +-   0.05% )
 MSR_WRITE   3672 0.46% 1.15%  0.88us  4.97us  
1.52us ( +-   0.53% )
EXTERNAL_INTERRUPT   1638 0.20% 0.27%  0.59us 11.04us  
0.81us ( +-   1.71% )

w/ this patch (duration:10s):
  VM-EXITSamples  Samples% Time%Min TimeMax Time
 Avg time

 MSR_WRITE   352484.11%87.17%  0.86us  4.43us  
1.74us ( +-   0.60% )
EXTERNAL_INTERRUPT51512.29%10.05%  0.64us  8.95us  
1.37us ( +-   1.54% )
 EPT_MISCONFIG151 3.60% 2.79%  0.40us 52.07us  
1.30us ( +-  31.44% )

Signed-off-by: Chao Gao 
---
 util/aio-posix.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/util/aio-posix.c b/util/aio-posix.c
index 731f3826c0..bd2076145b 100644
--- a/util/aio-posix.c
+++ b/util/aio-posix.c
@@ -519,7 +519,7 @@ static bool remove_idle_poll_handlers(AioContext *ctx,
  * Returns: true if progress was made, false otherwise
  */
 static bool run_poll_handlers(AioContext *ctx, AioHandlerList *ready_list,
-  int64_t max_ns, int64_t *timeout)
+  int64_t max_ns, int64_t *timeout, bool *success)
 {
 bool progress;
 int64_t start_time, elapsed_time;
@@ -553,6 +553,8 @@ static bool run_poll_handlers(AioContext *ctx, 
AioHandlerList *ready_list,
 progress = true;
 }
 
+*success = !*timeout;
+
 /* If time has passed with no successful polling, adjust *timeout to
  * keep the same ending time.
  */
@@ -577,22 +579,28 @@ static bool run_poll_handlers(AioContext *ctx, 
AioHandlerList *ready_list,
 static bool try_poll_mode(AioContext *ctx, AioHandlerList *ready_list,
   int64_t *timeout)
 {
-int64_t max_ns;
+int64_t max_ns, start_time;
+bool success = false;
 
 if (QLIST_EMPTY_RCU(>poll_aio_handlers)) {
 return false;
 }
 
+if (!*timeout) {
+start_time = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
+return run_poll_handlers_once(ctx, ready_list, start_time, timeout);
+}
+
 max_ns = qemu_soonest_timeout(*timeout, ctx->poll_ns);
 if (max_ns && !ctx->fdmon_ops->need_wait(ctx)) {
 poll_set_started(ctx, ready_list, true);
 
-if (run_poll_handlers(ctx, ready_list, max_ns, timeout)) {
+if (run_poll_handlers(ctx, ready_list, max_ns, timeout, )) {
 return true;
 }
 }
 
-if (poll_set_started(ctx, ready_list, false)) {
+if (!success && poll_set_started(ctx, ready_list, false)) {
 *timeout = 0;
 return true;
 }
-- 
2.25.1

[PATCH v2] microvm: turn off io reservations for pcie root ports

[Gerd Hoffmann]

The pcie host bridge has no io window on microvm,
so io reservations will not work.

Signed-off-by: Gerd Hoffmann 
---
 hw/i386/microvm.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index 4b3b1dd262f1..06f779e1aaee 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -667,6 +667,14 @@ static void microvm_machine_initfn(Object *obj)
 qemu_register_powerdown_notifier(>powerdown_req);
 }
 
+GlobalProperty microvm_properties[] = {
+/*
+ * pcie host bridge (gpex) on microvm has no io address window,
+ * so reserving io space is not going to work.  Turn it off.
+ */
+{ "pcie-root-port", "io-reserve", "0" },
+};
+
 static void microvm_class_init(ObjectClass *oc, void *data)
 {
 X86MachineClass *x86mc = X86_MACHINE_CLASS(oc);
@@ -757,6 +765,9 @@ static void microvm_class_init(ObjectClass *oc, void *data)
 "Set off to disable adding virtio-mmio devices to the kernel cmdline");
 
 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
+
+compat_props_add(mc->compat_props, microvm_properties,
+ G_N_ELEMENTS(microvm_properties));
 }
 
 static const TypeInfo microvm_machine_info = {
-- 
2.36.1

Re: [PATCH v5 07/12] net: stream: add unix socket

[Laurent Vivier]

On 30/06/2022 11:28, Dr. David Alan Gilbert wrote:

* Laurent Vivier (lviv...@redhat.com) wrote:

Signed-off-by: Laurent Vivier 
Reviewed-by: Stefano Brivio 
---
  net/stream.c| 106 +---
  qemu-options.hx |   1 +
  2 files changed, 102 insertions(+), 5 deletions(-)

diff --git a/net/stream.c b/net/stream.c
index e8afbaca50b6..1a2bc237707e 100644
--- a/net/stream.c
+++ b/net/stream.c
@@ -235,7 +235,7 @@ static NetStreamState 
*net_stream_fd_init_stream(NetClientState *peer,
  static void net_stream_accept(void *opaque)
  {
  NetStreamState *s = opaque;
-struct sockaddr_in saddr;
+struct sockaddr_storage saddr;
  socklen_t len;
  int fd;
  
@@ -253,9 +253,27 @@ static void net_stream_accept(void *opaque)

  s->fd = fd;
  s->nc.link_down = false;
  net_stream_connect(s);
-snprintf(s->nc.info_str, sizeof(s->nc.info_str),
- "connection from %s:%d",
- inet_ntoa(saddr.sin_addr), ntohs(saddr.sin_port));
+switch (saddr.ss_family) {
+case AF_INET: {
+struct sockaddr_in *saddr_in = (struct sockaddr_in *)
+
+snprintf(s->nc.info_str, sizeof(s->nc.info_str),
+ "connection from %s:%d",
+ inet_ntoa(saddr_in->sin_addr), ntohs(saddr_in->sin_port));
+break;
+}
+case AF_UNIX: {
+struct sockaddr_un saddr_un;
+
+len = sizeof(saddr_un);
+getsockname(s->listen_fd, (struct sockaddr *)_un, );
+snprintf(s->nc.info_str, sizeof(s->nc.info_str),
+ "connect from %s", saddr_un.sun_path);
+break;
+}
+default:
+g_assert_not_reached();
+}
  }
  
  static int net_stream_server_init(NetClientState *peer,

@@ -295,6 +313,42 @@ static int net_stream_server_init(NetClientState *peer,
  }
  break;
  }
+case SOCKET_ADDRESS_TYPE_UNIX: {
+struct sockaddr_un saddr_un;
+
+ret = unlink(addr->u.q_unix.path);
+if (ret < 0 && errno != ENOENT) {
+error_setg_errno(errp, errno, "failed to unlink socket %s",
+ addr->u.q_unix.path);
+return -1;
+}
+
+saddr_un.sun_family = PF_UNIX;
+ret = snprintf(saddr_un.sun_path, sizeof(saddr_un.sun_path), "%s",
+   addr->u.q_unix.path);
+if (ret < 0 || ret >= sizeof(saddr_un.sun_path)) {
+error_setg(errp, "UNIX socket path '%s' is too long",
+   addr->u.q_unix.path);
+error_append_hint(errp, "Path must be less than %zu bytes\n",
+  sizeof(saddr_un.sun_path));


return here?

+
+fd = qemu_socket(PF_UNIX, SOCK_STREAM, 0);
+if (fd < 0) {
+error_setg_errno(errp, errno, "can't create stream socket");
+return -1;
+}
+qemu_socket_set_nonblock(fd);
+
+ret = bind(fd, (struct sockaddr *)_un, sizeof(saddr_un));
+if (ret < 0) {
+error_setg_errno(errp, errno, "can't create socket with path: %s",
+ saddr_un.sun_path);
+closesocket(fd);
+return -1;
+}
+break;
+}
  case SOCKET_ADDRESS_TYPE_FD:
  fd = monitor_fd_param(monitor_cur(), addr->u.fd.str, errp);
  if (fd == -1) {
@@ -380,6 +434,48 @@ static int net_stream_client_init(NetClientState *peer,
 ntohs(saddr_in.sin_port));
  break;
  }
+case SOCKET_ADDRESS_TYPE_UNIX: {
+struct sockaddr_un saddr_un;
+
+saddr_un.sun_family = PF_UNIX;
+ret = snprintf(saddr_un.sun_path, sizeof(saddr_un.sun_path), "%s",
+   addr->u.q_unix.path);
+if (ret < 0 || ret >= sizeof(saddr_un.sun_path)) {
+error_setg(errp, "UNIX socket path '%s' is too long",
+   addr->u.q_unix.path);
+error_append_hint(errp, "Path must be less than %zu bytes\n",
+  sizeof(saddr_un.sun_path));


and here

(Can you not do a lot of this just by calling util/qemu-sockets.c
unix_connect?)


Thank you for your comments.

In fact, in the last patch, I replace all this code by QIO functions.

I keep all the intermediate patches to be sure I don't break anything from the original 
behaviour of -netdev socket and to ease debugging by allowing to bisect between the 
different steps in the change.


Thanks,
Laurent

[PATCH 08/11] target/loongarch: Fix the meaning of ECFG reg's VS field

[Xiaojuan Yang]

By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.

Signed-off-by: Xiaojuan Yang 
---
 target/loongarch/cpu.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 4c8f96bc3a..04e5e47da4 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -219,6 +219,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
 env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
 
+if (vec_size) {
+vec_size = (1 << vec_size) * 4;
+}
+
 if  (cs->exception_index == EXCCODE_INT) {
 /* Interrupt */
 uint32_t vector = 0;
-- 
2.31.1

[PATCH 07/11] hw/rtc/ls7a_rtc: Fix 'calculate' spelling errors

[Xiaojuan Yang]

Fix 'calculate' spelling errors.

Signed-off-by: Xiaojuan Yang 
---
 hw/rtc/ls7a_rtc.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index 85cd2d22a5..e8b75701e4 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -156,7 +156,7 @@ static void toymatch_write(LS7ARtcState *s, uint64_t val, 
int num)
 /* it do not support write when toy disabled */
 if (toy_enabled(s)) {
 s->toymatch[num] = val;
-/* caculate expire time */
+/* calculate expire time */
 now = qemu_clock_get_ms(rtc_clock);
 toymatch_val_to_time(s, val, );
 expire_time = now + (qemu_timedate_diff() - s->offset_toy) * 1000;
@@ -171,7 +171,7 @@ static void rtcmatch_write(LS7ARtcState *s, uint64_t val, 
int num)
 /* it do not support write when toy disabled */
 if (rtc_enabled(s)) {
 s->rtcmatch[num] = val;
-/* caculate expire time */
+/* calculate expire time */
 expire_ns = ticks_to_ns(val) - ticks_to_ns(s->offset_rtc);
 timer_mod_ns(s->rtc_timer[num], expire_ns);
 }
@@ -181,7 +181,7 @@ static void ls7a_toy_stop(LS7ARtcState *s)
 {
 int i;
 
-/* delete timers, and when re-enabled, recaculate expire time */
+/* delete timers, and when re-enabled, recalculate expire time */
 for (i = 0; i < TIMER_NUMS; i++) {
 timer_del(s->toy_timer[i]);
 }
@@ -191,7 +191,7 @@ static void ls7a_rtc_stop(LS7ARtcState *s)
 {
 int i;
 
-/* delete timers, and when re-enabled, recaculate expire time */
+/* delete timers, and when re-enabled, recalculate expire time */
 for (i = 0; i < TIMER_NUMS; i++) {
 timer_del(s->rtc_timer[i]);
 }
@@ -205,7 +205,7 @@ static void ls7a_toy_start(LS7ARtcState *s)
 
 now = qemu_clock_get_ms(rtc_clock);
 
-/* recaculate expire time and enable timer */
+/* recalculate expire time and enable timer */
 for (i = 0; i < TIMER_NUMS; i++) {
 toymatch_val_to_time(s, s->toymatch[i], );
 expire_time = now + (qemu_timedate_diff() - s->offset_toy) * 1000;
@@ -218,7 +218,7 @@ static void ls7a_rtc_start(LS7ARtcState *s)
 int i;
 uint64_t expire_time;
 
-/* recaculate expire time and enable timer */
+/* recalculate expire time and enable timer */
 for (i = 0; i < TIMER_NUMS; i++) {
 expire_time = ticks_to_ns(s->rtcmatch[i]) - ticks_to_ns(s->offset_rtc);
 timer_mod_ns(s->rtc_timer[i], expire_time);
-- 
2.31.1

Re: [PATCH] Add some documentation for "dtb" devices tree blobs

[Peter Maydell]

On Sat, 25 Jun 2022 at 23:39, Simon Sapin  wrote:
>
> Signed-off-by: Simon Sapin 
> ---
>  docs/specs/device-trees.rst| 57 ++
>  docs/specs/index.rst   |  1 +
>  docs/system/arm/virt.rst   |  5 +-
>  docs/system/arm/xlnx-versal-virt.rst   |  3 +-
>  docs/system/ppc/ppce500.rst|  3 +-
>  docs/system/riscv/microchip-icicle-kit.rst |  3 +-
>  docs/system/riscv/sifive_u.rst |  3 +-
>  docs/system/riscv/virt.rst |  3 +-
>  qemu-options.hx|  5 ++
>  9 files changed, 77 insertions(+), 6 deletions(-)
>  create mode 100644 docs/specs/device-trees.rst

Hi; thanks for writing this documentation.

> diff --git docs/specs/device-trees.rst docs/specs/device-trees.rst
> new file mode 100644
> index 00..8160342124
> --- /dev/null
> +++ docs/specs/device-trees.rst
> @@ -0,0 +1,57 @@
> +
> +Device Trees
> +
> +
> +On some targets, guests can find out what devices are emulated and how to 
> access them
> +through a *Device Tree Blob* (dtb), also called *Flattened Device Tree* 
> (fdt).
> +The dtb can be passed by the user through the ``-dtb file`` command-line 
> options,
> +or automatically generated by QEMU.
> +
> +Host: dumping the dtb
> +=
> +
> +The (possibly generated) dtb can be written to a file with
> +the ``dumpdtb`` property of the ``machine`` command-line option.
> +Then `dtc `_ can convert it to Device Tree Source 
> text "dts" format
> +For example::
> +
> +qemu-system-riscv32 -machine virt,dumpdtb=rv32-virt.dtb
> +dtc -q rv32-virt.dtb -o rv32-virt.dts
> +head -n 7 rv32-virt.dts
> +
> +::
> +
> +qemu-system-riscv32: info: dtb dumped to rv32-virt.dtb. Exiting.
> +/dts-v1/;
> +
> +/ {
> +#address-cells = <0x02>;
> +#size-cells = <0x02>;
> +compatible = "riscv-virtio";
> +model = "riscv-virtio,qemu";
> +
> +Guest: finding the dtb
> +==
> +
> +On startup, the dtb is memory-mapped and its address is passed to the guest
> +in a target-specific way:
> +
> +* Arm: :ref:`arm-baremetal`
> +* **TODO**: document other targets

Don't leave TODO notes in the docs, please.

Also, the DTB is not necessarily memory-mapped. For instance on
Arm platforms if the user requests a bios/firmware image to be
run, then we put the dtb (like the kernel and initrd) in the
fw_cfg device for the firmware to extract.

> diff --git qemu-options.hx qemu-options.hx
> index 377d22fbd8..eea75ddb37 100644
> --- qemu-options.hx
> +++ qemu-options.hx
> @@ -38,6 +38,7 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \
>  "hmat=on|off controls ACPI HMAT support (default=off)\n"
>  "memory-backend='backend-id' specifies explicitly 
> provided backend for main RAM (default=none)\n"
>  "
> cxl-fmw.0.targets.0=firsttarget,cxl-fmw.0.targets.1=secondtarget,cxl-fmw.0.size=size[,cxl-fmw.0.interleave-granularity=granularity]\n",
> +"dumpdtb=file dump current device tree blob to a file 
> and quit\n"
>  QEMU_ARCH_ALL)
>  SRST
>  ``-machine [type=]name[,prop=value[,...]]``
> @@ -157,6 +158,10 @@ SRST
>  ::
>
>  -machine 
> cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=128G,cxl-fmw.0.interleave-granularity=512k
> +
> +``dumpdtb=file``
> +Dump the current :doc:`Device Tree Blob `
> +to the give file name, then exit.

 to the given file name, then exit QEMU without running the guest.
 This is primarily useful for debugging, as it allows you to see the
 contents of the DTB including all additions and modifications that
 QEMU makes before handing it to the guest.

 This option is ignored on machine types which do not use a DTB.

>  ERST
>
>  DEF("M", HAS_ARG, QEMU_OPTION_M,


thanks
-- PMM

Re: [PATCH v3 2/2] ui/gtk: a new array param monitor to specify the target displays

[Gerd Hoffmann]

  Hi,

> > +# @monitor: Array of numbers, each of which represents physical
> > +#   monitor where GTK window containing a given VC will be
> > +#   placed. Each monitor number in the array will be
> > +#   associated with a virtual-console starting from VC0.
> 
> Drop the hyphen in "virtual-console".
> 
> Is the term "virtual console" obvious?  Gerd?

I think so, same term is used elsewhere too for the same concept.

take care,
  Gerd

Re: venv for python qtest bits? (was: Re: [PATCH 11/12] acpi/tests/bits: add README file for bits qtests)

[Michael S. Tsirkin]

On Fri, Jul 01, 2022 at 12:58:33PM +0530, Ani Sinha wrote:
> On Fri, Jul 1, 2022 at 12:23 PM Michael S. Tsirkin  wrote:
> >
> > On Fri, Jul 01, 2022 at 06:12:14AM +0200, Thomas Huth wrote:
> > > I even wouldn't mind if you put your python stuff in a new directory like
> > > tests/pytests/ for example, as long as it downloads your binaries 
> > > separately
> > > - as I wrote in another mail, the avocado framework rather looks like an
> > > oddball in our test framework nowadays since it uses a separate test 
> > > runner
> > > and not the meson test harness, so having a new approach for python-based
> > > tests is maybe even a good idea. I just really want to avoid that this 
> > > goes
> > > into tests/qtest (since it really does not belong there), and please don't
> > > add more external stuff via git submodules, that's really the wrong 
> > > approach
> > > for this.
> >
> > I get it, people hate submodules with passion.  I think trying another
> > approach for testing that is neither avocado nor qtest is
> > not too bad. As long as this is not user visible, we can
> > allow ourselves space to experiment.
> >
> > OK so, how about this:
> > - put it in a new directory: tests/roms?
> > - create repo for a fork of biosbits under git.qemu.org
> > - roll our own analog to git submodules: a script
> >   that clones the repo
> 
> No need to clone the whole repo. We can simply download the binaries
> that the girlab CI job would generate from the bits sources in that
> repo.
> We need to clone if we are always building bits from source for every
> test. That is not necessary IMHO since much of the bits package would
> remain as is without modification.

IMHO CI job idea isn't great since isn't versioned at all, is it?
Also as long as test passes, sure. But if it fails one will
need the sources to investigate.

Let's start with building things from source. Add an option
of prebuilt binaries as an optimization once things
stabilize.


> > - new target make check-roms,
> 
> I think make pytest or some such is better and more generic if other
> such tests in other areas follow suit.

The name is not critical in my mind, but I think we need to decide
what exactly differentiates it from other tests.


> 
> if the clone exists locally -
> >   run the test, if not - skip it
> 
> if download of the bits binaries fail, skip it.

You seem to be recreating either git or avocado or both here.

Personally I want something that works offline.



> > - as for using pre-generates ISOs as an optimization,
> >   I'm not sure how important that is, if yes -
> >   we can add another repo and another make target along the
> >   same lines
> >
> >
> >
> > --
> > MST
> >

Re: [PATCH v2 02/10] tests/qemu-iotests: skip 108 when FUSE is not loaded

[Hanna Reitz]

On 16.06.22 16:26, John Snow wrote:

In certain container environments we may not have FUSE at all, so skip
the test in this circumstance too.

Signed-off-by: John Snow 
---
  tests/qemu-iotests/108 | 5 +
  1 file changed, 5 insertions(+)


Reviewed-by: Hanna Reitz 

Re: [QEMU PATCH v2 3/6] acpi/nvdimm: NVDIMM _DSM Spec supports revision 2

[Robert Hoo]

On Thu, 2022-06-16 at 13:38 +0200, Igor Mammedov wrote:
> On Mon, 30 May 2022 11:40:44 +0800
> Robert Hoo  wrote:
> 
> > The Intel Optane PMem DSM Interface, Version 2.0 [1], is the up-to-
> > date
> > spec for NVDIMM _DSM definition, which supports revision_id == 2.
> > 
> > Nevertheless, Rev.2 of NVDIMM _DSM has no functional change on
> > those Label
> > Data _DSM Functions, which are the only ones implemented for
> > vNVDIMM.
> > So, simple change to support this revision_id == 2 case.
> > 
> > [1] 
> > https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf
> 
> pls enumerate functions that QEMU implement and that are supported by
> rev=2,
> do we really need rev2 ?

No matter rev.1 or rev.2, current QEMU implements only the three label
methods: get namespace label data size (func index 4), get namespace
label data (func index 5), set namespace label data (func index 6).
In both rev.1 an rev.2, these 3 _DSM label methods are deprecated by
ACPI Label methods. So, okay, we don't really need rev.2, at present.
> 
> also don't we need make sure that rev1 only function are excluded?
> /spec above says, functions 3-6 are deprecated and limited to rev1
> only/
> "
> Warning: This function has been deprecated in preference to the ACPI
> 6.2 _LSW (Label Storage Write)
> NVDIMM Device Interface and is only supported with Arg1 – Revision Id
> = 1. It is included here for
> backwards compatibility with existing Arg1 - Revision Id = 1
> implementations.
> "
Well, they're deprecated, not obsoleted, so still included, I think.
Anyway, as said above, we don't need this patch at this moment, let's
keep it unchanged.
> 
> > 
> > Signed-off-by: Robert Hoo 
> > Reviewed-by: Jingqi Liu 
> > ---
> >  hw/acpi/nvdimm.c | 10 +++---
> >  1 file changed, 7 insertions(+), 3 deletions(-)
> > 
> > diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
> > index 0ab247a870..59b42afcf1 100644
> > --- a/hw/acpi/nvdimm.c
> > +++ b/hw/acpi/nvdimm.c
> > @@ -849,9 +849,13 @@ nvdimm_dsm_write(void *opaque, hwaddr addr,
> > uint64_t val, unsigned size)
> >  nvdimm_debug("Revision 0x%x Handler 0x%x Function 0x%x.\n",
> > in->revision,
> >   in->handle, in->function);
> >  
> > -if (in->revision != 0x1 /* Currently we only support DSM Spec
> > Rev1. */) {
> > -nvdimm_debug("Revision 0x%x is not supported, expect
> > 0x%x.\n",
> > - in->revision, 0x1);
> > +/*
> > + * Current NVDIMM _DSM Spec supports Rev1 and Rev2
> > + * Intel® OptanePersistent Memory Module DSM Interface,
> > Revision 2.0
> > + */
> > +if (in->revision != 0x1 && in->revision != 0x2) {
> > +nvdimm_debug("Revision 0x%x is not supported, expect 0x1
> > or 0x2.\n",
> > + in->revision);
> >  nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT,
> > dsm_mem_addr);
> >  goto exit;
> >  }
> 
> 

Re: [PATCH 3/3] gitlab: honour QEMU_CI variable in edk2/opensbi jobs

[Daniel P . Berrangé]

On Fri, Jul 01, 2022 at 07:13:44AM +0530, Richard Henderson wrote:
> On 6/29/22 22:36, Daniel P. Berrangé wrote:
> > +# In forks, if QEMU_CI=1 is set, then create manual job
> > +# if the branch/tag starts with 'edk2'
> > +- if: '$QEMU_CI == "1" && $CI_PROJECT_NAMESPACE != "qemu-project" && 
> > $CI_COMMIT_REF_NAME =~ /^edk2/'
> > +  when: manual
> > +
> > +# In forks, if QEMU_CI=1 is set, then create manual job
> > +# if last commit msg contains 'EDK2' (case insensitive)
> > +- if: '$QEMU_CI == "1" && $CI_PROJECT_NAMESPACE != "qemu-project" && 
> > $CI_COMMIT_MESSAGE =~ /edk2/i'
> > +  when: on_success
> 
> manual on last line?

/facepalmYes, of course.


With regards,
Daniel
-- 
|: https://berrange.com  -o-https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o-https://fstop138.berrange.com :|
|: https://entangle-photo.org-o-https://www.instagram.com/dberrange :|

[PATCH 03/11] hw/rtc/ls7a_rtc: Remove unimplemented device in realized function

[Xiaojuan Yang]

Remove the unimplemented device when realized ls7a RTC, as it is not uesd.

Signed-off-by: Xiaojuan Yang 
---
 hw/rtc/ls7a_rtc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index 780144b9da..f1e7a660e9 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -461,7 +461,6 @@ static void ls7a_rtc_realize(DeviceState *dev, Error **errp)
 d->save_toy_year = 0;
 d->save_rtc = 0;
 
-create_unimplemented_device("mmio fallback 1", 0x10013ffc, 0x4);
 }
 
 static int ls7a_rtc_pre_save(void *opaque)
-- 
2.31.1

[PATCH v2 00/11] Fix bugs for LoongArch virt machine

[Xiaojuan Yang]

This series fix some bugs for LoongArch virt machine. Including
RTC device emulation, ECFG reg emulation, timer clear function,
and IPI device function, etc.

Xiaojuan Yang (11):
  hw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch writing function
  hw/rtc/ls7a_rtc: Fix timer call back function
  hw/rtc/ls7a_rtc: Remove unimplemented device in realized function
  hw/rtc/ls7a_rtc: Add reset function
  hw/rtc/ls7a_rtc: Fix rtc enable and disable function
  hw/rtc/ls7a_rtc: Use tm struct pointer as arguments in
toy_time_to_val()
  hw/rtc/ls7a_rtc: Fix 'calculate' spelling errors
  target/loongarch: Fix the meaning of ECFG reg's VS field
  target/loongarch: Add lock when writing timer clear reg
  hw/intc/loongarch_ipi: Fix ipi device access of 64bits
  hw/intc/loongarch_ipi: Fix mail send and any send function

 hw/intc/loongarch_ipi.c |  83 +---
 hw/loongarch/loongson3.c|   5 +-
 hw/rtc/ls7a_rtc.c   | 131 +---
 include/hw/intc/loongarch_ipi.h |   7 +-
 target/loongarch/cpu.c  |   4 +
 target/loongarch/csr_helper.c   |   2 +
 6 files changed, 122 insertions(+), 110 deletions(-)

-- 
2.31.1

Re: [RFC PATCH v4 10/11] qemu-sockets: introduce socket_uri()

[Laurent Vivier]

On 29/06/2022 13:26, Markus Armbruster wrote:

Laurent Vivier  writes:


Format a string URI from a SocketAddress.

Original code from hmp-cmds.c:SocketAddress_to_str()

Replace 'tcp:' by 'inet:' (because 'inet' can be also 'udp').


This one's merely misleading.


Replace 'tcp:' by 'vsock:' with vsock socket type.


This one's positively wrong: it makes a vsock address look like an inet
address with CID misinterpreted as host.  Goes back to commit 9aca82ba31
"migration: Create socket-address parameter"


Signed-off-by: Laurent Vivier 
---
  include/qemu/sockets.h |  2 +-
  monitor/hmp-cmds.c | 23 +--
  util/qemu-sockets.c| 20 
  3 files changed, 22 insertions(+), 23 deletions(-)

diff --git a/include/qemu/sockets.h b/include/qemu/sockets.h
index 47194b9732f8..3e2ae7e21705 100644
--- a/include/qemu/sockets.h
+++ b/include/qemu/sockets.h
@@ -41,6 +41,7 @@ int unix_listen(const char *path, Error **errp);
  int unix_connect(const char *path, Error **errp);
  
  SocketAddress *socket_parse(const char *str, Error **errp);

+char *socket_uri(SocketAddress *addr);
  int socket_connect(SocketAddress *addr, Error **errp);
  int socket_listen(SocketAddress *addr, int num, Error **errp);
  void socket_listen_cleanup(int fd, Error **errp);
@@ -123,5 +124,4 @@ SocketAddress *socket_address_flatten(SocketAddressLegacy 
*addr);
   * Return 0 on success.
   */
  int socket_address_parse_named_fd(SocketAddress *addr, Error **errp);
-
  #endif /* QEMU_SOCKETS_H */
diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c
index 47a27326eef7..eb0fe0a293b8 100644
--- a/monitor/hmp-cmds.c
+++ b/monitor/hmp-cmds.c
@@ -197,27 +197,6 @@ void hmp_info_mice(Monitor *mon, const QDict *qdict)
  qapi_free_MouseInfoList(mice_list);
  }
  
-static char *SocketAddress_to_str(SocketAddress *addr)

-{
-switch (addr->type) {
-case SOCKET_ADDRESS_TYPE_INET:
-return g_strdup_printf("tcp:%s:%s",
-   addr->u.inet.host,
-   addr->u.inet.port);
-case SOCKET_ADDRESS_TYPE_UNIX:
-return g_strdup_printf("unix:%s",
-   addr->u.q_unix.path);
-case SOCKET_ADDRESS_TYPE_FD:
-return g_strdup_printf("fd:%s", addr->u.fd.str);
-case SOCKET_ADDRESS_TYPE_VSOCK:
-return g_strdup_printf("tcp:%s:%s",
-   addr->u.vsock.cid,
-   addr->u.vsock.port);
-default:
-return g_strdup("unknown address type");
-}
-}
-
  void hmp_info_migrate(Monitor *mon, const QDict *qdict)
  {
  MigrationInfo *info;
@@ -375,7 +354,7 @@ void hmp_info_migrate(Monitor *mon, const QDict *qdict)
  monitor_printf(mon, "socket address: [\n");
  
  for (addr = info->socket_address; addr; addr = addr->next) {

-char *s = SocketAddress_to_str(addr->value);
+char *s = socket_uri(addr->value);
  monitor_printf(mon, "\t%s\n", s);
  g_free(s);
  }
diff --git a/util/qemu-sockets.c b/util/qemu-sockets.c
index 13b5b197f9ea..4efc2ce8b074 100644
--- a/util/qemu-sockets.c
+++ b/util/qemu-sockets.c
@@ -1098,6 +1098,26 @@ int unix_connect(const char *path, Error **errp)
  return sock;
  }
  
+char *socket_uri(SocketAddress *addr)

+{
+switch (addr->type) {
+case SOCKET_ADDRESS_TYPE_INET:
+return g_strdup_printf("inet:%s:%s",
+   addr->u.inet.host,
+   addr->u.inet.port);
+case SOCKET_ADDRESS_TYPE_UNIX:
+return g_strdup_printf("unix:%s",
+   addr->u.q_unix.path);
+case SOCKET_ADDRESS_TYPE_FD:
+return g_strdup_printf("fd:%s", addr->u.fd.str);
+case SOCKET_ADDRESS_TYPE_VSOCK:
+return g_strdup_printf("vsock:%s:%s",
+   addr->u.vsock.cid,
+   addr->u.vsock.port);
+default:
+return g_strdup("unknown address type");
+}
+}
  
  SocketAddress *socket_parse(const char *str, Error **errp)

  {


Why do you move and rename?  I'm not objecting, I just want to know the
reason :)


I missed your comment before sending the v5.

I move and rename because this function is the counterpart for socket_parse(), so make the 
name similar and put the function in the same place.


Perhaps it should also be improved to display all the options ("keep-alive", "mptcp", ...) 
that socket_parse() is able to decode?


Thanks,
Laurent

[PATCH 01/11] hw/rtc/ls7a_rtc: Fix uninitialied bugs and toymatch writing function

[Xiaojuan Yang]

1. Initialize the tm struct in toymatch_write() and ls7a_toy_start() to
   fix uninitialized bugs.
2. Fix toymatch_val_to_time function. By the document, when we calculate
   the expiration year, we should first get current year, and replace the
   0-5 bits with toymatch's 26-31 bits.

Fixes: Coverity CID 1489766, 1489763

Signed-off-by: Xiaojuan Yang 
---
 hw/rtc/ls7a_rtc.c | 20 +++-
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index fe6710310f..b88a90de8b 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -148,8 +148,9 @@ static inline uint64_t toy_time_to_val_year(struct tm tm)
 return year;
 }
 
-static inline void toymatch_val_to_time(uint64_t val, struct tm *tm)
+static inline void toymatch_val_to_time(LS7ARtcState *s, uint64_t val, struct 
tm *tm)
 {
+qemu_get_timedate(tm, s->offset_toy);
 tm->tm_sec = FIELD_EX32(val, TOY_MATCH, SEC);
 tm->tm_min = FIELD_EX32(val, TOY_MATCH, MIN);
 tm->tm_hour = FIELD_EX32(val, TOY_MATCH, HOUR);
@@ -158,17 +159,18 @@ static inline void toymatch_val_to_time(uint64_t val, 
struct tm *tm)
 tm->tm_year += (FIELD_EX32(val, TOY_MATCH, YEAR) - (tm->tm_year & 0x3f));
 }
 
-static void toymatch_write(LS7ARtcState *s, struct tm *tm, uint64_t val, int 
num)
+static void toymatch_write(LS7ARtcState *s, uint64_t val, int num)
 {
 int64_t now, expire_time;
+struct tm tm = {};
 
 /* it do not support write when toy disabled */
 if (toy_enabled(s)) {
 s->toymatch[num] = val;
 /* caculate expire time */
 now = qemu_clock_get_ms(rtc_clock);
-toymatch_val_to_time(val, tm);
-expire_time = now + (qemu_timedate_diff(tm) - s->offset_toy) * 1000;
+toymatch_val_to_time(s, val, );
+expire_time = now + (qemu_timedate_diff() - s->offset_toy) * 1000;
 timer_mod(s->toy_timer[num], expire_time);
 }
 }
@@ -223,7 +225,7 @@ static void ls7a_toy_start(LS7ARtcState *s)
 {
 int i;
 uint64_t expire_time, now;
-struct tm tm;
+struct tm tm = {};
 /*
  * need to recaculate toy offset
  * and expire time when enable it.
@@ -236,7 +238,7 @@ static void ls7a_toy_start(LS7ARtcState *s)
 
 /* recaculate expire time and enable timer */
 for (i = 0; i < TIMER_NUMS; i++) {
-toymatch_val_to_time(s->toymatch[i], );
+toymatch_val_to_time(s, s->toymatch[i], );
 expire_time = now + (qemu_timedate_diff() - s->offset_toy) * 1000;
 timer_mod(s->toy_timer[i], expire_time);
 }
@@ -352,13 +354,13 @@ static void ls7a_rtc_write(void *opaque, hwaddr addr,
 }
 break;
 case SYS_TOYMATCH0:
-toymatch_write(s, , val, 0);
+toymatch_write(s, val, 0);
 break;
 case SYS_TOYMATCH1:
-toymatch_write(s, , val, 1);
+toymatch_write(s, val, 1);
 break;
 case SYS_TOYMATCH2:
-toymatch_write(s, , val, 2);
+toymatch_write(s, val, 2);
 break;
 case SYS_RTCCTRL:
 /* get old ctrl */
-- 
2.31.1

Re: [PATCH v4 04/45] target/arm: Mark ADR as non-streaming

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:26, Richard Henderson
 wrote:
>
> Mark ADR as a non-streaming instruction, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Removing entries from sme-fa64.decode is an easy way to see
> what remains to be done.
>
> Signed-off-by: Richard Henderson 

Yes, this is a nice way to do it and easy to review.

Reviewed-by: Peter Maydell 

thanks
-- PMM

RE: [PATCH] gtk: Add show_tabs=on|off command line option.

[Zhang, Chen]

> -Original Message-
> From: Qemu-devel  bounces+chen.zhang=intel@nongnu.org> On Behalf Of Felix xq
> Queißner
> Sent: Tuesday, June 28, 2022 12:44 AM
> To: qemu-devel@nongnu.org
> Cc: kra...@redhat.com; th...@redhat.com; Felix "xq" Queißner
> 
> Subject: [PATCH] gtk: Add show_tabs=on|off command line option.
> 
> The patch adds "show_tabs" command line option for GTK ui similar to
> "grab_on_hover". This option allows tabbed view mode to not have to be
> enabled by hand at each start of the VM.
> 
> Signed-off-by: Felix "xq" Queißner 

Thanks your patch, but please use your real name to sign a patch.
For the details:
docs/devel/submitting-a-patch.rst

Thanks
Chen


> ---
>  qapi/ui.json| 5 -
>  qemu-options.hx | 2 +-
>  ui/gtk.c| 4 
>  3 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/qapi/ui.json b/qapi/ui.json index 413371d5e8..049e7957a9 100644
> --- a/qapi/ui.json
> +++ b/qapi/ui.json
> @@ -1195,12 +1195,15 @@
>  #   assuming the guest will resize the display to match
>  #   the window size then.  Otherwise it defaults to "off".
>  #   Since 3.1
> +# @show-tabs:   Displays the tab items by default.
> +#   Since 7.1
>  #
>  # Since: 2.12
>  ##
>  { 'struct'  : 'DisplayGTK',
>'data': { '*grab-on-hover' : 'bool',
> -'*zoom-to-fit'   : 'bool'  } }
> +'*zoom-to-fit'   : 'bool',
> +'*show-tabs' : 'bool'  } }
> 
>  ##
>  # @DisplayEGLHeadless:
> diff --git a/qemu-options.hx b/qemu-options.hx index
> 377d22fbd8..2b279afff7 100644
> --- a/qemu-options.hx
> +++ b/qemu-options.hx
> @@ -1937,7 +1937,7 @@ DEF("display", HAS_ARG, QEMU_OPTION_display,
>  "[,window-close=on|off]\n"
>  #endif
>  #if defined(CONFIG_GTK)
> -"-display gtk[,full-screen=on|off][,gl=on|off][,grab-on-hover=on|off]\n"
> +"-display gtk[,full-screen=on|off][,gl=on|off][,grab-on-
> hover=on|off][,show-tabs=on|off]\n"
>  "[,show-cursor=on|off][,window-close=on|off]\n"
>  #endif
>  #if defined(CONFIG_VNC)
> diff --git a/ui/gtk.c b/ui/gtk.c
> index 2a791dd2aa..1467b8c7d7 100644
> --- a/ui/gtk.c
> +++ b/ui/gtk.c
> @@ -2390,6 +2390,10 @@ static void gtk_display_init(DisplayState *ds,
> DisplayOptions *opts)
>  opts->u.gtk.grab_on_hover) {
>  gtk_menu_item_activate(GTK_MENU_ITEM(s->grab_on_hover_item));
>  }
> +if (opts->u.gtk.has_show_tabs &&
> +opts->u.gtk.show_tabs) {
> +gtk_menu_item_activate(GTK_MENU_ITEM(s->show_tabs_item));
> +}
>  gd_clipboard_init(s);
>  }
> 
> --
> 2.36.1
> 

Re: [PATCH v3] ui/cocoa: Take refresh rate into account

[Gerd Hoffmann]

On Tue, Jun 21, 2022 at 09:51:38AM +0100, Peter Maydell wrote:
> On Mon, 20 Jun 2022 at 21:29, Akihiko Odaki  wrote:
> >
> > Retreieve the refresh rate of the display and reflect it with
> > dpy_set_ui_info() and update_displaychangelistener(), allowing the
> > guest and DisplayChangeListener to consume the information.
> 
> But why? What goes wrong if we don't bother to do this?

Nothing goes wrong.  This provides a hint to the guest how often the
display is updated, so the guest has the chance to adapt to that.
When we run 30 Hz display updates on the host side it is pointless for
the guest to update the screen at 60Hz frequency, the guest can spare
some cpu cycles instead.

[ this should be better explained in the commit message ]

take care,
  Gerd

Re: [PATCH v3 3/4] docs: rSTify GettingStartedDevelopers wiki; move it to QEMU Git

[Peter Maydell]

On Mon, 6 Jun 2022 at 17:43, Kashyap Chamarthy  wrote:
>
> Converted the wiki[1] from Markdown to rST using:
>
> $> pandoc -f Mediawiki -t rst getting-started-developers.wiki
> -o getting-started-developers.rst
>
> It's a 1-1 conversion (I double-checked to the best I could).  I've also
> checked that the hyperlinks work correctly post-conversion.
>
> [1] https://wiki.qemu.org/Documentation/GettingStartedDevelopers
>
> Signed-off-by: Kashyap Chamarthy 

> +-  Its OK if your new implementation doesn't do everything (or has some

I noticed a typo here (should be "It's"), but we should fix
that separately from this automated conversion.

Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [QEMU PATCH v2 6/6] acpi/nvdimm: Define trace events for NVDIMM and substitute nvdimm_debug()

[Robert Hoo]

On Thu, 2022-06-16 at 14:35 +0200, Igor Mammedov wrote:
> On Mon, 30 May 2022 11:40:47 +0800
> Robert Hoo  wrote:
> 
> suggest to put this patch as the 1st in series
> (well you can rebase it on current master and
> post that right away for merging since it doesn't
> really depend on other patches, and post new patches on
> top (whenever they are ready) will use tracing)

OK
> 
> > Signed-off-by: Robert Hoo 
> > Reviewed-by: Jingqi Liu 
> > ---
> >  hw/acpi/nvdimm.c| 38 ++---
> > -
> >  hw/acpi/trace-events| 14 ++
> >  include/hw/mem/nvdimm.h |  8 
> >  3 files changed, 32 insertions(+), 28 deletions(-)
> > 
> > diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
> > index 50ee85866b..fc777990e6 100644
> > --- a/hw/acpi/nvdimm.c
> > +++ b/hw/acpi/nvdimm.c
> > @@ -35,6 +35,7 @@
> >  #include "hw/nvram/fw_cfg.h"
> >  #include "hw/mem/nvdimm.h"
> >  #include "qemu/nvdimm-utils.h"
> > +#include "trace.h"
> >  
> >  /*
> >   * define Byte Addressable Persistent Memory (PM) Region according
> > to
> > @@ -558,8 +559,8 @@ static void
> > nvdimm_dsm_func_read_fit(NVDIMMState *state, NvdimmDsmIn *in,
> >  
> >  fit = fit_buf->fit;
> >  
> > -nvdimm_debug("Read FIT: offset 0x%x FIT size 0x%x Dirty
> > %s.\n",
> > - read_fit->offset, fit->len, fit_buf->dirty ?
> > "Yes" : "No");
> > +trace_acpi_nvdimm_read_fit(read_fit->offset, fit->len,
> > +   fit_buf->dirty ? "Yes" : "No");
> >  
> >  if (read_fit->offset > fit->len) {
> >  func_ret_status = NVDIMM_DSM_RET_STATUS_INVALID;
> > @@ -667,7 +668,7 @@ static void nvdimm_dsm_label_size(NVDIMMDevice
> > *nvdimm, hwaddr dsm_mem_addr)
> >  label_size = nvdimm->label_size;
> >  mxfer = nvdimm_get_max_xfer_label_size();
> >  
> > -nvdimm_debug("label_size 0x%x, max_xfer 0x%x.\n", label_size,
> > mxfer);
> > +trace_acpi_nvdimm_label_info(label_size, mxfer);
> >  
> >  label_size_out.func_ret_status =
> > cpu_to_le32(NVDIMM_DSM_RET_STATUS_SUCCESS);
> >  label_size_out.label_size = cpu_to_le32(label_size);
> > @@ -683,20 +684,18 @@ static uint32_t
> > nvdimm_rw_label_data_check(NVDIMMDevice *nvdimm,
> >  uint32_t ret = NVDIMM_DSM_RET_STATUS_INVALID;
> >  
> >  if (offset + length < offset) {
> > -nvdimm_debug("offset 0x%x + length 0x%x is overflow.\n",
> > offset,
> > - length);
> > +trace_acpi_nvdimm_label_overflow(offset, length);
> >  return ret;
> >  }
> >  
> >  if (nvdimm->label_size < offset + length) {
> > -nvdimm_debug("position 0x%x is beyond label data (len = %"
> > PRIx64 ").\n",
> > - offset + length, nvdimm->label_size);
> > +trace_acpi_nvdimm_label_oversize(offset + length, nvdimm-
> > >label_size);
> >  return ret;
> >  }
> >  
> >  if (length > nvdimm_get_max_xfer_label_size()) {
> > -nvdimm_debug("length (0x%x) is larger than max_xfer
> > (0x%x).\n",
> > - length, nvdimm_get_max_xfer_label_size());
> > +trace_acpi_nvdimm_label_xfer_exceed(length,
> > +nvdimm_get_max_xfer_la
> > bel_size());
> >  return ret;
> >  }
> >  
> > @@ -718,8 +717,8 @@ static void
> > nvdimm_dsm_get_label_data(NVDIMMDevice *nvdimm,
> >  get_label_data->offset = le32_to_cpu(get_label_data->offset);
> >  get_label_data->length = le32_to_cpu(get_label_data->length);
> >  
> > -nvdimm_debug("Read Label Data: offset 0x%x length 0x%x.\n",
> > - get_label_data->offset, get_label_data->length);
> > +trace_acpi_nvdimm_read_label(get_label_data->offset,
> > + get_label_data->length);
> >  
> >  status = nvdimm_rw_label_data_check(nvdimm, get_label_data-
> > >offset,
> >  get_label_data->length);
> > @@ -755,8 +754,8 @@ static void
> > nvdimm_dsm_set_label_data(NVDIMMDevice *nvdimm,
> >  set_label_data->offset = le32_to_cpu(set_label_data->offset);
> >  set_label_data->length = le32_to_cpu(set_label_data->length);
> >  
> > -nvdimm_debug("Write Label Data: offset 0x%x length 0x%x.\n",
> > - set_label_data->offset, set_label_data->length);
> > +trace_acpi_nvdimm_write_label(set_label_data->offset,
> > +  set_label_data->length);
> >  
> >  status = nvdimm_rw_label_data_check(nvdimm, set_label_data-
> > >offset,
> >  set_label_data->length);
> > @@ -833,7 +832,7 @@ static void nvdimm_dsm_device(uint32_t
> > nv_handle, NvdimmDsmIn *dsm_in,
> >  static uint64_t
> >  nvdimm_method_read(void *opaque, hwaddr addr, unsigned size)
> >  {
> > -nvdimm_debug("BUG: we never read NVDIMM Method IO Port.\n");
> > +trace_acpi_nvdimm_read_io_port();
> >  return 0;
> >  }
> >  
> > @@ -843,20 +842,19 @@ nvdimm_dsm_handle(void *opaque, 

[PATCH 09/11] target/loongarch: Add lock when writing timer clear reg

[Xiaojuan Yang]

There is such error info when running linux kernel:
tcg_handle_interrupt: assertion failed: (qemu_mutex_iothread_locked()).
calling stack:
#0 in raise () at /lib64/libc.so.6
#1 in abort () at /lib64/libc.so.6
#2 in g_assertion_message_expr.cold () at /lib64/libglib-2.0.so.0
#3 in g_assertion_message_expr () at /lib64/libglib-2.0.so.0
#4 in tcg_handle_interrupt (cpu=0x63230800, mask=2) at 
../accel/tcg/tcg-accel-ops.c:79
#5 in cpu_interrupt (cpu=0x63230800, mask=2) at ../softmmu/cpus.c:248
#6 in loongarch_cpu_set_irq (opaque=0x63230800, irq=11, level=0)
   at ../target/loongarch/cpu.c:100
#7 in helper_csrwr_ticlr (env=0x63239440, val=1) at 
../target/loongarch/csr_helper.c:85
#8 in code_gen_buffer ()
#9 in cpu_tb_exec (cpu=0x63230800, itb=0x7fff946ac280, 
tb_exit=0x7ffe4fcb6c30)
   at ../accel/tcg/cpu-exec.c:358

Add mutex iothread lock around loongarch_cpu_set_irq in csrwr_ticlr() to
fix the bug.

Signed-off-by: Xiaojuan Yang 
---
 target/loongarch/csr_helper.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/loongarch/csr_helper.c b/target/loongarch/csr_helper.c
index 24a9389364..7e02787895 100644
--- a/target/loongarch/csr_helper.c
+++ b/target/loongarch/csr_helper.c
@@ -81,7 +81,9 @@ target_ulong helper_csrwr_ticlr(CPULoongArchState *env, 
target_ulong val)
 int64_t old_v = 0;
 
 if (val & 0x1) {
+qemu_mutex_lock_iothread();
 loongarch_cpu_set_irq(cpu, IRQ_TIMER, 0);
+qemu_mutex_unlock_iothread();
 }
 return old_v;
 }
-- 
2.31.1

[PATCH 10/11] hw/intc/loongarch_ipi: Fix ipi device access of 64bits

[Xiaojuan Yang]

In general loongarch ipi device, 32bit registers is emulated, however for
anysend/mailsend device only 64bit register access is supported. So separate
the ipi memory region into two regions, including 32 bits and 64 bits.

Signed-off-by: Xiaojuan Yang 
---
 hw/intc/loongarch_ipi.c | 38 +++--
 hw/loongarch/loongson3.c|  5 -
 include/hw/intc/loongarch_ipi.h |  7 +++---
 3 files changed, 39 insertions(+), 11 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index 66bee93675..553e88703d 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -150,12 +150,6 @@ static void loongarch_ipi_writel(void *opaque, hwaddr 
addr, uint64_t val,
 case IOCSR_IPI_SEND:
 ipi_send(val);
 break;
-case IOCSR_MAIL_SEND:
-mail_send(val);
-break;
-case IOCSR_ANY_SEND:
-any_send(val);
-break;
 default:
 qemu_log_mask(LOG_UNIMP, "invalid write: %x", (uint32_t)addr);
 break;
@@ -172,6 +166,32 @@ static const MemoryRegionOps loongarch_ipi_ops = {
 .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
+/* mail send and any send only support writeq */
+static void loongarch_ipi_writeq(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+addr &= 0xfff;
+switch (addr) {
+case MAIL_SEND_OFFSET:
+mail_send(val);
+break;
+case ANY_SEND_OFFSET:
+any_send(val);
+break;
+default:
+   break;
+}
+}
+
+static const MemoryRegionOps loongarch_ipi64_ops = {
+.write = loongarch_ipi_writeq,
+.impl.min_access_size = 8,
+.impl.max_access_size = 8,
+.valid.min_access_size = 4,
+.valid.max_access_size = 8,
+.endianness = DEVICE_LITTLE_ENDIAN,
+};
+
 static void loongarch_ipi_init(Object *obj)
 {
 int cpu;
@@ -187,8 +207,12 @@ static void loongarch_ipi_init(Object *obj)
 lams = LOONGARCH_MACHINE(machine);
 for (cpu = 0; cpu < MAX_IPI_CORE_NUM; cpu++) {
 memory_region_init_io(>ipi_iocsr_mem[cpu], obj, _ipi_ops,
->ipi_core[cpu], "loongarch_ipi_iocsr", 
0x100);
+>ipi_core[cpu], "loongarch_ipi_iocsr", 0x48);
 sysbus_init_mmio(sbd, >ipi_iocsr_mem[cpu]);
+
+memory_region_init_io(>ipi64_iocsr_mem[cpu], obj, 
_ipi64_ops,
+  >ipi_core[cpu], "loongarch_ipi64_iocsr", 
0x118);
+sysbus_init_mmio(sbd, >ipi64_iocsr_mem[cpu]);
 qdev_init_gpio_out(DEVICE(obj), >ipi_core[cpu].irq, 1);
 }
 }
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index bd20ebbb78..0cc023bd3c 100644
--- a/hw/loongarch/loongson3.c
+++ b/hw/loongarch/loongson3.c
@@ -230,7 +230,10 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
 /* IPI iocsr memory region */
 memory_region_add_subregion(>system_iocsr, SMP_IPI_MAILBOX,
 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
-cpu));
+cpu * 2));
+memory_region_add_subregion(>system_iocsr, MAIL_SEND_ADDR,
+sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi),
+cpu * 2 + 1));
 /* extioi iocsr memory region */
 memory_region_add_subregion(>system_iocsr, APIC_BASE,
 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi),
diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
index 996ed7ea93..0ee48fca55 100644
--- a/include/hw/intc/loongarch_ipi.h
+++ b/include/hw/intc/loongarch_ipi.h
@@ -24,8 +24,9 @@
 #define IOCSR_MAIL_SEND   0x48
 #define IOCSR_ANY_SEND0x158
 
-/* IPI system memory address */
-#define IPI_SYSTEM_MEM0x1fe01000
+#define MAIL_SEND_ADDR(SMP_IPI_MAILBOX + IOCSR_MAIL_SEND)
+#define MAIL_SEND_OFFSET  0
+#define ANY_SEND_OFFSET   (IOCSR_ANY_SEND - IOCSR_MAIL_SEND)
 
 #define MAX_IPI_CORE_NUM  4
 #define MAX_IPI_MBX_NUM   4
@@ -46,7 +47,7 @@ typedef struct IPICore {
 struct LoongArchIPI {
 SysBusDevice parent_obj;
 MemoryRegion ipi_iocsr_mem[MAX_IPI_CORE_NUM];
-MemoryRegion ipi_system_mem[MAX_IPI_CORE_NUM];
+MemoryRegion ipi64_iocsr_mem[MAX_IPI_CORE_NUM];
 };
 
 #endif
-- 
2.31.1

Re: [PATCH] block/rbd: support driver-specific reopen

[Hanna Reitz]

On 13.04.22 14:26, Raphael Pour wrote:

This patch completes the reopen functionality for an attached RBD where altered
driver options can be passed to. This is necessary to move RBDs between ceph
clusters without interrupting QEMU, where some ceph settings need to be 
adjusted.

The reopen_prepare method early returns if no rbd-specific driver options are
given to maintain compatible with the previous behavior by dropping all
generic block layer options. Otherwise the reopen acts similar to qemu_rbd_open.

The reopen_commit tears down the old state and replaces it with the new
one.

The reopen_abort drops an ongoing reopen.

Signed-off-by: Raphael Pour 
---
  block/rbd.c | 206 ++--
  1 file changed, 201 insertions(+), 5 deletions(-)

diff --git a/block/rbd.c b/block/rbd.c
index 6caf35cbba..e7b45d1c50 100644
--- a/block/rbd.c
+++ b/block/rbd.c
@@ -1029,19 +1029,213 @@ out:


I think the comment above this point (“Since RBD is currently...”) 
should either be dropped now or moved above the `if (new_s->snap && 
...)` condition.



  static int qemu_rbd_reopen_prepare(BDRVReopenState *state,
 BlockReopenQueue *queue, Error **errp)
  {
-BDRVRBDState *s = state->bs->opaque;
-int ret = 0;
+BDRVRBDState *new_s = state->bs->opaque;
+BlockdevOptionsRbd *opts = NULL;
+const QDictEntry *e;
+Error *local_err = NULL;
+char *keypairs, *secretid;
+rbd_image_info_t info;
+int r = 0;
  
-if (s->snap && state->flags & BDRV_O_RDWR) {

+if (new_s->snap && state->flags & BDRV_O_RDWR) {
  error_setg(errp,
 "Cannot change node '%s' to r/w when using RBD snapshot",
 bdrv_get_device_or_node_name(state->bs));


Is this still the case?  I understand next to nothing about RBD, but can 
the user not make it R/W if they simultaneously decide to switch from 
snapshot to not-snapshot?


(I.e. shouldn’t we just let the generic code below figure out whether 
we’ll get an error with the whole new configuration?)



-ret = -EINVAL;
+r = -EINVAL;


If it is still relevant: Why not return the error immediately here?

If we don’t, it looks like a couple of bad things might happen below; 
like `r` getting overwritten, or `errp` getting set twice (which would 
cause an assertion failure).



  }
  
-return ret;

+/*
+ * Remove all keys from the generic layer which
+ * can't be converted by rbd
+ */


Does any other driver do this?  Shouldn’t we leave them there so that 
the generic layer can verify that they aren’t changed?



+qdict_del(state->options, "driver");
+qdict_del(state->options, "node-name");
+qdict_del(state->options, "auto-read-only");
+qdict_del(state->options, "discard");
+qdict_del(state->options, "cache");


Because AFAIU this would mean that users could attempt to change e.g. 
the @cache option, and wouldn’t receive an error back, even though there 
is no support for changing it.



+
+/*
+ * To maintain the compatibility prior the rbd-reopen,
+ * where the generic layer can be altered without any
+ * rbd argument given,


What does “the generic layer can be altered” mean?  As far as I 
understand, it was only possible to change between read/write and 
read-only access.



 we must early return if there
+ * aren't any rbd-specific options left.
+ */
+if (qdict_size(state->options) == 0) {
+return r;
+}
+
+new_s = state->opaque = g_new0(BDRVReopenState, 1);


This seems like it’s only “new” from this point on, but before that, it 
was the old state.  I find it confusing that a variable named “new_s” 
apparently stored the old state before this point, so if that were the 
case, I’d use a different variable (e.g. the previously existing `s`) 
for `state->bs->opaque`.



+
+keypairs = g_strdup(qdict_get_try_str(state->options, "=keyvalue-pairs"));
+if (keypairs) {
+qdict_del(state->options, "=keyvalue-pairs");
+}
+
+secretid = g_strdup(qdict_get_try_str(state->options, "password-secret"));
+if (secretid) {
+qdict_del(state->options, "password-secret");
+}
+
+r = qemu_rbd_convert_options(state->options, , _err);
+if (local_err) {
+/*
+ * If keypairs are present, that means some options are present in
+ * the modern option format.  Don't attempt to parse legacy option
+ * formats, as we won't support mixed usage.
+ */
+if (keypairs) {
+error_propagate(errp, local_err);
+goto out;
+}
+
+/*
+ * If the initial attempt to convert and process the options failed,
+ * we may be attempting to open an image file that has the rbd options
+ * specified in the older format consisting of all key/value pairs
+ * encoded in the filename.  Go ahead and attempt to parse the
+   

Re: [PATCH] gtk: Add show_tabs=on|off command line option.

[kra...@redhat.com]

On Fri, Jul 01, 2022 at 09:14:02AM +, Zhang, Chen wrote:
> 
> 
> > Signed-off-by: Felix "xq" Queißner 
> 
> Thanks your patch, but please use your real name to sign a patch.
> For the details:
> docs/devel/submitting-a-patch.rst

Hmm?  Felix Queißner looks like a real name to me ...

take care,
  Gerd

Re: [PATCH v2 0/3] CanoKey: Fix xHCI compatibility and CCID ZLP

[Gerd Hoffmann]

On Thu, Jun 23, 2022 at 11:16:39PM +0800, Hongren (Zenithal) Zheng wrote:
> On Mon, Jun 13, 2022 at 08:12:38PM +0800, Hongren (Zenithal) Zheng wrote:
>  
> > ---
> > v2: 
> >   * use usb_ep_get instead of recording ep_in_pointer
> >   as suggested by kraxel
> >   * CI result for v2 is at
> > https://gitlab.com/ZenithalHourlyRate/qemu/-/pipelines/562306905
> 
> Hi kraxel, is there any further feedback on this?
> 
> BTW, as the commit "add myself as CanoKey maintainer" has been
> merged, how should I submit patches on CanoKey to you and QEMU?

Sending to the list with /me Cc'ed is fine.

> For other contributors, before I can send PULL (my key is not signed yet)
> I think I should first give Reviewed-by tags then request you
> to pass them.

Yes.

Series queued up now.

thanks,
  Gerd

Re: [PATCH v2 01/10] tests/qemu-iotests: hotfix for 307, 223 output

[Hanna Reitz]

On 16.06.22 16:26, John Snow wrote:

Fixes: 58a6fdcc
Signed-off-by: John Snow 
Tested-by: Daniel P. Berrangé 
Reviewed-by: Daniel P. Berrangé 
---
  tests/qemu-iotests/223.out | 4 ++--
  tests/qemu-iotests/307.out | 4 ++--
  2 files changed, 4 insertions(+), 4 deletions(-)


Reviewed-by: Hanna Reitz 

Re: [QEMU PATCH v2 4/6] nvdimm: Implement ACPI NVDIMM Label Methods

[Robert Hoo]

On Thu, 2022-06-16 at 14:32 +0200, Igor Mammedov wrote:
> On Mon, 30 May 2022 11:40:45 +0800
> Robert Hoo  wrote:
> 
> > Recent ACPI spec [1] has defined NVDIMM Label Methods _LS{I,R,W},
> > which
> > depricates corresponding _DSM Functions defined by PMEM _DSM
> > Interface spec
> > [2].
> > 
> > In this implementation, we do 2 things
> > 1. Generalize the QEMU<->ACPI BIOS NVDIMM interface, wrap it with
> > ACPI
> > method dispatch, _DSM is one of the branches. This also paves the
> > way for
> > adding other ACPI methods for NVDIMM.
> > 2. Add _LS{I,R,W} method in each NVDIMM device in SSDT.
> > ASL form of SSDT changes can be found in next test/qtest/bios-
> > table-test
> > commit message.
> > 
> > [1] ACPI Spec v6.4, 6.5.10 NVDIMM Label Methods
> > https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf
> > [2] Intel PMEM _DSM Interface Spec v2.0, 3.10 Deprecated Functions
> > https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf
> > 
> > Signed-off-by: Robert Hoo 
> > Reviewed-by: Jingqi Liu 
> > ---
> >  hw/acpi/nvdimm.c| 424 +++-
> > 
> 
> This patch is too large and doing to many things to be reviewable.
> It needs to be split into smaller distinct chunks.
> (however hold your horses and read on)
> 
> The patch it is too intrusive and my hunch is that it breaks
> ABI and needs a bunch of compat knobs to work properly and
> that I'd like to avoid unless there is not other way around
> the problem.

Is the ABI here you mentioned the "struct NvdimmMthdIn{}" stuff?
and the compat knobs refers to related functions' input/output params?

My thoughts is that eventually, sooner or later, more ACPI methods will
be implemented per request, although now we can play the trick of
wrapper new methods over the pipe of old _DSM implementation.
Though this changes a little on existing struct NvdimmDsmIn {}, it
paves the way for the future; and actually the change is more an
extension or generalization, not fundamentally changes the framework.

In short, my point is the change/generalization/extension will be
inevitable, even if not present.
> 
> I was skeptical about this approach during v1 review and
> now I'm pretty much sure it's over-engineered and we can
> just repack data we receive from existing label _DSM functions
> to provide _LS{I,R,W} like it was suggested in v1.
> It will be much simpler and affect only AML side without
> complicating ABI and without any compat cruft and will work
> with ping-pong migration without any issues.

Ostensibly it may looks simpler, actually not, I think. The AML "common
pipe" NCAL() is already complex, it packs all _DSMs and NFIT() function
logics there, packing new stuff in/through it will be bug-prone.
Though this time we can avert touching it, as the new ACPI methods
deprecating old _DSM functionally is almost the same.
How about next time? are we going to always packing new methods logic
in NCAL()?
My point is that we should implement new methods as itself, of course,
as a general programming rule, we can/should abstract common routines,
but not packing them in one large function.
> 
> 
> >  include/hw/mem/nvdimm.h |   6 +
> >  2 files changed, 338 insertions(+), 92 deletions(-)
> > 
> > diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
> > index 59b42afcf1..50ee85866b 100644
> > --- a/hw/acpi/nvdimm.c
> > +++ b/hw/acpi/nvdimm.c
> > @@ -416,17 +416,22 @@ static void nvdimm_build_nfit(NVDIMMState
> > *state, GArray *table_offsets,
> >  
> >  #define NVDIMM_DSM_MEMORY_SIZE  4096
> >  
> > -struct NvdimmDsmIn {
> > +struct NvdimmMthdIn {
> >  uint32_t handle;
> > +uint32_t method;
> > +uint8_t  args[4088];
> > +} QEMU_PACKED;
> > +typedef struct NvdimmMthdIn NvdimmMthdIn;
> > +struct NvdimmDsmIn {
> >  uint32_t revision;
> >  uint32_t function;
> >  /* the remaining size in the page is used by arg3. */
> >  union {
> > -uint8_t arg3[4084];
> > +uint8_t arg3[4080];
> >  };
> >  } QEMU_PACKED;
> >  typedef struct NvdimmDsmIn NvdimmDsmIn;
> > -QEMU_BUILD_BUG_ON(sizeof(NvdimmDsmIn) != NVDIMM_DSM_MEMORY_SIZE);
> > +QEMU_BUILD_BUG_ON(sizeof(NvdimmMthdIn) != NVDIMM_DSM_MEMORY_SIZE);
> >  
> >  struct NvdimmDsmOut {
> >  /* the size of buffer filled by QEMU. */
> > @@ -470,7 +475,8 @@ struct NvdimmFuncGetLabelDataIn {
> >  } QEMU_PACKED;
> >  typedef struct NvdimmFuncGetLabelDataIn NvdimmFuncGetLabelDataIn;
> >  QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelDataIn) +
> > -  offsetof(NvdimmDsmIn, arg3) >
> > NVDIMM_DSM_MEMORY_SIZE);
> > +  offsetof(NvdimmDsmIn, arg3) +
> > offsetof(NvdimmMthdIn, args) >
> > +  NVDIMM_DSM_MEMORY_SIZE);
> >  
> >  struct NvdimmFuncGetLabelDataOut {
> >  /* the size of buffer filled by QEMU. */
> > @@ -488,14 +494,16 @@ struct NvdimmFuncSetLabelDataIn {
> >  } QEMU_PACKED;
> >  typedef struct NvdimmFuncSetLabelDataIn NvdimmFuncSetLabelDataIn;
> >  

[PATCH 04/11] hw/rtc/ls7a_rtc: Add reset function

[Xiaojuan Yang]

Add ls7a rtc reset function to delete timers and clear regs when rtc reset.

Signed-off-by: Xiaojuan Yang 
---
 hw/rtc/ls7a_rtc.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index f1e7a660e9..eb10cdb451 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -463,6 +463,25 @@ static void ls7a_rtc_realize(DeviceState *dev, Error 
**errp)
 
 }
 
+/* delete timer and clear reg when reset */
+static void ls7a_rtc_reset(DeviceState *dev)
+{
+int i;
+SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+LS7ARtcState *d = LS7A_RTC(sbd);
+for (i = 0; i < TIMER_NUMS; i++) {
+if (toy_enabled(d)) {
+timer_del(d->toy_timer[i]);
+}
+if (rtc_enabled(d)) {
+timer_del(d->rtc_timer[i]);
+}
+d->toymatch[i] = 0;
+d->rtcmatch[i] = 0;
+}
+d->cntrctl = 0;
+}
+
 static int ls7a_rtc_pre_save(void *opaque)
 {
 LS7ARtcState *s = LS7A_RTC(opaque);
@@ -511,6 +530,7 @@ static void ls7a_rtc_class_init(ObjectClass *klass, void 
*data)
 DeviceClass *dc = DEVICE_CLASS(klass);
 dc->vmsd = _ls7a_rtc;
 dc->realize = ls7a_rtc_realize;
+dc->reset = ls7a_rtc_reset;
 dc->desc = "ls7a rtc";
 }
 
-- 
2.31.1

[PATCH 05/11] hw/rtc/ls7a_rtc: Fix rtc enable and disable function

[Xiaojuan Yang]

Fix ls7a rtc enable and disable function. When rtc disabled, it do
not support to read or write, but the real time is still continue,
so we need not neither save the time nor update the rtc offset.

Signed-off-by: Xiaojuan Yang 
---
 hw/rtc/ls7a_rtc.c | 60 ++-
 1 file changed, 7 insertions(+), 53 deletions(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index eb10cdb451..a36aeea9dd 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -72,9 +72,6 @@ struct LS7ARtcState {
  */
 int64_t offset_toy;
 int64_t offset_rtc;
-uint64_t save_toy_mon;
-uint64_t save_toy_year;
-uint64_t save_rtc;
 int64_t data;
 int tidx;
 uint32_t toymatch[3];
@@ -140,14 +137,6 @@ static inline uint64_t toy_time_to_val_mon(struct tm tm)
 return val;
 }
 
-static inline uint64_t toy_time_to_val_year(struct tm tm)
-{
-uint64_t year;
-
-year = tm.tm_year;
-return year;
-}
-
 static inline void toymatch_val_to_time(LS7ARtcState *s, uint64_t val, struct 
tm *tm)
 {
 qemu_get_timedate(tm, s->offset_toy);
@@ -191,14 +180,6 @@ static void rtcmatch_write(LS7ARtcState *s, uint64_t val, 
int num)
 static void ls7a_toy_stop(LS7ARtcState *s)
 {
 int i;
-struct tm tm;
-/*
- * save time when disabled toy,
- * because toy time not add counters.
- */
-qemu_get_timedate(, s->offset_toy);
-s->save_toy_mon = toy_time_to_val_mon(tm);
-s->save_toy_year = toy_time_to_val_year(tm);
 
 /* delete timers, and when re-enabled, recaculate expire time */
 for (i = 0; i < TIMER_NUMS; i++) {
@@ -209,11 +190,6 @@ static void ls7a_toy_stop(LS7ARtcState *s)
 static void ls7a_rtc_stop(LS7ARtcState *s)
 {
 int i;
-uint64_t time;
-
-/* save rtc time */
-time = ls7a_rtc_ticks() + s->offset_rtc;
-s->save_rtc = time;
 
 /* delete timers, and when re-enabled, recaculate expire time */
 for (i = 0; i < TIMER_NUMS; i++) {
@@ -226,14 +202,7 @@ static void ls7a_toy_start(LS7ARtcState *s)
 int i;
 uint64_t expire_time, now;
 struct tm tm = {};
-/*
- * need to recaculate toy offset
- * and expire time when enable it.
- */
-toy_val_to_time_mon(s->save_toy_mon, );
-toy_val_to_time_year(s->save_toy_year, );
 
-s->offset_toy = qemu_timedate_diff();
 now = qemu_clock_get_ms(rtc_clock);
 
 /* recaculate expire time and enable timer */
@@ -247,14 +216,7 @@ static void ls7a_toy_start(LS7ARtcState *s)
 static void ls7a_rtc_start(LS7ARtcState *s)
 {
 int i;
-uint64_t expire_time, now;
-
-/*
- * need to recaculate rtc offset
- * and expire time when enable it.
- */
-now = ls7a_rtc_ticks();
-s->offset_rtc = s->save_rtc - now;
+uint64_t expire_time;
 
 /* recaculate expire time and enable timer */
 for (i = 0; i < TIMER_NUMS; i++) {
@@ -271,23 +233,21 @@ static uint64_t ls7a_rtc_read(void *opaque, hwaddr addr, 
unsigned size)
 
 switch (addr) {
 case SYS_TOYREAD0:
-/* if toy disabled, read save toy time */
 if (toy_enabled(s)) {
 qemu_get_timedate(, s->offset_toy);
 val = toy_time_to_val_mon(tm);
 } else {
-/* read save mon val */
-val = s->save_toy_mon;
+/* return 0 when toy disabled */
+val = 0;
 }
 break;
 case SYS_TOYREAD1:
-/* if toy disabled, read save toy time */
 if (toy_enabled(s)) {
 qemu_get_timedate(, s->offset_toy);
 val = tm.tm_year;
 } else {
-/* read save year val */
-val = s->save_toy_year;
+/* return 0 when toy disabled */
+val = 0;
 }
 break;
 case SYS_TOYMATCH0:
@@ -303,11 +263,11 @@ static uint64_t ls7a_rtc_read(void *opaque, hwaddr addr, 
unsigned size)
 val = s->cntrctl;
 break;
 case SYS_RTCREAD0:
-/* if rtc disabled, read save rtc time */
 if (rtc_enabled(s)) {
 val = ls7a_rtc_ticks() + s->offset_rtc;
 } else {
-val = s->save_rtc;
+/* return 0 when rtc disabled */
+val = 0;
 }
 break;
 case SYS_RTCMATCH0:
@@ -457,9 +417,6 @@ static void ls7a_rtc_realize(DeviceState *dev, Error **errp)
 }
 d->offset_toy = 0;
 d->offset_rtc = 0;
-d->save_toy_mon = 0;
-d->save_toy_year = 0;
-d->save_rtc = 0;
 
 }
 
@@ -515,9 +472,6 @@ static const VMStateDescription vmstate_ls7a_rtc = {
 .fields = (VMStateField[]) {
 VMSTATE_INT64(offset_toy, LS7ARtcState),
 VMSTATE_INT64(offset_rtc, LS7ARtcState),
-VMSTATE_UINT64(save_toy_mon, LS7ARtcState),
-VMSTATE_UINT64(save_toy_year, LS7ARtcState),
-VMSTATE_UINT64(save_rtc, LS7ARtcState),
 VMSTATE_UINT32_ARRAY(toymatch, LS7ARtcState, TIMER_NUMS),
 VMSTATE_UINT32_ARRAY(rtcmatch, LS7ARtcState, TIMER_NUMS),
 VMSTATE_UINT32(cntrctl, LS7ARtcState),

[PATCH 06/11] hw/rtc/ls7a_rtc: Use tm struct pointer as arguments in toy_time_to_val()

[Xiaojuan Yang]

Use pointer as arguments in toy_time_to_val() instead of struct tm.

Signed-off-by: Xiaojuan Yang 
---
 hw/rtc/ls7a_rtc.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index a36aeea9dd..85cd2d22a5 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -125,15 +125,15 @@ static inline void toy_val_to_time_year(uint64_t 
toy_year, struct tm *tm)
 }
 
 /* parse struct tm to toy value */
-static inline uint64_t toy_time_to_val_mon(struct tm tm)
+static inline uint64_t toy_time_to_val_mon(struct tm *tm)
 {
 uint64_t val = 0;
 
-val = FIELD_DP32(val, TOY, MON, tm.tm_mon + 1);
-val = FIELD_DP32(val, TOY, DAY, tm.tm_mday);
-val = FIELD_DP32(val, TOY, HOUR, tm.tm_hour);
-val = FIELD_DP32(val, TOY, MIN, tm.tm_min);
-val = FIELD_DP32(val, TOY, SEC, tm.tm_sec);
+val = FIELD_DP32(val, TOY, MON, tm->tm_mon + 1);
+val = FIELD_DP32(val, TOY, DAY, tm->tm_mday);
+val = FIELD_DP32(val, TOY, HOUR, tm->tm_hour);
+val = FIELD_DP32(val, TOY, MIN, tm->tm_min);
+val = FIELD_DP32(val, TOY, SEC, tm->tm_sec);
 return val;
 }
 
@@ -235,7 +235,7 @@ static uint64_t ls7a_rtc_read(void *opaque, hwaddr addr, 
unsigned size)
 case SYS_TOYREAD0:
 if (toy_enabled(s)) {
 qemu_get_timedate(, s->offset_toy);
-val = toy_time_to_val_mon(tm);
+val = toy_time_to_val_mon();
 } else {
 /* return 0 when toy disabled */
 val = 0;
-- 
2.31.1

[PATCH 11/11] hw/intc/loongarch_ipi: Fix mail send and any send function

[Xiaojuan Yang]

By the document of ipi mailsend device, byte is written only when the mask bit
is 0. The original code discards mask bit and overwrite the data always, this
patch fixes the issue.

Signed-off-by: Xiaojuan Yang 
---
 hw/intc/loongarch_ipi.c | 45 ++---
 1 file changed, 24 insertions(+), 21 deletions(-)

diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c
index 553e88703d..e4b1fb5366 100644
--- a/hw/intc/loongarch_ipi.c
+++ b/hw/intc/loongarch_ipi.c
@@ -50,35 +50,40 @@ static uint64_t loongarch_ipi_readl(void *opaque, hwaddr 
addr, unsigned size)
 return ret;
 }
 
-static int get_ipi_data(target_ulong val)
+static void send_ipi_data(CPULoongArchState *env, target_ulong val, 
target_ulong addr)
 {
 int i, mask, data;
 
-data = val >> 32;
-mask = (val >> 27) & 0xf;
-
+data = address_space_ldl(>address_space_iocsr, addr,
+ MEMTXATTRS_UNSPECIFIED, NULL);
+mask  = 0;
 for (i = 0; i < 4; i++) {
-if ((mask >> i) & 1) {
-data &= ~(0xff << (i * 8));
+/* bit 27 - 30 is mask for byte write */
+if (val & (0x1UL << (27 + i))) {
+mask |= 0xff << (i * 8);
 }
 }
-return data;
+
+data &= mask;
+data |= (val >> 32) & ~mask;
+address_space_stl(>address_space_iocsr, addr,
+  data, MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
 static void ipi_send(uint64_t val)
 {
 int cpuid, data;
 CPULoongArchState *env;
+CPUState *cs;
+LoongArchCPU *cpu;
 
 cpuid = (val >> 16) & 0x3ff;
 /* IPI status vector */
 data = 1 << (val & 0x1f);
-qemu_mutex_lock_iothread();
-CPUState *cs = qemu_get_cpu(cpuid);
-LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+cs = qemu_get_cpu(cpuid);
+cpu = LOONGARCH_CPU(cs);
 env = >env;
 loongarch_cpu_set_irq(cpu, IRQ_IPI, 1);
-qemu_mutex_unlock_iothread();
 address_space_stl(>address_space_iocsr, 0x1008,
   data, MEMTXATTRS_UNSPECIFIED, NULL);
 
@@ -86,23 +91,23 @@ static void ipi_send(uint64_t val)
 
 static void mail_send(uint64_t val)
 {
-int cpuid, data;
+int cpuid;
 hwaddr addr;
 CPULoongArchState *env;
+CPUState *cs;
+LoongArchCPU *cpu;
 
 cpuid = (val >> 16) & 0x3ff;
 addr = 0x1020 + (val & 0x1c);
-CPUState *cs = qemu_get_cpu(cpuid);
-LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+cs = qemu_get_cpu(cpuid);
+cpu = LOONGARCH_CPU(cs);
 env = >env;
-data = get_ipi_data(val);
-address_space_stl(>address_space_iocsr, addr,
-  data, MEMTXATTRS_UNSPECIFIED, NULL);
+send_ipi_data(env, val, addr);
 }
 
 static void any_send(uint64_t val)
 {
-int cpuid, data;
+int cpuid;
 hwaddr addr;
 CPULoongArchState *env;
 
@@ -111,9 +116,7 @@ static void any_send(uint64_t val)
 CPUState *cs = qemu_get_cpu(cpuid);
 LoongArchCPU *cpu = LOONGARCH_CPU(cs);
 env = >env;
-data = get_ipi_data(val);
-address_space_stl(>address_space_iocsr, addr,
-  data, MEMTXATTRS_UNSPECIFIED, NULL);
+send_ipi_data(env, val, addr);
 }
 
 static void loongarch_ipi_writel(void *opaque, hwaddr addr, uint64_t val,
-- 
2.31.1

[PATCH 02/11] hw/rtc/ls7a_rtc: Fix timer call back function

[Xiaojuan Yang]

Replace qemu_irq_pulse with qemu_irq_raise in ls7a_timer_cb function
to keep consistent with hardware behavior when raise irq.

Signed-off-by: Xiaojuan Yang 
---
 hw/rtc/ls7a_rtc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/rtc/ls7a_rtc.c b/hw/rtc/ls7a_rtc.c
index b88a90de8b..780144b9da 100644
--- a/hw/rtc/ls7a_rtc.c
+++ b/hw/rtc/ls7a_rtc.c
@@ -425,7 +425,7 @@ static void toy_timer_cb(void *opaque)
 LS7ARtcState *s = opaque;
 
 if (toy_enabled(s)) {
-qemu_irq_pulse(s->irq);
+qemu_irq_raise(s->irq);
 }
 }
 
@@ -434,7 +434,7 @@ static void rtc_timer_cb(void *opaque)
 LS7ARtcState *s = opaque;
 
 if (rtc_enabled(s)) {
-qemu_irq_pulse(s->irq);
+qemu_irq_raise(s->irq);
 }
 }
 
-- 
2.31.1

Re: venv for python qtest bits? (was: Re: [PATCH 11/12] acpi/tests/bits: add README file for bits qtests)

[Michael S. Tsirkin]

On Fri, Jul 01, 2022 at 01:20:30PM +0530, Ani Sinha wrote:
> On Fri, Jul 1, 2022 at 1:08 PM Michael S. Tsirkin  wrote:
> >
> > On Fri, Jul 01, 2022 at 12:58:33PM +0530, Ani Sinha wrote:
> > > On Fri, Jul 1, 2022 at 12:23 PM Michael S. Tsirkin  
> > > wrote:
> > > >
> > > > On Fri, Jul 01, 2022 at 06:12:14AM +0200, Thomas Huth wrote:
> > > > > I even wouldn't mind if you put your python stuff in a new directory 
> > > > > like
> > > > > tests/pytests/ for example, as long as it downloads your binaries 
> > > > > separately
> > > > > - as I wrote in another mail, the avocado framework rather looks like 
> > > > > an
> > > > > oddball in our test framework nowadays since it uses a separate test 
> > > > > runner
> > > > > and not the meson test harness, so having a new approach for 
> > > > > python-based
> > > > > tests is maybe even a good idea. I just really want to avoid that 
> > > > > this goes
> > > > > into tests/qtest (since it really does not belong there), and please 
> > > > > don't
> > > > > add more external stuff via git submodules, that's really the wrong 
> > > > > approach
> > > > > for this.
> > > >
> > > > I get it, people hate submodules with passion.  I think trying another
> > > > approach for testing that is neither avocado nor qtest is
> > > > not too bad. As long as this is not user visible, we can
> > > > allow ourselves space to experiment.
> > > >
> > > > OK so, how about this:
> > > > - put it in a new directory: tests/roms?
> > > > - create repo for a fork of biosbits under git.qemu.org
> > > > - roll our own analog to git submodules: a script
> > > >   that clones the repo
> > >
> > > No need to clone the whole repo. We can simply download the binaries
> > > that the girlab CI job would generate from the bits sources in that
> > > repo.
> > > We need to clone if we are always building bits from source for every
> > > test. That is not necessary IMHO since much of the bits package would
> > > remain as is without modification.
> >
> > IMHO CI job idea isn't great since isn't versioned at all, is it?
> 
> bits is versioned yes, in a crude way. every time you make a commit in
> the top level repo, the version would increment by one.

Is it easy to find out which source was this generated from?
And is there a promise to keep these around indefinitely?

> > Also as long as test passes, sure. But if it fails one will
> > need the sources to investigate.
> 
> sources might also be needed to write the tests.
> 
> >
> > Let's start with building things from source.
> 
> hmm. bitys uses old autotools, not ninja and takes about 10/15 mins to
> build depending on parallelity and build host.

Right. But whoever wants to use these just needs to do it once.


> Add an option
> > of prebuilt binaries as an optimization once things
> > stabilize.
> >
> >
> > > > - new target make check-roms,
> > >
> > > I think make pytest or some such is better and more generic if other
> > > such tests in other areas follow suit.
> >
> > The name is not critical in my mind, but I think we need to decide
> > what exactly differentiates it from other tests.
> >
> >
> > >
> > > if the clone exists locally -
> > > >   run the test, if not - skip it
> > >
> > > if download of the bits binaries fail, skip it.
> >
> > You seem to be recreating either git or avocado or both here.
> >
> > Personally I want something that works offline.
> >
> >
> >
> > > > - as for using pre-generates ISOs as an optimization,
> > > >   I'm not sure how important that is, if yes -
> > > >   we can add another repo and another make target along the
> > > >   same lines
> > > >
> > > >
> > > >
> > > > --
> > > > MST
> > > >
> >

Re: [PATCH v4 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:26, Richard Henderson
 wrote:
>
> This new behaviour is in the ARM pseudocode function
> AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32
> via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which
> the trap would be delivered is in AArch64 mode.
>
> Given that ARMv9 drops support for AArch32 outside EL0, the trap EL
> detection ought to be trivially true, but the pseudocode still contains
> a number of conditions, and QEMU has not yet committed to dropping A32
> support for EL[12] when v9 features are present.
>
> Since the computation of SME_TRAP_NONSTREAMING is necessarily different
> for the two modes, we might as well preserve bits within TBFLAG_ANY and
> allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead.
>
> Signed-off-by: Richard Henderson 

> +# These patterns are taken from Appendix E1.1 of DDI0616 A.a,
> +# Arm Architecture Reference Manual Supplement,
> +# The Scalable Matrix Extension (SME), for Armv9-A
> +
> +{
> +  [
> +OK  0-00 1110  0001 0010 11--     # SMOV W|Xd,Vn.B[0]
> +OK  0-00 1110  0010 0010 11--     # SMOV W|Xd,Vn.H[0]
> +OK  0100 1110  0100 0010 11--     # SMOV Xd,Vn.S[0]
> +OK   1110  0001 0011 11--     # UMOV Wd,Vn.B[0]
> +OK   1110  0010 0011 11--     # UMOV Wd,Vn.H[0]
> +OK   1110  0100 0011 11--     # UMOV Wd,Vn.S[0]
> +OK  0100 1110  1000 0011 11--     # UMOV Xd,Vn.D[0]
> +  ]
> +  FAIL  0--0 111-         # Advanced SIMD vector 
> operations
> +}
> +
> +{
> +  [
> +OK  0101 1110 --1-  11-1 11--     # FMULX/FRECPS/FRSQRTS 
> (scalar)
> +OK  0101 1110 -10-  00-1 11--     # FMULX/FRECPS/FRSQRTS 
> (scalar, FP16)
> +OK  01-1 1110 1-10 0001 11-1 10--     # FRECPE/FRSQRTE/FRECPX 
> (scalar)
> +OK  01-1 1110  1001 11-1 10--     # FRECPE/FRSQRTE/FRECPX 
> (scalar, FP16)
> +  ]
> +  FAIL  01-1 111-         # Advanced SIMD 
> single-element operations
> +}
> +
> +FAIL0-00 110-         # Advanced SIMD structure 
> load/store
> +FAIL1100 1110         # Advanced SIMD 
> cryptography extensions
> +
> +# These are the "avoidance of doubt" final table of Illegal Advanced SIMD 
> instructions
> +# We don't actually need to include these, as the default is OK.
> +#   -001 111-         # Scalar floating-point 
> operations
> +#   --10 110-         # Load/store pair of FP 
> registers
> +#   --01 1100         # Load FP register 
> (PC-relative literal)
> +#   --11 1100 --0-        # Load/store FP register 
> (unscaled imm)
> +#   --11 1100 --1-     --10   # Load/store FP register 
> (register offset)
> +#   --11 1101         # Load/store FP register 
> (scaled imm)

Don't we need a FAIL line for the "FJCVTZS should be illegal" case ?

> +FAIL 0100 --1-  1010      # ADR
> +FAIL 0100 --1-  1011 -0--     # FTSSEL, FEXPA
> +FAIL 0101 --10 0001 100-      # COMPACT
> +FAIL0010 0101 --01 100-  000- ---0    # RDFFR, RDFFRS
> +FAIL0010 0101 --10 1--- 1001      # WRFFR, SETFFR
> +FAIL0100 0101 --0-  1011      # BDEP, BEXT, BGRP
> +FAIL0100 0101 000-  0110 1---     # PMULLB, PMULLT (128b 
> result)
> +FAIL0110 0100 --1-  1110 01--     # FMMLA, BFMMLA
> +FAIL0110 0101 --0-   11--     # FTSMUL
> +FAIL0110 0101 --01 0--- 100-      # FTMAD
> +FAIL0110 0101 --01 1--- 001-      # FADDA
> +FAIL0100 0101 --0-  1001 10--     # SMMLA, UMMLA, USMMLA
> +FAIL0100 0101 --1-  1---      # SVE2 string/histo/crypto 
> instructions
> +FAIL1000 010- -00-  10--      # SVE2 32-bit gather NT 
> load (vector+scalar)
> +FAIL1000 010- -00-  111-      # SVE 32-bit gather 
> prefetch (vector+imm)
> +FAIL1000 0100 0-1-  0---      # SVE 32-bit gather 
> prefetch (scalar+vector)
> +FAIL1000 010- -01-  1---      # SVE 32-bit gather load 
> (vector+imm)
> +FAIL1000 0100 0-0-  0---      # SVE 32-bit gather load 
> byte (scalar+vector)
> +FAIL1000 0100 1---  0---      # SVE 32-bit gather load 
> half (scalar+vector)
> +FAIL1000 0101 0---  0---      # SVE 32-bit gather load 
> word (scalar+vector)
> +FAIL1010 010-   011-      # SVE contiguous FF load 
> (scalar+scalar)
> +FAIL1010 010- ---1  101-      # SVE contiguous NF load 
> (scalar+imm)
> +FAIL1010 010- -10-  000-      # SVE load & replicate 32 
> bytes (scalar+scalar)
> +FAIL 

Re: venv for python qtest bits? (was: Re: [PATCH 11/12] acpi/tests/bits: add README file for bits qtests)

[Ani Sinha]

On Fri, Jul 1, 2022 at 1:08 PM Michael S. Tsirkin  wrote:
>
> On Fri, Jul 01, 2022 at 12:58:33PM +0530, Ani Sinha wrote:
> > On Fri, Jul 1, 2022 at 12:23 PM Michael S. Tsirkin  wrote:
> > >
> > > On Fri, Jul 01, 2022 at 06:12:14AM +0200, Thomas Huth wrote:
> > > > I even wouldn't mind if you put your python stuff in a new directory 
> > > > like
> > > > tests/pytests/ for example, as long as it downloads your binaries 
> > > > separately
> > > > - as I wrote in another mail, the avocado framework rather looks like an
> > > > oddball in our test framework nowadays since it uses a separate test 
> > > > runner
> > > > and not the meson test harness, so having a new approach for 
> > > > python-based
> > > > tests is maybe even a good idea. I just really want to avoid that this 
> > > > goes
> > > > into tests/qtest (since it really does not belong there), and please 
> > > > don't
> > > > add more external stuff via git submodules, that's really the wrong 
> > > > approach
> > > > for this.
> > >
> > > I get it, people hate submodules with passion.  I think trying another
> > > approach for testing that is neither avocado nor qtest is
> > > not too bad. As long as this is not user visible, we can
> > > allow ourselves space to experiment.
> > >
> > > OK so, how about this:
> > > - put it in a new directory: tests/roms?
> > > - create repo for a fork of biosbits under git.qemu.org
> > > - roll our own analog to git submodules: a script
> > >   that clones the repo
> >
> > No need to clone the whole repo. We can simply download the binaries
> > that the girlab CI job would generate from the bits sources in that
> > repo.
> > We need to clone if we are always building bits from source for every
> > test. That is not necessary IMHO since much of the bits package would
> > remain as is without modification.
>
> IMHO CI job idea isn't great since isn't versioned at all, is it?

bits is versioned yes, in a crude way. every time you make a commit in
the top level repo, the version would increment by one.

> Also as long as test passes, sure. But if it fails one will
> need the sources to investigate.

sources might also be needed to write the tests.

>
> Let's start with building things from source.

hmm. bitys uses old autotools, not ninja and takes about 10/15 mins to
build depending on parallelity and build host.

Add an option
> of prebuilt binaries as an optimization once things
> stabilize.
>
>
> > > - new target make check-roms,
> >
> > I think make pytest or some such is better and more generic if other
> > such tests in other areas follow suit.
>
> The name is not critical in my mind, but I think we need to decide
> what exactly differentiates it from other tests.
>
>
> >
> > if the clone exists locally -
> > >   run the test, if not - skip it
> >
> > if download of the bits binaries fail, skip it.
>
> You seem to be recreating either git or avocado or both here.
>
> Personally I want something that works offline.
>
>
>
> > > - as for using pre-generates ISOs as an optimization,
> > >   I'm not sure how important that is, if yes -
> > >   we can add another repo and another make target along the
> > >   same lines
> > >
> > >
> > >
> > > --
> > > MST
> > >
>

Re: [PATCH v3 0/4] rSTify a few more docs; move them to QEMU Git

[Kashyap Chamarthy]

Ping.

Thomas/Peter: when you get some time, please have a look at this.

On Mon, Jun 06, 2022 at 06:55:47PM +0200, Kashyap Chamarthy wrote:
> On Mon, Jun 06, 2022 at 06:49:49PM +0200, Kashyap Chamarthy wrote:
> > Oops, messed up v3's cover-letter subject; now fixed.  Sorry.
> 
> Sigh, instead of "v3", I accidentally wrote "v4" in the cover-letter
> subject.  Now fix that too; sorry for the noise.
> 
> > On Mon, Jun 06, 2022 at 06:43:32PM +0200, Kashyap Chamarthy wrote:
> > > - Add back the "" fragment in security-process.rst
> > >   [Thomas]
> > > - Add a docs/about/contacting-the-project.rst as per Peter's feedback
> > >   here:
> > >   https://lists.nongnu.org/archive/html/qemu-devel/2022-03/msg05178.html
> > >   [pm215]
> > > - Keep Thomas' R-by for "docs: rSTify MailingLists wiki; move it to QEMU
> > >   Git"
> > > 
> > > v2 cover letter:
> > > ---
> > > rSTify a few more docs; move them to QEMU Git
> > > 
> > > This series rST-ifies:
> > > 
> > >   - security-process[1]
> > >   - MailingLists[2]
> > >   - GettingStartedDevelopers[3]
> > > 
> > > The 'security-process' page is from the QEMU web and is moved to
> > > docs/devel/ in QEMU Git.  This is based on Paolo's feedback here[4].
> > > The next two docs are converted from the Wiki.
> > > 
> > > [1] https://www.qemu.org/contribute/security-process
> > > [2] https://wiki.qemu.org/Contribute/MailingLists
> > > [3] https://wiki.qemu.org/Documentation/GettingStartedDevelopers
> > > [4] https://lists.nongnu.org/archive/html/qemu-devel/2021-11/msg04002.html
> > > ---
> > > 
> > > Kashyap Chamarthy (4):
> > >   docs: rSTify "security-process" page; move it to QEMU Git
> > >   docs: rSTify MailingLists wiki; move it to QEMU Git
> > >   docs: rSTify GettingStartedDevelopers wiki; move it to QEMU Git
> > >   Add a new doc "contacting-the-project.rst"
> > > 
> > >  docs/about/contacting-the-project.rst |  16 ++
> > >  docs/about/index.rst  |   1 +
> > >  docs/devel/getting-started-developers.rst | 200 ++
> > >  docs/devel/index.rst  |   3 +
> > >  docs/devel/mailing-lists.rst  |  51 ++
> > >  docs/devel/security-process.rst   | 190 
> > >  6 files changed, 461 insertions(+)
> > >  create mode 100644 docs/about/contacting-the-project.rst
> > >  create mode 100644 docs/devel/getting-started-developers.rst
> > >  create mode 100644 docs/devel/mailing-lists.rst
> > >  create mode 100644 docs/devel/security-process.rst
> > > 
> > > -- 
> > > 2.36.1
> > > 
> > 
> > -- 
> > /kashyap
> 
> -- 
> /kashyap
> 
> 

-- 
/kashyap

Re: [PATCH] gtk: Add show_tabs=on|off command line option.

[Gerd Hoffmann]

  Hi,

> But a bit more verbosity might be nice, too.  What about “Display the tab
> bar for switching between the various graphical interfaces (e.g. VGA and
> virtual console character devices) by default”?  (Note the imperative on
> “Display”, I think we generally use the imperative to document options.)

And 'tab bar' is more clear too I think.

take care,
  Gerd

Re: [PATCH v3 0/4] rSTify a few more docs; move them to QEMU Git

[Peter Maydell]

On Fri, 1 Jul 2022 at 09:53, Kashyap Chamarthy  wrote:
>
> Ping.
>
> Thomas/Peter: when you get some time, please have a look at this.

I reviewed the one patch that had neither already got an R-by
or some review comments.

thanks
-- PMM

Re: [PATCH v4 01/45] target/arm: Handle SME in aarch64_cpu_dump_state

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:25, Richard Henderson
 wrote:
>
> Dump SVCR, plus use the correct access check for Streaming Mode.
>
> Signed-off-by: Richard Henderson 
> ---

Reviewed-by: Peter Maydell 

Dumping the actual ZA storage seems like it would be more
annoying than useful :-)

thanks
-- PMM

Re: [PATCH v3] ui/cocoa: Take refresh rate into account

[Peter Maydell]

On Fri, 1 Jul 2022 at 11:11, Gerd Hoffmann  wrote:
>
> On Tue, Jun 21, 2022 at 09:51:38AM +0100, Peter Maydell wrote:
> > On Mon, 20 Jun 2022 at 21:29, Akihiko Odaki  wrote:
> > >
> > > Retreieve the refresh rate of the display and reflect it with
> > > dpy_set_ui_info() and update_displaychangelistener(), allowing the
> > > guest and DisplayChangeListener to consume the information.
> >
> > But why? What goes wrong if we don't bother to do this?
>
> Nothing goes wrong.  This provides a hint to the guest how often the
> display is updated, so the guest has the chance to adapt to that.
> When we run 30 Hz display updates on the host side it is pointless for
> the guest to update the screen at 60Hz frequency, the guest can spare
> some cpu cycles instead.
>
> [ this should be better explained in the commit message ]

Thanks for the explanation.

-- PMM

Re: venv for python qtest bits? (was: Re: [PATCH 11/12] acpi/tests/bits: add README file for bits qtests)

[Ani Sinha]

On Fri, Jul 1, 2022 at 3:12 PM Michael S. Tsirkin  wrote:
>
> On Fri, Jul 01, 2022 at 01:20:30PM +0530, Ani Sinha wrote:
> > On Fri, Jul 1, 2022 at 1:08 PM Michael S. Tsirkin  wrote:
> > >
> > > On Fri, Jul 01, 2022 at 12:58:33PM +0530, Ani Sinha wrote:
> > > > On Fri, Jul 1, 2022 at 12:23 PM Michael S. Tsirkin  
> > > > wrote:
> > > > >
> > > > > On Fri, Jul 01, 2022 at 06:12:14AM +0200, Thomas Huth wrote:
> > > > > > I even wouldn't mind if you put your python stuff in a new 
> > > > > > directory like
> > > > > > tests/pytests/ for example, as long as it downloads your binaries 
> > > > > > separately
> > > > > > - as I wrote in another mail, the avocado framework rather looks 
> > > > > > like an
> > > > > > oddball in our test framework nowadays since it uses a separate 
> > > > > > test runner
> > > > > > and not the meson test harness, so having a new approach for 
> > > > > > python-based
> > > > > > tests is maybe even a good idea. I just really want to avoid that 
> > > > > > this goes
> > > > > > into tests/qtest (since it really does not belong there), and 
> > > > > > please don't
> > > > > > add more external stuff via git submodules, that's really the wrong 
> > > > > > approach
> > > > > > for this.
> > > > >
> > > > > I get it, people hate submodules with passion.  I think trying another
> > > > > approach for testing that is neither avocado nor qtest is
> > > > > not too bad. As long as this is not user visible, we can
> > > > > allow ourselves space to experiment.
> > > > >
> > > > > OK so, how about this:
> > > > > - put it in a new directory: tests/roms?
> > > > > - create repo for a fork of biosbits under git.qemu.org
> > > > > - roll our own analog to git submodules: a script
> > > > >   that clones the repo
> > > >
> > > > No need to clone the whole repo. We can simply download the binaries
> > > > that the girlab CI job would generate from the bits sources in that
> > > > repo.
> > > > We need to clone if we are always building bits from source for every
> > > > test. That is not necessary IMHO since much of the bits package would
> > > > remain as is without modification.
> > >
> > > IMHO CI job idea isn't great since isn't versioned at all, is it?
> >
> > bits is versioned yes, in a crude way. every time you make a commit in
> > the top level repo, the version would increment by one.
>
> Is it easy to find out which source was this generated from?

yes because this is how the version number is generated:

expr 2000 + `git rev-list HEAD 2>/dev/null | wc -l`

That means we simply count the number of commits in the top level
directory. If we overwrote history by force pushing, then well yes all
bets are off.

> And is there a promise to keep these around indefinitely?

We do not need to maintain multiple versions of bits or increment the
version number every time we wrote a test. Typically new
commits/changes will be made if we wanted to fix a bug or upgrade
acpica or whatever. Test scripts are python based and can be pushed
into bits while generating a new iso for testing purposes.

>
> > > Also as long as test passes, sure. But if it fails one will
> > > need the sources to investigate.
> >
> > sources might also be needed to write the tests.
> >
> > >
> > > Let's start with building things from source.
> >
> > hmm. bitys uses old autotools, not ninja and takes about 10/15 mins to
> > build depending on parallelity and build host.
>
> Right. But whoever wants to use these just needs to do it once.

but I thought you were suggesting we built bits every time the test is run?

>
>
> > Add an option
> > > of prebuilt binaries as an optimization once things
> > > stabilize.
> > >
> > >
> > > > > - new target make check-roms,
> > > >
> > > > I think make pytest or some such is better and more generic if other
> > > > such tests in other areas follow suit.
> > >
> > > The name is not critical in my mind, but I think we need to decide
> > > what exactly differentiates it from other tests.
> > >
> > >
> > > >
> > > > if the clone exists locally -
> > > > >   run the test, if not - skip it
> > > >
> > > > if download of the bits binaries fail, skip it.
> > >
> > > You seem to be recreating either git or avocado or both here.
> > >
> > > Personally I want something that works offline.
> > >
> > >
> > >
> > > > > - as for using pre-generates ISOs as an optimization,
> > > > >   I'm not sure how important that is, if yes -
> > > > >   we can add another repo and another make target along the
> > > > >   same lines
> > > > >
> > > > >
> > > > >
> > > > > --
> > > > > MST
> > > > >
> > >
>

Re: [PATCH v4 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:26, Richard Henderson
 wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson 

Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [PATCH 2/2] hw: m25p80: add tests for BP and TB bit write protect

[Cédric Le Goater]

On 6/27/22 20:52, Iris Chen wrote:

Signed-off-by: Iris Chen 


Palmettos are getting old (2014). We might want to change the machine
model to an ast2600 one.

Anyhow, these are very good tests for both m25p80 and aspeed-smc models.

Reviewed-by: Cédric Le Goater 

Thanks,

C.




---
  tests/qtest/aspeed_smc-test.c | 111 ++
  1 file changed, 111 insertions(+)

diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index 1258687eac..05ce941566 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -192,6 +192,24 @@ static void read_page_mem(uint32_t addr, uint32_t *page)
  }
  }
  
+static void write_page_mem(uint32_t addr, uint32_t write_value)

+{
+spi_ctrl_setmode(CTRL_WRITEMODE, PP);
+
+for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+writel(ASPEED_FLASH_BASE + addr + i * 4, write_value);
+}
+}
+
+static void assert_page_mem(uint32_t addr, uint32_t expected_value)
+{
+uint32_t page[FLASH_PAGE_SIZE / 4];
+read_page_mem(addr, page);
+for (int i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
+g_assert_cmphex(page[i], ==, expected_value);
+}
+}
+
  static void test_erase_sector(void)
  {
  uint32_t some_page_addr = 0x600 * FLASH_PAGE_SIZE;
@@ -501,6 +519,95 @@ static void test_status_reg_write_protection(void)
  flash_reset();
  }
  
+static void test_write_block_protect(void)

+{
+uint32_t sector_size = 65536;
+uint32_t n_sectors = 512;
+
+spi_ce_ctrl(1 << CRTL_EXTENDED0);
+spi_conf(CONF_ENABLE_W0);
+
+uint32_t bp_bits = 0b0;
+
+for (int i = 0; i < 16; i++) {
+bp_bits = ((i & 0b1000) << 3) | ((i & 0b0111) << 2);
+
+spi_ctrl_start_user();
+writeb(ASPEED_FLASH_BASE, WREN);
+writeb(ASPEED_FLASH_BASE, BULK_ERASE);
+writeb(ASPEED_FLASH_BASE, WREN);
+writeb(ASPEED_FLASH_BASE, WRSR);
+writeb(ASPEED_FLASH_BASE, bp_bits);
+writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
+writeb(ASPEED_FLASH_BASE, WREN);
+spi_ctrl_stop_user();
+
+uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
+uint32_t protection_start = n_sectors - num_protected_sectors;
+uint32_t protection_end = n_sectors;
+
+for (int sector = 0; sector < n_sectors; sector++) {
+uint32_t addr = sector * sector_size;
+
+assert_page_mem(addr, 0x);
+write_page_mem(addr, make_be32(0xabcdef12));
+
+uint32_t expected_value = protection_start <= sector
+  && sector < protection_end
+  ? 0x : 0xabcdef12;
+
+assert_page_mem(addr, expected_value);
+}
+}
+
+flash_reset();
+}
+
+static void test_write_block_protect_bottom_bit(void)
+{
+uint32_t sector_size = 65536;
+uint32_t n_sectors = 512;
+
+spi_ce_ctrl(1 << CRTL_EXTENDED0);
+spi_conf(CONF_ENABLE_W0);
+
+/* top bottom bit is enabled */
+uint32_t bp_bits = 0b00100 << 3;
+
+for (int i = 0; i < 16; i++) {
+bp_bits = (((i & 0b1000) | 0b0100) << 3) | ((i & 0b0111) << 2);
+
+spi_ctrl_start_user();
+writeb(ASPEED_FLASH_BASE, WREN);
+writeb(ASPEED_FLASH_BASE, BULK_ERASE);
+writeb(ASPEED_FLASH_BASE, WREN);
+writeb(ASPEED_FLASH_BASE, WRSR);
+writeb(ASPEED_FLASH_BASE, bp_bits);
+writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
+writeb(ASPEED_FLASH_BASE, WREN);
+spi_ctrl_stop_user();
+
+uint32_t num_protected_sectors = i ? MIN(1 << (i - 1), n_sectors) : 0;
+uint32_t protection_start = 0;
+uint32_t protection_end = num_protected_sectors;
+
+for (int sector = 0; sector < n_sectors; sector++) {
+uint32_t addr = sector * sector_size;
+
+assert_page_mem(addr, 0x);
+write_page_mem(addr, make_be32(0xabcdef12));
+
+uint32_t expected_value = protection_start <= sector
+  && sector < protection_end
+  ? 0x : 0xabcdef12;
+
+assert_page_mem(addr, expected_value);
+}
+}
+
+flash_reset();
+}
+
  static char tmp_path[] = "/tmp/qtest.m25p80.XX";
  
  int main(int argc, char **argv)

@@ -529,6 +636,10 @@ int main(int argc, char **argv)
  qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg);
  qtest_add_func("/ast2400/smc/status_reg_write_protection",
 test_status_reg_write_protection);
+qtest_add_func("/ast2400/smc/write_block_protect",
+   test_write_block_protect);
+qtest_add_func("/ast2400/smc/write_block_protect_bottom_bit",
+   test_write_block_protect_bottom_bit);
  
  flash_reset();

  ret = g_test_run();

Re: venv for python qtest bits? (was: Re: [PATCH 11/12] acpi/tests/bits: add README file for bits qtests)

[Michael S. Tsirkin]

On Fri, Jul 01, 2022 at 06:12:14AM +0200, Thomas Huth wrote:
> I even wouldn't mind if you put your python stuff in a new directory like
> tests/pytests/ for example, as long as it downloads your binaries separately
> - as I wrote in another mail, the avocado framework rather looks like an
> oddball in our test framework nowadays since it uses a separate test runner
> and not the meson test harness, so having a new approach for python-based
> tests is maybe even a good idea. I just really want to avoid that this goes
> into tests/qtest (since it really does not belong there), and please don't
> add more external stuff via git submodules, that's really the wrong approach
> for this.

I get it, people hate submodules with passion.  I think trying another
approach for testing that is neither avocado nor qtest is
not too bad. As long as this is not user visible, we can
allow ourselves space to experiment.

OK so, how about this:
- put it in a new directory: tests/roms?
- create repo for a fork of biosbits under git.qemu.org
- roll our own analog to git submodules: a script
  that clones the repo
- new target make check-roms, if the clone exists locally -
  run the test, if not - skip it
- as for using pre-generates ISOs as an optimization,
  I'm not sure how important that is, if yes -
  we can add another repo and another make target along the
  same lines



-- 
MST

Re: [PATCH v2 09/13] hw/i2c/pmbus: Add read-only IC_DEVICE_ID support

[Cédric Le Goater]

 > Thanks for the new device. It helps me see where to expand on PMBus.

Thanks for adding the whole pmbus infrastructure! It’s really useful.
And thanks for the review.

Off-topic, but I’ve been meaning to reach out to you guys (Google
engineers working on QEMU for OpenBMC) about your Nuvoton NPCM845R
series, my team is interested in using it. I was just curious about
the status of it and if there’s any features missing and what plans
you have for the future, maybe we can collaborate.


Peter, feel free to reach out to me, or Titus, and we can sync up.  I used to 
work with Patrick who's now at Fb on OpenBMC stuff.  We sent a bunch of the 
Nuvoton patches up for review recently, and we're actively adding more devices, 
etc.

We also have quite a few patches downstream we're looking to upstream, 
including PECI, and sensors, etc, etc that we've seen on BMC servers.


So a simple PECI model is now merged. Sensors are always welcome,
it's nice to have properties to change values. On my wish-list
are PCIe and a working USB gadget network device.

Thanks,

C.

RE: [RFC PATCH 00/12] Introduce QEMU userspace ebpf support

[Zhang, Chen]

> -Original Message-
> From: Andrew Melnichenko 
> Sent: Wednesday, June 29, 2022 6:43 PM
> To: Zhang, Chen 
> Cc: Jason Wang ; qemu-dev  de...@nongnu.org>; Paolo Bonzini ; Daniel P.
> Berrangé ; Eduardo Habkost
> ; Eric Blake ; Markus
> Armbruster ; Peter Maydell
> ; Thomas Huth ; Laurent
> Vivier ; Yuri Benditovich
> 
> Subject: Re: [RFC PATCH 00/12] Introduce QEMU userspace ebpf support
> 
> Hi all,
> Nice idea.
> It would be great if future patches would add the BPF map support(if uBPF
> allows it).

The BPF map support is very useful.  But current uBPF project don't support 
this yet.
According to the previous discussion with Thomas and Daniel, we should avoid
Introduce new git submodule for QEMU. And related general discussion:
Why we should avoid new submodules if possible:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg897339.html

I think for the future development, we have to submit patch to the uBPF project.

Thanks
Chen

> 
> On Fri, Jun 17, 2022 at 10:51 AM Zhang Chen  wrote:
> >
> > Hi All,
> >
> > The goal of this series is to bring the power of ebpf to QEMU.
> > It makes QEMU have the ability to extend the capabilities without
> > requiring changing source code. Just need to load the eBPF binary file
> > even at VM runtime. And already have some userspace ebpf
> > implementation like: Intel DPDK eBPF, windows eBPF, etc..
> > The original idea suggested by Jason Wang.
> >
> > eBPF is a revolutionary technology with origins in the Linux
> > kernel that can run sandboxed programs in an operating system kernel.
> > It is used to safely and efficiently extend the capabilities of the
> > kernel without requiring to change kernel source code or load kernel
> > modules.(from https://ebpf.io/)
> >
> > KVM already got benefits from it, but QEMU did not. Hence we want
> > to bring the power of eBPF to QEMU. It can load binary eBPF program
> > even when VM running. At the same time, add some hooks in QEMU as
> the
> > user space eBPF load point. Do the things on different layers.
> >
> >That’s the advantages of kernel eBPF. Most of the functions can be
> > implemented in QEMU. This series just a start of the Power of
> Programmability.
> >
> > 1). Safety:
> >
> > Building on the foundation of seeing and understanding all system
> > calls and combining that with a packet and socket-level view of all
> > networking operations allows for revolutionary new approaches to
> > securing systems.
> >
> > 2). Tracing & Profiling:
> >
> > The ability to attach eBPF programs to trace points as well as kernel
> > and user application probe points allows unprecedented visibility into
> > the runtime behavior of applications and the system itself.
> >
> > 3). Networking:
> >
> > The combination of programmability and efficiency makes eBPF a natural
> > fit for all packet processing requirements of networking solutions.
> >
> > 4). Observability & Monitoring:
> >
> > Instead of relying on static counters and gauges exposed by the
> > perating system, eBPF enables the collection & in-kernel aggregation
> > of custom metrics and generation of visibility events based on a wide
> > range of possible sources.
> >
> > QEMU userspace ebpf design based on ubpf project
> (https://github.com/iovisor/ubpf).
> > The most mature userspace ebpf implementation. This project officially
> > support by iovisor(Like BCC and bpftrace). This project includes an
> > eBPF assembler, disassembler, interpreter (for all platforms), and JIT
> > compiler (for x86-64 and Arm64 targets). Qemu userspace ebpf make the
> > ubpf project as the git submodule.
> >
> > Current implementation support load ebpf program and run it in
> > net/filter-ubpf module, this filter can support any user defined rules
> > to hanle network packet. At the same time, it's easy for other
> > developers to use the ubpf infrastructue in QEMU's other modules from
> > the function in /ebpf/ubpf.c, and it support JIT.
> >
> > For the uBPF License is Apache License 2.0, It's OK to compatible
> > with QEMU’s GPLv2 LICENSE same as mason.
> >
> > TODO: Need to add more comments and test-case for ubpf, current
> > implementation not include ebpf verifier. But I think maybe it's not a
> > big problem, current ebpf load/unload API exposed by QMP command.
> > Qemu is a userspace program, if someone want to hack QEMU, no need to
> > load a malicious ubpf program, it can hack QEMU code or crash QEMU on
> > host directly(different from kernel ebpf needs strict inspection, but
> > yes, it still need basic check).
> >
> > Any comments are welcome.
> >
> > Thanks
> > Chen
> >
> >
> > Zhang Chen (12):
> >   configure: Add iovisor/ubpf project as a submodule for QEMU
> >   meson: Add ubpf build config and misc
> >   ebpf/uBPF: Introduce userspace ebpf data structure
> >   ebpf/uBPF: Introduce ubpf initialize functions
> >   ebpf/uBPF: Add qemu_prepare_ubpf to load ebpf binary

Re: [PATCH v1 2/2] migration/multifd: Warn user when zerocopy not working

[Leonardo Brás]

On Tue, 2022-06-28 at 17:56 +0100, Dr. David Alan Gilbert wrote:
> * Leonardo Bras Soares Passos (leob...@redhat.com) wrote:
> > On Tue, Jun 28, 2022 at 10:52 AM Dr. David Alan Gilbert
> >  wrote:
> > > 
> > > * Daniel P. Berrangé (berra...@redhat.com) wrote:
> > > > On Tue, Jun 28, 2022 at 09:32:04AM -0300, Leonardo Bras Soares Passos
> > > > wrote:
> > > > > On Tue, Jun 28, 2022 at 4:53 AM Daniel P. Berrangé
> > > > >  wrote:
> > > > > > 
> > > > > > On Mon, Jun 27, 2022 at 10:09:09PM -0300, Leonardo Bras wrote:
> > > > > > > Some errors, like the lack of Scatter-Gather support by the
> > > > > > > network
> > > > > > > interface(NETIF_F_SG) may cause sendmsg(...,MSG_ZEROCOPY) to fail
> > > > > > > on using
> > > > > > > zero-copy, which causes it to fall back to the default copying
> > > > > > > mechanism.
> > > > > > 
> > > > > > How common is this lack of SG support ? What NICs did you have that
> > > > > > were affected ?
> > > > > 
> > > > > I am not aware of any NIC without SG available for testing, nor have
> > > > > any idea on how common they are.
> > > > > But since we can detect sendmsg() falling back to copying we should
> > > > > warn the user if this ever happens.
> > > > > 
> > > > > There is also a case in IPv6 related to fragmentation that may cause
> > > > > MSG_ZEROCOPY to fall back to the copying mechanism, so it's also
> > > > > covered.
> > > > > 
> > > > > > 
> > > > > > > After each full dirty-bitmap scan there should be a zero-copy
> > > > > > > flush
> > > > > > > happening, which checks for errors each of the previous calls to
> > > > > > > sendmsg(...,MSG_ZEROCOPY). If all of them failed to use zero-copy,
> > > > > > > then
> > > > > > > warn the user about it.
> > > > > > > 
> > > > > > > Since it happens once each full dirty-bitmap scan, even in worst
> > > > > > > case
> > > > > > > scenario it should not print a lot of warnings, and will allow
> > > > > > > tracking
> > > > > > > how many dirty-bitmap iterations were not able to use zero-copy
> > > > > > > send.
> > > > > > 
> > > > > > For long running migrations which are not converging, or converging
> > > > > > very slowly there could be 100's of passes.
> > > > > > 
> > > > > 
> > > > > I could change it so it only warns once, if that is too much output.
> > > > 
> > > > Well I'm mostly wondering what we're expecting the user todo with this
> > > > information.
> > 
> > 
> > My rationale on that:
> > - zero-copy-send is a feature that is supposed to improve send
> > throughput by reducing cpu usage.
> > - there is a chance the sendmsg(MSG_ZEROCOPY) fails to use zero-copy
> > - if this happens, there will be a potential throughput decrease on
> > sendmsg()
> > - the user (or management app) need to know when zero-copy-send is
> > degrading throughput, so it can be disabled
> > - this is also important for performance testing, given it can be
> > confusing having zero-copy-send improving throughput in some cases,
> > and degrading in others, without any apparent reason why.
> > 
> > > > Generally a log file containing warnings ends up turning
> > > > into a bug report. If we think it is important for users and/or mgmt
> > > > apps to be aware of this info, then it might be better to actually
> > > > put a field in the query-migrate stats to report if zero-copy is
> > > > being honoured or not,
> > > 
> > > Yeh just a counter would work there I think.
> > 
> > The warning idea was totally due to my inexperience on this mgmt app
> > interface, since I had no other idea on how to deal with that.
> 
> Yeh it's not too silly an idea!
> The way some of these warning or stats get to us can be a bit random,
> but sometimes can confuse things.
> 
> > I think having it in query-migrate is a much better idea than a
> > warning, since it should be much easier to parse and disable
> > zero-copy-send if desired.
> > Even in my current qemu test script, it's much better having it in
> > query-migrate.
> > 
> > > 
> > > > and just have a trace point in this location
> > > > instead.
> > > 
> > > Yeh.
> > > 
> > 
> > Yeap, the counter idea seems great!
> > Will it be always printed there, or only when zero-copy-send is enabled?
> 
> You could make it either if it's enabled or if it's none zero.
> (I guess you want it to reset to 0 at the start of a new migration).
> 
> Dave

Thanks for this feedback!

I have everything already working, but I am struggling with a good property
name. 

I am currently using zero_copy_copied (or zero-copy-copied in json), but it does
not look like a good Migration stat name. 

Do you have any suggestion?

Best regards,
Leo


> 
> > 
> > Best regards,
> > Leo
> > 
> > > Dave
> > > 
> > > > With regards,
> > > > Daniel
> > > > --
> > > > > : https://berrange.com  -o-   
> > > > > https://www.flickr.com/photos/dberrange :|
> > > > > : https://libvirt.org -o-   
> > > > > https://fstop138.berrange.com :|
> > > > > : https://entangle-photo.org    -o-   
> > > > > 

Re: [PATCH 1/2] hw: m25p80: Add Block Protect and Top Bottom bits for write protect

[Cédric Le Goater]

Even for a simple addition a quick intro is always nice to have.

On 6/27/22 20:52, Iris Chen wrote:

Signed-off-by: Iris Chen 


Too bad that we are modeling 5 bits with 5 bools but given the layout
it makes the code easier to read. LGTM.

Reviewed-by: Cédric Le Goater 

Thanks,

C.




---
  hw/block/m25p80.c | 74 +++
  1 file changed, 62 insertions(+), 12 deletions(-)

diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 50b523e5b1..0156a70f5e 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -38,21 +38,19 @@
  #include "trace.h"
  #include "qom/object.h"
  
-/* Fields for FlashPartInfo->flags */

-
-/* erase capabilities */
-#define ER_4K 1
-#define ER_32K 2
-/* set to allow the page program command to write 0s back to 1. Useful for
- * modelling EEPROM with SPI flash command set
- */
-#define EEPROM 0x100
-
  /* 16 MiB max in 3 byte address mode */
  #define MAX_3BYTES_SIZE 0x100
-
  #define SPI_NOR_MAX_ID_LEN 6
  
+/* Fields for FlashPartInfo->flags */

+enum spi_nor_option_flags {
+ER_4K  = BIT(0),
+ER_32K = BIT(1),
+EEPROM = BIT(2),
+SNOR_F_HAS_SR_TB   = BIT(3),
+SNOR_F_HAS_SR_BP3_BIT6 = BIT(4),
+};
+
  typedef struct FlashPartInfo {
  const char *part_name;
  /*
@@ -253,7 +251,8 @@ static const FlashPartInfo known_devices[] = {
  { INFO("n25q512a11",  0x20bb20,  0,  64 << 10, 1024, ER_4K) },
  { INFO("n25q512a13",  0x20ba20,  0,  64 << 10, 1024, ER_4K) },
  { INFO("n25q128", 0x20ba18,  0,  64 << 10, 256, 0) },
-{ INFO("n25q256a",0x20ba19,  0,  64 << 10, 512, ER_4K) },
+{ INFO("n25q256a",0x20ba19,  0,  64 << 10, 512,
+   ER_4K | SNOR_F_HAS_SR_BP3_BIT6 | SNOR_F_HAS_SR_TB) },
  { INFO("n25q512a",0x20ba20,  0,  64 << 10, 1024, ER_4K) },
  { INFO("n25q512ax3",  0x20ba20,  0x1000,  64 << 10, 1024, ER_4K) },
  { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) },
@@ -480,6 +479,11 @@ struct Flash {
  bool reset_enable;
  bool quad_enable;
  bool aai_enable;
+bool block_protect0;
+bool block_protect1;
+bool block_protect2;
+bool block_protect3;
+bool top_bottom_bit;
  bool status_register_write_disabled;
  uint8_t ear;
  
@@ -630,6 +634,29 @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data)

  qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write protect!\n");
  return;
  }
+uint32_t block_protect_value = (s->block_protect3 << 3) |
+   (s->block_protect2 << 2) |
+   (s->block_protect1 << 1) |
+   (s->block_protect0 << 0);
+
+ uint32_t num_protected_sectors = 1 << (block_protect_value - 1);
+ uint32_t sector = addr / s->pi->sector_size;
+
+ /* top_bottom_bit == 0 means TOP */
+if (!s->top_bottom_bit) {
+if (block_protect_value > 0 &&
+s->pi->n_sectors <= sector + num_protected_sectors) {
+qemu_log_mask(LOG_GUEST_ERROR,
+  "M25P80: write with write protect!\n");
+return;
+}
+} else {
+if (block_protect_value > 0 && sector < num_protected_sectors) {
+qemu_log_mask(LOG_GUEST_ERROR,
+  "M25P80: write with write protect!\n");
+return;
+}
+}
  
  if ((prev ^ data) & data) {

  trace_m25p80_programming_zero_to_one(s, addr, prev, data);
@@ -728,6 +755,15 @@ static void complete_collecting_data(Flash *s)
  break;
  case WRSR:
  s->status_register_write_disabled = extract32(s->data[0], 7, 1);
+s->block_protect0 = extract32(s->data[0], 2, 1);
+s->block_protect1 = extract32(s->data[0], 3, 1);
+s->block_protect2 = extract32(s->data[0], 4, 1);
+if (s->pi->flags & SNOR_F_HAS_SR_TB) {
+s->top_bottom_bit = extract32(s->data[0], 5, 1);
+}
+if (s->pi->flags & SNOR_F_HAS_SR_BP3_BIT6) {
+s->block_protect3 = extract32(s->data[0], 6, 1);
+}
  
  switch (get_man(s)) {

  case MAN_SPANSION:
@@ -1213,6 +1249,15 @@ static void decode_new_cmd(Flash *s, uint32_t value)
  case RDSR:
  s->data[0] = (!!s->write_enable) << 1;
  s->data[0] |= (!!s->status_register_write_disabled) << 7;
+s->data[0] |= (!!s->block_protect0) << 2;
+s->data[0] |= (!!s->block_protect1) << 3;
+s->data[0] |= (!!s->block_protect2) << 4;
+if (s->pi->flags & SNOR_F_HAS_SR_TB) {
+s->data[0] |= (!!s->top_bottom_bit) << 5;
+}
+if (s->pi->flags & SNOR_F_HAS_SR_BP3_BIT6) {
+s->data[0] |= (!!s->block_protect3) << 6;
+}
  
  if (get_man(s) == MAN_MACRONIX || get_man(s) == MAN_ISSI) {

  s->data[0] |= (!!s->quad_enable) << 6;
@@ -1553,6 +1598,11 @@ static void 

Re: [PATCH 1/2] hw: m25p80: Add Block Protect and Top Bottom bits for write protect

[Francisco Iglesias]

Hi Iris,

Looks good, a couple of minor comments below!

On [2022 Jun 27] Mon 11:52:33, Iris Chen wrote:
> Signed-off-by: Iris Chen 
> ---
>  hw/block/m25p80.c | 74 +++
>  1 file changed, 62 insertions(+), 12 deletions(-)
> 
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index 50b523e5b1..0156a70f5e 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -38,21 +38,19 @@
>  #include "trace.h"
>  #include "qom/object.h"
>  
> -/* Fields for FlashPartInfo->flags */
> -
> -/* erase capabilities */
> -#define ER_4K 1
> -#define ER_32K 2
> -/* set to allow the page program command to write 0s back to 1. Useful for
> - * modelling EEPROM with SPI flash command set
> - */
> -#define EEPROM 0x100
> -
>  /* 16 MiB max in 3 byte address mode */
>  #define MAX_3BYTES_SIZE 0x100
> -
>  #define SPI_NOR_MAX_ID_LEN 6
>  
> +/* Fields for FlashPartInfo->flags */
> +enum spi_nor_option_flags {

(A suggestion is to s/nor/flash/ above (and s/SNOR_F_//  below) since there
looks to be nand flashes as W25N01GV using the protocol to).

> +ER_4K  = BIT(0),
> +ER_32K = BIT(1),
> +EEPROM = BIT(2),
> +SNOR_F_HAS_SR_TB   = BIT(3),
> +SNOR_F_HAS_SR_BP3_BIT6 = BIT(4),
> +};
> +
>  typedef struct FlashPartInfo {
>  const char *part_name;
>  /*
> @@ -253,7 +251,8 @@ static const FlashPartInfo known_devices[] = {
>  { INFO("n25q512a11",  0x20bb20,  0,  64 << 10, 1024, ER_4K) },
>  { INFO("n25q512a13",  0x20ba20,  0,  64 << 10, 1024, ER_4K) },
>  { INFO("n25q128", 0x20ba18,  0,  64 << 10, 256, 0) },
> -{ INFO("n25q256a",0x20ba19,  0,  64 << 10, 512, ER_4K) },
> +{ INFO("n25q256a",0x20ba19,  0,  64 << 10, 512,
> +   ER_4K | SNOR_F_HAS_SR_BP3_BIT6 | SNOR_F_HAS_SR_TB) },
>  { INFO("n25q512a",0x20ba20,  0,  64 << 10, 1024, ER_4K) },
>  { INFO("n25q512ax3",  0x20ba20,  0x1000,  64 << 10, 1024, ER_4K) },
>  { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | ER_32K) 
> },
> @@ -480,6 +479,11 @@ struct Flash {
>  bool reset_enable;
>  bool quad_enable;
>  bool aai_enable;
> +bool block_protect0;
> +bool block_protect1;
> +bool block_protect2;
> +bool block_protect3;
> +bool top_bottom_bit;
>  bool status_register_write_disabled;
>  uint8_t ear;
>  
> @@ -630,6 +634,29 @@ void flash_write8(Flash *s, uint32_t addr, uint8_t data)
>  qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write 
> protect!\n");
>  return;
>  }
> +uint32_t block_protect_value = (s->block_protect3 << 3) |
> +   (s->block_protect2 << 2) |
> +   (s->block_protect1 << 1) |
> +   (s->block_protect0 << 0);
> +
> + uint32_t num_protected_sectors = 1 << (block_protect_value - 1);
> + uint32_t sector = addr / s->pi->sector_size;
> +
> + /* top_bottom_bit == 0 means TOP */

Indentation needs minor fixing on above lines, also the declarations should
be at the top of the function.

> +if (!s->top_bottom_bit) {
> +if (block_protect_value > 0 &&
> +s->pi->n_sectors <= sector + num_protected_sectors) {
> +qemu_log_mask(LOG_GUEST_ERROR,
> +  "M25P80: write with write protect!\n");
> +return;
> +}
> +} else {
> +if (block_protect_value > 0 && sector < num_protected_sectors) {
> +qemu_log_mask(LOG_GUEST_ERROR,
> +  "M25P80: write with write protect!\n");
> +return;
> +}
> +}
>  
>  if ((prev ^ data) & data) {
>  trace_m25p80_programming_zero_to_one(s, addr, prev, data);
> @@ -728,6 +755,15 @@ static void complete_collecting_data(Flash *s)
>  break;
>  case WRSR:
>  s->status_register_write_disabled = extract32(s->data[0], 7, 1);
> +s->block_protect0 = extract32(s->data[0], 2, 1);
> +s->block_protect1 = extract32(s->data[0], 3, 1);
> +s->block_protect2 = extract32(s->data[0], 4, 1);
> +if (s->pi->flags & SNOR_F_HAS_SR_TB) {
> +s->top_bottom_bit = extract32(s->data[0], 5, 1);
> +}
> +if (s->pi->flags & SNOR_F_HAS_SR_BP3_BIT6) {
> +s->block_protect3 = extract32(s->data[0], 6, 1);
> +}
>  
>  switch (get_man(s)) {
>  case MAN_SPANSION:
> @@ -1213,6 +1249,15 @@ static void decode_new_cmd(Flash *s, uint32_t value)
>  case RDSR:
>  s->data[0] = (!!s->write_enable) << 1;
>  s->data[0] |= (!!s->status_register_write_disabled) << 7;
> +s->data[0] |= (!!s->block_protect0) << 2;
> +s->data[0] |= (!!s->block_protect1) << 3;
> +s->data[0] |= (!!s->block_protect2) << 4;
> +if (s->pi->flags & SNOR_F_HAS_SR_TB) {
> +s->data[0] |= (!!s->top_bottom_bit) << 5;
> +

Re: [PATCH v4 07/45] target/arm: Mark PMULL, FMMLA as non-streaming

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:28, Richard Henderson
 wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson 
> ---
>  target/arm/sme-fa64.decode |  2 --
>  target/arm/translate-sve.c | 18 ++
>  2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
> index c25bad5ee5..c75a94e0fc 100644
> --- a/target/arm/sme-fa64.decode
> +++ b/target/arm/sme-fa64.decode
> @@ -58,8 +58,6 @@ FAIL1100 1110         # 
> Advanced SIMD cryptography e
>  #   --11 1100 --1-     --10   # Load/store FP register 
> (register offset)
>  #   --11 1101         # Load/store FP register 
> (scaled imm)
>
> -FAIL0100 0101 000-  0110 1---     # PMULLB, PMULLT (128b 
> result)

This encoding pattern (as the comment says) covers only the esize = 128 case...

> -TRANS_FEAT(PMULLB, aa64_sve2, do_trans_pmull, a, false)
> -TRANS_FEAT(PMULLT, aa64_sve2, do_trans_pmull, a, true)
> +TRANS_FEAT_NONSTREAMING(PMULLB, aa64_sve2, do_trans_pmull, a, false)
> +TRANS_FEAT_NONSTREAMING(PMULLT, aa64_sve2, do_trans_pmull, a, true)

..but these trans functions cover all the esize values.

In the pseudocode for PMULLB/PMULLT it explicitly does
 if esize < 128 then CheckSVEEnabled(); else CheckNonStreamingSVEEnabled();
so it is definitely intended to distinguish the 128 bit case
from the 16 and 64 bit ones.

thanks
-- PMM

Re: [PATCH v4 08/45] target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:28, Richard Henderson
 wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson 

Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [PATCH v4 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:25, Richard Henderson
 wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson 

Reviewed-by: Peter Maydell 

thanks
-- PMM

API to change the vendor of IDE disk

[Alex]

Dear Qemu Genius




This is zaifeng (wzf_develo...@foxmail.com) (WeChat ID: QemuKVM).

Yes, I am a cloud engineer. (๑•̀ㅂ•́)و✧




MayIaskyousomequestionsaboutQemu?









Here is the problem:




If you use IDE disk on a Windows VM, "QEMU HARDDISK" could be found from device 
manager.




Some applications will refuse to boot on virtualized environment by detecting 
if the disk name contains "QEMU" string. I have no idea why, maybe they worried 
about copy-vm = copy-license?




I know for virtio-scsi disks, it's possible to change it by adding 

CA3A36F6@EA9D5647.C5ADBE62.png
Description: Binary data


2F5FFF0E@4BBF3414.C5ADBE62.png
Description: Binary data


6609D128@75F2655D.C5ADBE62.png
Description: Binary data

[PATCH 2/3] hw/i386/pc: Always place CXL Memory Regions after device_memory

[Jonathan Cameron via]

Previously broken_reserved_end was taken into account, but Igor Mammedov
identified that this could lead to a clash between potential RAM being
mapped in the region and CXL usage. Hence always add the size of the
device_memory memory region.  This only affects the case where the
broken_reserved_end flag was set.

Fixes: 6e4e3ae936e6 ("hw/cxl/component: Implement host bridge MMIO (8.2.5, 
table 142)")
Reported-by: Igor Mammedov 
Signed-off-by: Jonathan Cameron 
---
 hw/i386/pc.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 774cb2bf07..8d68295fda 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -922,10 +922,8 @@ void pc_memory_init(PCMachineState *pcms,
 hwaddr cxl_size = MiB;
 
 if (pcmc->has_reserved_memory && machine->device_memory->base) {
-cxl_base = machine->device_memory->base;
-if (!pcmc->broken_reserved_end) {
-cxl_base += memory_region_size(>device_memory->mr);
-}
+cxl_base = machine->device_memory->base
++ memory_region_size(>device_memory->mr);
 } else if (pcms->sgx_epc.size != 0) {
 cxl_base = sgx_epc_above_4g_end(>sgx_epc);
 } else {
-- 
2.32.0

[PATCH 1/3] hw/machine: Clear out left over CXL related pointer from move of state handling to machines.

[Jonathan Cameron via]

This got left behind in the move of the CXL setup code from core
files to the machines that support it.

Link: 
https://gitlab.com/qemu-project/qemu/-/commit/1ebf9001fb2701e3c00b401334c8f3900a46adaa
Signed-off-by: Jonathan Cameron 
---
 include/hw/boards.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/hw/boards.h b/include/hw/boards.h
index d94edcef28..7b416c9787 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -360,7 +360,6 @@ struct MachineState {
 CpuTopology smp;
 struct NVDIMMState *nvdimms_state;
 struct NumaState *numa_state;
-CXLFixedMemoryWindowOptionsList *cfmws_list;
 };
 
 #define DEFINE_MACHINE(namestr, machine_initfn) \
-- 
2.32.0

[PATCH 00/17] acpi:pc/q35: minor PCI refactoring/cleanups

[Igor Mammedov]

Flushing out ACPI PCI cleanups that preceed conversion of
DSDT PCI slots ennumeration to AcpiDevAmlIf interface.
It's is mostly collection of patches thraet removes code
duplication, we've accumulated around PCI relaterd AML
in DSDT.

git:
   https://gitlab.com/imammedo/qemu.git x86_pci_cleanups

Igor Mammedov (17):
  tests: acpi: whitelist pc/q35 DSDT due to HPET AML move
  acpi: x86: deduplicate HPET AML building
  tests: acpi: update expected blobs after HPET move
  tests: acpi: whitelist pc/q35 DSDT due to HPET AML move
  acpi: x86: refactor PDSM method to reduce nesting
  x86: acpi: _DSM: use Package to pass parameters
  tests: acpi: update expected blobs
  tests: acpi: whitelist pc/q35 DSDT before switching _DSM to use ASUN
  x86: acpi: cleanup PCI device _DSM duplication
  tests: acpi: update expected blobs
  tests: acpi: whitelist pc/q35 DSDT before moving _ADR field
  x86: pci: acpi: reorder Device's _ADR and _SUN fields
  tests: acpi: update expected blobs
  tests: acpi: whitelist pc/q35 DSDT before moving _ADR field
  x86: pci: acpi:  reorder Device's _DSM method
  tests: acpi: update expected blobs
  x86: pci: acpi: deduplate PCI slots creation

 hw/i386/acpi-build.c  | 302 ++
 tests/data/acpi/pc/DSDT   | Bin 5987 -> 6422 bytes
 tests/data/acpi/pc/DSDT.acpierst  | Bin 5954 -> 6382 bytes
 tests/data/acpi/pc/DSDT.acpihmat  | Bin 7312 -> 7747 bytes
 tests/data/acpi/pc/DSDT.bridge| Bin 8653 -> 9496 bytes
 tests/data/acpi/pc/DSDT.cphp  | Bin 6451 -> 6886 bytes
 tests/data/acpi/pc/DSDT.dimmpxm   | Bin 7641 -> 8076 bytes
 tests/data/acpi/pc/DSDT.hpbridge  | Bin 5954 -> 6382 bytes
 tests/data/acpi/pc/DSDT.hpbrroot  | Bin 3069 -> 3069 bytes
 tests/data/acpi/pc/DSDT.ipmikcs   | Bin 6059 -> 6494 bytes
 tests/data/acpi/pc/DSDT.memhp | Bin 7346 -> 7781 bytes
 tests/data/acpi/pc/DSDT.nohpet| Bin 5845 -> 6280 bytes
 tests/data/acpi/pc/DSDT.numamem   | Bin 5993 -> 6428 bytes
 tests/data/acpi/pc/DSDT.roothp| Bin 6195 -> 6656 bytes
 tests/data/acpi/q35/DSDT  | Bin 8274 -> 8320 bytes
 tests/data/acpi/q35/DSDT.acpierst | Bin 8291 -> 8337 bytes
 tests/data/acpi/q35/DSDT.acpihmat | Bin 9599 -> 9645 bytes
 tests/data/acpi/q35/DSDT.applesmc | Bin 8320 -> 8366 bytes
 tests/data/acpi/q35/DSDT.bridge   | Bin 10988 -> 11449 bytes
 tests/data/acpi/q35/DSDT.cphp | Bin 8738 -> 8784 bytes
 tests/data/acpi/q35/DSDT.cxl  | Bin 9600 -> 9646 bytes
 tests/data/acpi/q35/DSDT.dimmpxm  | Bin 9928 -> 9974 bytes
 tests/data/acpi/q35/DSDT.ipmibt   | Bin 8349 -> 8395 bytes
 tests/data/acpi/q35/DSDT.ipmismbus| Bin 8363 -> 8409 bytes
 tests/data/acpi/q35/DSDT.ivrs | Bin 8291 -> 8337 bytes
 tests/data/acpi/q35/DSDT.memhp| Bin 9633 -> 9679 bytes
 tests/data/acpi/q35/DSDT.mmio64   | Bin 9404 -> 9450 bytes
 tests/data/acpi/q35/DSDT.multi-bridge | Bin 8568 -> 8640 bytes
 tests/data/acpi/q35/DSDT.nohpet   | Bin 8132 -> 8178 bytes
 tests/data/acpi/q35/DSDT.numamem  | Bin 8280 -> 8326 bytes
 tests/data/acpi/q35/DSDT.pvpanic-isa  | Bin 8375 -> 8421 bytes
 tests/data/acpi/q35/DSDT.tis.tpm12| Bin 8880 -> 8926 bytes
 tests/data/acpi/q35/DSDT.tis.tpm2 | Bin 8906 -> 8952 bytes
 tests/data/acpi/q35/DSDT.viot | Bin 9383 -> 9429 bytes
 tests/data/acpi/q35/DSDT.xapic| Bin 35637 -> 35683 bytes
 35 files changed, 161 insertions(+), 141 deletions(-)

-- 
2.31.1

[PATCH 01/17] tests: acpi: whitelist pc/q35 DSDT due to HPET AML move

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h | 32 +
 1 file changed, 32 insertions(+)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..a7aa428fab 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,33 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/pc/DSDT",
+"tests/data/acpi/pc/DSDT.acpierst",
+"tests/data/acpi/pc/DSDT.acpihmat",
+"tests/data/acpi/pc/DSDT.bridge",
+"tests/data/acpi/pc/DSDT.cphp",
+"tests/data/acpi/pc/DSDT.dimmpxm",
+"tests/data/acpi/pc/DSDT.hpbridge",
+"tests/data/acpi/pc/DSDT.hpbrroot",
+"tests/data/acpi/pc/DSDT.ipmikcs",
+"tests/data/acpi/pc/DSDT.memhp",
+"tests/data/acpi/pc/DSDT.numamem",
+"tests/data/acpi/pc/DSDT.roothp",
+"tests/data/acpi/q35/DSDT",
+"tests/data/acpi/q35/DSDT.acpierst",
+"tests/data/acpi/q35/DSDT.acpihmat",
+"tests/data/acpi/q35/DSDT.applesmc",
+"tests/data/acpi/q35/DSDT.bridge",
+"tests/data/acpi/q35/DSDT.cphp",
+"tests/data/acpi/q35/DSDT.cxl",
+"tests/data/acpi/q35/DSDT.dimmpxm",
+"tests/data/acpi/q35/DSDT.ipmibt",
+"tests/data/acpi/q35/DSDT.ipmismbus",
+"tests/data/acpi/q35/DSDT.ivrs",
+"tests/data/acpi/q35/DSDT.memhp",
+"tests/data/acpi/q35/DSDT.mmio64",
+"tests/data/acpi/q35/DSDT.multi-bridge",
+"tests/data/acpi/q35/DSDT.numamem",
+"tests/data/acpi/q35/DSDT.pvpanic-isa",
+"tests/data/acpi/q35/DSDT.tis.tpm12",
+"tests/data/acpi/q35/DSDT.tis.tpm2",
+"tests/data/acpi/q35/DSDT.viot",
+"tests/data/acpi/q35/DSDT.xapic",
-- 
2.31.1

[PATCH 04/17] tests: acpi: whitelist pc/q35 DSDT due to HPET AML move

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h | 34 +
 1 file changed, 34 insertions(+)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..452145badd 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,35 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/pc/DSDT",
+"tests/data/acpi/pc/DSDT.acpierst",
+"tests/data/acpi/pc/DSDT.acpihmat",
+"tests/data/acpi/pc/DSDT.bridge",
+"tests/data/acpi/pc/DSDT.cphp",
+"tests/data/acpi/pc/DSDT.dimmpxm",
+"tests/data/acpi/pc/DSDT.hpbridge",
+"tests/data/acpi/pc/DSDT.hpbrroot",
+"tests/data/acpi/pc/DSDT.ipmikcs",
+"tests/data/acpi/pc/DSDT.memhp",
+"tests/data/acpi/pc/DSDT.numamem",
+"tests/data/acpi/pc/DSDT.roothp",
+"tests/data/acpi/q35/DSDT",
+"tests/data/acpi/q35/DSDT.acpierst",
+"tests/data/acpi/q35/DSDT.acpihmat",
+"tests/data/acpi/q35/DSDT.applesmc",
+"tests/data/acpi/q35/DSDT.bridge",
+"tests/data/acpi/q35/DSDT.cphp",
+"tests/data/acpi/q35/DSDT.cxl",
+"tests/data/acpi/q35/DSDT.dimmpxm",
+"tests/data/acpi/q35/DSDT.ipmibt",
+"tests/data/acpi/q35/DSDT.ipmismbus",
+"tests/data/acpi/q35/DSDT.ivrs",
+"tests/data/acpi/q35/DSDT.memhp",
+"tests/data/acpi/q35/DSDT.mmio64",
+"tests/data/acpi/q35/DSDT.multi-bridge",
+"tests/data/acpi/q35/DSDT.numamem",
+"tests/data/acpi/q35/DSDT.pvpanic-isa",
+"tests/data/acpi/q35/DSDT.tis.tpm12",
+"tests/data/acpi/q35/DSDT.tis.tpm2",
+"tests/data/acpi/q35/DSDT.viot",
+"tests/data/acpi/q35/DSDT.xapic",
+"tests/data/acpi/q35/DSDT.nohpet",
+"tests/data/acpi/pc/DSDT.nohpet",
-- 
2.31.1

[PATCH 06/17] x86: acpi: _DSM: use Package to pass parameters

[Igor Mammedov]

Numer of possible arguments to pass to a method is limited
in ACPI. The following patches will need to pass over more
parameters to PDSM method, will hit that limit.

Prepare for this by passing structure (Package) to method,
which let us workaround arguments limitation.
Pass to PDSM all standard arguments of _DSM as is, and
pack custom parameters into Package that is passed as
the last argument to PDSM.

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c | 40 +++-
 1 file changed, 27 insertions(+), 13 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index fe676b4831..8700446f50 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -431,11 +431,17 @@ static void build_append_pci_bus_devices(Aml 
*parent_scope, PCIBus *bus,
 );
 aml_append(dev, method);
 method = aml_method("_DSM", 4, AML_SERIALIZED);
-aml_append(method,
-aml_return(aml_call6("PDSM", aml_arg(0), aml_arg(1),
- aml_arg(2), aml_arg(3),
- aml_name("BSEL"), aml_name("_SUN")))
-);
+{
+Aml *params = aml_local(0);
+Aml *pkg = aml_package(2);
+aml_append(pkg, aml_name("BSEL"));
+aml_append(pkg, aml_name("_SUN"));
+aml_append(method, aml_store(pkg, params));
+aml_append(method,
+aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
+ aml_arg(2), aml_arg(3), params))
+);
+}
 aml_append(dev, method);
 aml_append(parent_scope, dev);
 
@@ -480,10 +486,17 @@ static void build_append_pci_bus_devices(Aml 
*parent_scope, PCIBus *bus,
  */
 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
 method = aml_method("_DSM", 4, AML_SERIALIZED);
-aml_append(method, aml_return(
-aml_call6("PDSM", aml_arg(0), aml_arg(1), aml_arg(2),
-  aml_arg(3), aml_name("BSEL"), aml_name("ASUN"))
-));
+{
+Aml *params = aml_local(0);
+Aml *pkg = aml_package(2);
+aml_append(pkg, aml_name("BSEL"));
+aml_append(pkg, aml_name("ASUN"));
+aml_append(method, aml_store(pkg, params));
+aml_append(method, aml_return(
+aml_call5("PDSM", aml_arg(0), aml_arg(1), aml_arg(2),
+  aml_arg(3), params)
+));
+}
 aml_append(dev, method);
 }
 
@@ -580,12 +593,13 @@ Aml *aml_pci_device_dsm(void)
 Aml *acpi_index = aml_local(2);
 Aml *zero = aml_int(0);
 Aml *one = aml_int(1);
-Aml *bnum = aml_arg(4);
 Aml *func = aml_arg(2);
 Aml *rev = aml_arg(1);
-Aml *sunum = aml_arg(5);
+Aml *params = aml_arg(4);
+Aml *bnum = aml_derefof(aml_index(params, aml_int(0)));
+Aml *sunum = aml_derefof(aml_index(params, aml_int(1)));
 
-method = aml_method("PDSM", 6, AML_SERIALIZED);
+method = aml_method("PDSM", 5, AML_SERIALIZED);
 
 /* get supported functions */
 ifctx = aml_if(aml_equal(func, zero));
@@ -662,10 +676,10 @@ Aml *aml_pci_device_dsm(void)
 * update acpi-index to actual value
 */
aml_append(ifctx, aml_store(acpi_index, aml_index(ret, zero)));
+   aml_append(ifctx, aml_return(ret));
 }
 
 aml_append(method, ifctx);
-aml_append(method, aml_return(ret));
 return method;
 }
 
-- 
2.31.1

[PATCH RESEND 03/11] target/ppc: Move slbie to decodetree

[Lucas Coutinho]

Reviewed-by: Leandro Lupori 
Signed-off-by: Lucas Coutinho 
---
 target/ppc/helper.h  |  2 +-
 target/ppc/insn32.decode |  7 +++
 target/ppc/mmu-hash64.c  |  2 +-
 target/ppc/translate.c   | 13 -
 target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
 5 files changed, 23 insertions(+), 15 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5e663a0a50..b51b3d9f07 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -695,7 +695,7 @@ DEF_HELPER_2(load_slb_esid, tl, env, tl)
 DEF_HELPER_2(load_slb_vsid, tl, env, tl)
 DEF_HELPER_2(find_slb_vsid, tl, env, tl)
 DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
-DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
 DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
 #endif
 DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 2b985249b8..d282cf00c1 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -131,6 +131,9 @@
 _imm8 xt imm:uint8_t
 @X_imm8 .. . .. imm:8 .. .  _imm8 
xt=%x_xt
 
+_rb   rb
+@X_rb   .. . . rb:5 .. ._rb
+
 _uim5 xt uim:uint8_t
 @X_uim5 .. . . uim:5 .. .   _uim5 
xt=%x_xt
 
@@ -810,6 +813,10 @@ VMODUD  000100 . . . 11011001011@VX
 VMODSQ  000100 . . . 1111011@VX
 VMODUQ  000100 . . . 1101011@VX
 
+## SLB Management Instructions
+
+SLBIE   01 - - . 0110110010 -   @X_rb
+
 ## TLB Management Instructions
 
 _tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index da9fe99ff8..03f71a82ec 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -197,7 +197,7 @@ static void __helper_slbie(CPUPPCState *env, target_ulong 
addr,
 }
 }
 
-void helper_slbie(CPUPPCState *env, target_ulong addr)
+void helper_SLBIE(CPUPPCState *env, target_ulong addr)
 {
 __helper_slbie(env, addr, false);
 }
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 275cffb2a7..14881e637f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5466,18 +5466,6 @@ static void gen_slbia(DisasContext *ctx)
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
-/* slbie */
-static void gen_slbie(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
 /* slbieg */
 static void gen_slbieg(DisasContext *ctx)
 {
@@ -6910,7 +6898,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, 
PPC_MEM_TLBIA),
 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
 #if defined(TARGET_PPC64)
 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
-GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
 GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
 #endif
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc 
b/target/ppc/translate/storage-ctrl-impl.c.inc
index f9e4a807f2..41fc5ade8b 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -21,6 +21,20 @@
  * Store Control Instructions
  */
 
+static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SLBI);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIE(cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
 static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
 {
 #if defined(CONFIG_USER_ONLY)
-- 
2.25.1

[PATCH 13/17] tests: acpi: update expected blobs

[Igor Mammedov]

Expected change:
  -Name (_SUN, 0x0X)  // _SUN: Slot User Number
   Name (_ADR, 0xY)  // _ADR: Address
  ...
  +Name (_SUN, 0xX)  // _SUN: Slot User Number

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h |  14 --
 tests/data/acpi/pc/DSDT | Bin 6422 -> 6422 bytes
 tests/data/acpi/pc/DSDT.acpierst| Bin 6382 -> 6382 bytes
 tests/data/acpi/pc/DSDT.acpihmat| Bin 7747 -> 7747 bytes
 tests/data/acpi/pc/DSDT.bridge  | Bin 9496 -> 9496 bytes
 tests/data/acpi/pc/DSDT.cphp| Bin 6886 -> 6886 bytes
 tests/data/acpi/pc/DSDT.dimmpxm | Bin 8076 -> 8076 bytes
 tests/data/acpi/pc/DSDT.hpbridge| Bin 6382 -> 6382 bytes
 tests/data/acpi/pc/DSDT.ipmikcs | Bin 6494 -> 6494 bytes
 tests/data/acpi/pc/DSDT.memhp   | Bin 7781 -> 7781 bytes
 tests/data/acpi/pc/DSDT.nohpet  | Bin 6280 -> 6280 bytes
 tests/data/acpi/pc/DSDT.numamem | Bin 6428 -> 6428 bytes
 tests/data/acpi/pc/DSDT.roothp  | Bin 6656 -> 6656 bytes
 tests/data/acpi/q35/DSDT.bridge | Bin 11449 -> 11449 bytes
 tests/data/acpi/q35/DSDT.multi-bridge   | Bin 8640 -> 8640 bytes
 15 files changed, 14 deletions(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index 1983fa596b..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,15 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/pc/DSDT",
-"tests/data/acpi/pc/DSDT.acpierst",
-"tests/data/acpi/pc/DSDT.acpihmat",
-"tests/data/acpi/pc/DSDT.bridge",
-"tests/data/acpi/pc/DSDT.cphp",
-"tests/data/acpi/pc/DSDT.dimmpxm",
-"tests/data/acpi/pc/DSDT.hpbridge",
-"tests/data/acpi/pc/DSDT.ipmikcs",
-"tests/data/acpi/pc/DSDT.memhp",
-"tests/data/acpi/pc/DSDT.nohpet",
-"tests/data/acpi/pc/DSDT.numamem",
-"tests/data/acpi/pc/DSDT.roothp",
-"tests/data/acpi/q35/DSDT.bridge",
-"tests/data/acpi/q35/DSDT.multi-bridge",
diff --git a/tests/data/acpi/pc/DSDT b/tests/data/acpi/pc/DSDT
index 
8282d449ceaefd914b419f507a13f3fb7b318aaf..fd79a602a2aaac0f7d91d2ee2b1af8f2e6cdd4b3
 100644
GIT binary patch
delta 758
zcmYk(y-LGi6vpvN(>6`>{pO=-zHY!lJG6Ch2v8>4a26a~osMjK@aXy9keFc02_4YHa_A2
zaX?=ZhloQeJpJYfaYQ!~O+=GEB#sfsrU)F-qtah5MvUoKVuF~^ex%<_5mUOCI7OV~}8RCp?CFY1Zea8AX
s6^I3%9$m+WG}Z)FNyw56})1vy8W5#Yk19GZ~XB6IQ`lC1Mb_IlmGw#

delta 758
zcmYMxJ5Iw;5QX7EaT3R|uOHWsIDTz_0#YQQps)m#6d-D|0VHZ93R)`ANU2!@h#rX=
zi5{^TlIuC5{Xd^#d^d~D;x$)UdwF&44D7Bwxp0XFWOpX;gIei>E#f=X1||*>
zhs0lqBg7GL>C2a6#4+&=qK#-1e;`f}C|h8OzDArPPKn=wwm-u~bma_pd@
zuH_C7?umOl=cmx>_X@7WmD#Vb_u;;{Z+wma6u<-Vpm*#;cqkqkKf*qON8(ZM*lV~J
z*Zi#ipD6~%#E)A3UV@kq|01S{De-T6ouh{ocR5o_-&_vY={I2TZ@n-NFdfOfd=T}HWG;jXn+P-!Init3CMF#
ze7FCnGt$hQHmA+;F^GnK|K!bP#?0!UUmhHThM+*LUIx(NFma}&|DhVc}W
ze?eKlBc3vRJnqtkb2ocA`|X1DeJM)nTeVRzVXr}JI7%kFC5%HD%}>>j)9eYnr=
zYv0K}fCucs=xQhX5FXN3JUw587|}YJVvHEmo5Tb$p-+h^VoF^)%@v}eSBXo+C4ETD
z5HpI^^iMfr@4e61-xJ{MyEeD{Zk1q*-O3O%f5nF>=nDbQw^`#Ywh>4Z{Q7k
e!!G+4-m>$nU%mfk#^pcHH={rR

delta 772
zcmXxhyG;W@6ougnT6^E`@xFImfD!xo+4(!R%-)5&;;!D`VDG^_anJazobSVZabNom`v4w@2gb1v;h}h_
zeUE(vkHn+d)gJp89ut41@_Y$mLcGZ=8)Al-5q~1)h)%UmHU;#b5K;)?hK
zu|O<{QzidYB9?NGQs46q_pIQRcr`o!Dfy=wUW?ayf55(hH{y+Pyi*Hr#ar$7*mv+w
fyfcn{5AVf$?MLhf_#i!ER;cI(CbKs2L3

diff --git a/tests/data/acpi/pc/DSDT.acpihmat b/tests/data/acpi/pc/DSDT.acpihmat
index 
33169838bed50710495d45e0d9486ac59b4e504c..973320cb25120818a45ddb3d8e3b3211f0c00adc
 100644
GIT binary patch
delta 760
zcmYMxy-LGS7{>8PlQvC1@^z9lP1;<79|frpkQ8we2gSL$o^!n+9$u1*Cnp;yq+
zMQ|3p0T<1ApPqLL{C{}}=VV)N>&<1Ht(%LRp=EU}x4FH$_B!rbKj>AR7AHq*7jDCC
zcAI@^+<`mnj`oG@yYMc1w{^9UeGlHFXVnDwsEg>*x5PeTpX$WC=^=XbC~<%|pihZI
z#33D~W;+S@6v%e=F(dTpc`kYHSX8;e_gVt%2+53G657|S#Ka+g~kJux2
zxu+N*(xKsurX|KvKj>92Dp5UWGRx2xk)dh?i1c_`=YuHMz#t0-;m?r)rd-8PrEF42JORtJ7lXT|ApYil>)hPcuD
zTHJ)2;->Z$_7>a{w>noV?1%6n@r!DF{i8ObP5gs6LL3p-v3%(uI>b+iW5hA>7ov;k
z5-$^(PY@@>kBC#mDe*pO`gigWJ-Nfvcdl`#5BJ6W>}{XT#P;(^|uV;{mp@vwKi
zQv{F1Bkc|L3a-Re@7TxiSUlFg!9IZ};z{RfgMA85iQhAMz8T_-_zy8d%!sdZ`7%e$
uiC+;5#De%2u|zD1FAAB@5$D9uhzrC8@pmErQ-xT`9o7FGCm#>x=g|R&$ew!u

diff --git a/tests/data/acpi/pc/DSDT.bridge b/tests/data/acpi/pc/DSDT.bridge
index 
407066e1ac46922751969b823000e4fdfa542662..9583da4e4f558cb0bf6912733fbe8db7c1ad255f
 100644
GIT binary patch
delta 1438
zcmeIyOG?8~6vpu+O`9}*B~6>8P1;zT3T;t*fQX@v3OcX|?I}o}8
zHy}f*q5I2_2TiE3$CwlvXsI)|PUJ(qU6tLZkLuA}R8)lQa}2j=OG
zu>dSkFHC%l8$d%m-pIawi(k(~H$^wo{t)TQ@gj0jZtMtlP1J)>Z<+u>4MP#I`qO=2iEDQE5}`+O9!#U2CzZ5j7?yZ
zz8F2AN5eI_ZXf82efinCN4&5AJrF%eJJ~(C?-qJX^cFpNfA`%+ZquVDUpWMZ^vxIn
yBii@n$qukXH;i3imp|U_9>!huZSmt?pv_dtcqf>~HV??;`bsz4>VUUHt`{a3nzh

delta 1438
zcmeIwOG?8~6vpwBG;Pz{SJJde+N6!esn8b12Z$KzsGtLj;H+D41L9l|A7@gWxdWjq
za0BARks!{+J=i4Y!zDQBq?F(Pp5$`Kd@`RrpV#bodUitQEIvA2{wDwV-rfw4jp=ZA
zW+qWfV}(e|4rt2*+remI0Ne+Z3iyo6kmTw3NG2h$2!5ntPKxiYX!`~j>0

[PATCH RESEND 10/11] target/ppc: Move slbsync to decodetree

[Lucas Coutinho]

Reviewed-by: Leandro Lupori 
Signed-off-by: Lucas Coutinho 
---
 target/ppc/insn32.decode |  2 ++
 target/ppc/translate.c   | 17 -
 target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
 3 files changed, 16 insertions(+), 17 deletions(-)

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index a28d31e123..fb53bce0c8 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -830,6 +830,8 @@ SLBMFEE 01 . - . 1110010011 -   
@X_tb
 
 SLBFEE  01 . - . 010011 1   @X_tb
 
+SLBSYNC 01 - - - 0101010010 -
+
 ## TLB Management Instructions
 
 _tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 150318d70e..a918575fa9 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5388,20 +5388,6 @@ static void gen_tlbsync(DisasContext *ctx)
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
-#if defined(TARGET_PPC64)
-/* slbsync */
-static void gen_slbsync(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-gen_check_tlb_flush(ctx, true);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-#endif  /* defined(TARGET_PPC64) */
-
 /***  External control ***/
 /* Optional: */
 
@@ -6803,9 +6789,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, 
PPC_MEM_TLBIA),
  * different ISA versions
  */
 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
-#if defined(TARGET_PPC64)
-GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
-#endif
 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x0001, PPC_EXTERN),
 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc 
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 260bce35ac..c90cad10b4 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -139,6 +139,20 @@ static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
 return true;
 }
 
+static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_check_tlb_flush(ctx, true);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
 static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
 {
 #if defined(CONFIG_USER_ONLY)
-- 
2.25.1

Re: [PATCH] qga: add command 'guest-get-cpustats'

[Marc-André Lureau]

Hi

On Fri, Jul 1, 2022 at 7:11 AM zhenwei pi  wrote:

> A vCPU thread always reaches 100% utilization when:
> - guest uses idle=poll
> - disable HLT vm-exit
> - enable MWAIT
>
> Add new guest agent command 'guest-get-cpustats' to get guest CPU
> statistics, we can know the guest workload and how busy the CPU is.
>
> Signed-off-by: zhenwei pi 
> ---
>  qga/commands-posix.c | 72 
>  qga/commands-win32.c |  6 
>  qga/qapi-schema.json | 49 ++
>  3 files changed, 127 insertions(+)
>
> diff --git a/qga/commands-posix.c b/qga/commands-posix.c
> index 0469dc409d..2847023876 100644
> --- a/qga/commands-posix.c
> +++ b/qga/commands-posix.c
> @@ -2893,6 +2893,73 @@ GuestDiskStatsInfoList
> *qmp_guest_get_diskstats(Error **errp)
>  return guest_get_diskstats(errp);
>  }
>
> +GuestCpuStatsList *qmp_guest_get_cpustats(Error **errp)
> +{
> +GuestCpuStatsList *head = NULL, **tail = 
> +const char *cpustats = "/proc/stat";
> +FILE *fp;
> +size_t n;
> +char *line = NULL;
> +
> +fp = fopen(cpustats, "r");
> +if (fp  == NULL) {
> +error_setg_errno(errp, errno, "open(\"%s\")", cpustats);
> +return NULL;
> +}
> +
> +while (getline(, , fp) != -1) {
> +GuestCpuStats *cpustat = NULL;
> +int i;
> +unsigned long user, system, idle, iowait, irq, softirq, steal,
> guest;
> +unsigned long nice, guest_nice;
> +char name[64];
> +
> +i = sscanf(line, "%s %lu %lu %lu %lu %lu %lu %lu %lu %lu %lu",
> +   name, , , , , , ,
> ,
> +   , , _nice);
> +
> +/* drop "cpu 1 2 3 ...", get "cpuX 1 2 3 ..." only */
> +if (strncmp(name, "cpu", 3) || (name[3] == '\0')) {
>

For extra safety, check !name as well


> +continue;
> +}
> +
>

if i < 5, I guess you should warn and continue


> +cpustat = g_new0(GuestCpuStats, 1);
> +cpustat->cpu = atoi([3]);
> +cpustat->has_user = true;
> +cpustat->user = user * 10;
>

proc(5) says that the value is given "in units of USER_HZ (1/100ths of a
second on most architectures, use sysconf(_SC_CLK_TCK) to obtain the right
value)", so we should adjust this code if we want to return correctly in ms.


> +cpustat->has_system = true;
> +cpustat->system = system * 10;
> +cpustat->has_idle = true;
> +cpustat->idle = idle * 10;
> +
> +/* Linux version >= 2.6 */
>

That's pretty old now (2003), not sure anyone would care about that
comment, but np ;)


> +if (i > 5) {
> +cpustat->has_iowait = true;
> +cpustat->iowait = iowait * 10;
> +cpustat->has_irq = true;
> +cpustat->irq = irq * 10;
> +cpustat->has_softirq = true;
> +cpustat->softirq = softirq * 10;
> +}
> +
> +if (i > 8) {
> +cpustat->has_steal = true;
> +cpustat->steal = steal * 10;
> +}
> +
> +if (i > 9) {
> +cpustat->has_guest = true;
> +cpustat->guest = guest * 10;
> +}
> +
> +QAPI_LIST_APPEND(tail, cpustat);
> +}
> +
> +free(line);
> +fclose(fp);
> +return head;
> +}
> +
>  #else /* defined(__linux__) */
>
>  void qmp_guest_suspend_disk(Error **errp)
> @@ -3247,6 +3314,11 @@ GuestDiskStatsInfoList
> *qmp_guest_get_diskstats(Error **errp)
>  return NULL;
>  }
>
> +GuestCpuStatsList *qmp_guest_get_cpustats(Error **errp)
> +{
> +error_setg(errp, QERR_UNSUPPORTED);
> +return NULL;
> +}
>
>  #endif /* CONFIG_FSFREEZE */
>
> diff --git a/qga/commands-win32.c b/qga/commands-win32.c
> index 36f94c0f9c..7ed7664715 100644
> --- a/qga/commands-win32.c
> +++ b/qga/commands-win32.c
> @@ -2543,3 +2543,9 @@ GuestDiskStatsInfoList
> *qmp_guest_get_diskstats(Error **errp)
>  error_setg(errp, QERR_UNSUPPORTED);
>  return NULL;
>  }
> +
> +GuestCpuStatsList *qmp_guest_get_cpustats(Error **errp)
> +{
> +error_setg(errp, QERR_UNSUPPORTED);
> +return NULL;
> +}
> diff --git a/qga/qapi-schema.json b/qga/qapi-schema.json
> index 9fa20e791b..4859c887b2 100644
> --- a/qga/qapi-schema.json
> +++ b/qga/qapi-schema.json
> @@ -1576,3 +1576,52 @@
>  { 'command': 'guest-get-diskstats',
>'returns': ['GuestDiskStatsInfo']
>  }
> +
> +##
> +# @GuestCpuStats:
> +#
> +# Get statistics of each CPU in millisecond.
> +#
> +# @cpu: CPU index in guest OS
> +#
> +# @user: CPU time of user mode
>

"Time spent in user mode." is more understandable (from man proc(5))

Same for the other descriptions.

+#
> +# @system: CPU time of system mode
> +#
> +# @idle: CPU time of idle state
> +#
> +# @iowait: CPU time waiting IO
> +#
> +# @irq: CPU time of hardware interrupt
> +#
> +# @softirq: CPU time of soft interrupt
> +#
> +# @steal: CPU time stolen by host
> +#
> +# @guest: CPU time of running guest mode
>

Why not "guest_nice" ?

Do we expect this struct to be equally meaningful 

Re: [PATCH 03/12] pc-bios/s390-ccw/bootmap: Improve the guessing logic in zipl_load_vblk()

[Eric Farman]

On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> The logic of trying an final ISO or ECKD boot on virtio-block devices
> is
> very weird: Since the geometry hardly ever matches in
> virtio_disk_is_scsi(),
> virtio_blk_setup_device() always sets a "guessed" disk geometry via
> virtio_assume_scsi() (which is certainly also wrong in a lot of
> cases).
> 
> zipl_load_vblk() then sees that there's been a
> "virtio_guessed_disk_nature"
> and tries to fix up the geometry again via virtio_assume_iso9660()
> before
> always trying to do ipl_iso_el_torito(). That's a very brain-twisting
> way of attempting to boot from ISO images, which won't work anymore
> after
> the following patches that will clean up the virtio_assume_scsi()
> mess
> (and thus get rid of the "virtio_guessed_disk_nature" here).
> 
> Let's try a better approach instead: ISO files always have a magic
> string "CD001" at offset 0x8001 (see e.g. the ECMA-119 specification)
> which we can use to decide whether we should try to boot in ISO 9660
> mode (which we should also try if we see a sector size of 2048).
> 
> And if we were not able to boot in ISO mode here, the final boot
> attempt
> before panicking is to boot in ECKD mode. Since this is our last boot
> attempt anyway, simply always assume the ECKD geometry here (if the
> sector
> size was not 4096 yet), so that we also do not depend on the guessed
> disk
> geometry from virtio_blk_setup_device() here anymore.
> 
> Signed-off-by: Thomas Huth 
> ---
>  pc-bios/s390-ccw/bootmap.c | 25 +
>  1 file changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/pc-bios/s390-ccw/bootmap.c b/pc-bios/s390-ccw/bootmap.c
> index 56411ab3b6..3181b05382 100644
> --- a/pc-bios/s390-ccw/bootmap.c
> +++ b/pc-bios/s390-ccw/bootmap.c
> @@ -780,18 +780,35 @@ static void ipl_iso_el_torito(void)
>  }
>  }
>  
> +/**
> + * Detect whether we're trying to boot from an .ISO image.
> + * These always have a signature string "CD001" at offset 0x8001.
> + */
> +static bool has_iso_signature(void)
> +{
> +if (virtio_read(0x8000 / virtio_get_block_size(), sec)) {

Certainly unlikely, but virtio_get_block_size is able to return zero.

> +return false;
> +}
> +
> +return !memcmp("CD001", [1], 5);
> +}
> +
>  /***
> 
>   * Bus specific IPL sequences
>   */
>  
>  static void zipl_load_vblk(void)
>  {
> -if (virtio_guessed_disk_nature()) {
> -virtio_assume_iso9660();
> +int blksize = virtio_get_block_size();
> +
> +if (blksize == VIRTIO_ISO_BLOCK_SIZE || has_iso_signature()) {
> +if (blksize != VIRTIO_ISO_BLOCK_SIZE) {
> +virtio_assume_iso9660();
> +}
> +ipl_iso_el_torito();
>  }
> -ipl_iso_el_torito();
>  
> -if (virtio_guessed_disk_nature()) {
> +if (blksize != VIRTIO_DASD_BLOCK_SIZE) {
>  sclp_print("Using guessed DASD geometry.\n");
>  virtio_assume_eckd();
>  }

Re: [PATCH v4 16/45] target/arm: Handle SME in sve_access_check

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:39, Richard Henderson
 wrote:
>
> The pseudocode for CheckSVEEnabled gains a check for Streaming
> SVE mode, and for SME present but SVE absent.
>
> Signed-off-by: Richard Henderson 
> ---
>  target/arm/translate-a64.c | 22 --
>  1 file changed, 16 insertions(+), 6 deletions(-)

Reviewed-by: Peter Maydell 

thanks
-- PMM

[PATCH 09/17] x86: acpi: cleanup PCI device _DSM duplication

[Igor Mammedov]

add ASUN variable to hotpluggable slots and use it
instead of _SUN which has the same value to reuse
_DMS code on both branches (hot- and non-hotpluggable).
No functional change.

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c | 56 +---
 1 file changed, 27 insertions(+), 29 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 8700446f50..36fe43c52f 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -374,6 +374,25 @@ build_facs(GArray *table_data)
 g_array_append_vals(table_data, reserved, 40); /* Reserved */
 }
 
+Aml *aml_pci_device_dsm(void)
+{
+Aml *method;
+
+method = aml_method("_DSM", 4, AML_SERIALIZED);
+{
+Aml *params = aml_local(0);
+Aml *pkg = aml_package(2);
+aml_append(pkg, aml_name("BSEL"));
+aml_append(pkg, aml_name("ASUN"));
+aml_append(method, aml_store(pkg, params));
+aml_append(method,
+aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
+ aml_arg(2), aml_arg(3), params))
+);
+}
+return method;
+}
+
 static void build_append_pcihp_notify_entry(Aml *method, int slot)
 {
 Aml *if_ctx;
@@ -423,26 +442,17 @@ static void build_append_pci_bus_devices(Aml 
*parent_scope, PCIBus *bus,
 break;
 }
 dev = aml_device("S%.02X", devfn);
-aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
+aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
+aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
 aml_append(method,
 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
 );
 aml_append(dev, method);
-method = aml_method("_DSM", 4, AML_SERIALIZED);
-{
-Aml *params = aml_local(0);
-Aml *pkg = aml_package(2);
-aml_append(pkg, aml_name("BSEL"));
-aml_append(pkg, aml_name("_SUN"));
-aml_append(method, aml_store(pkg, params));
-aml_append(method,
-aml_return(aml_call5("PDSM", aml_arg(0), aml_arg(1),
- aml_arg(2), aml_arg(3), params))
-);
-}
-aml_append(dev, method);
+
+aml_append(dev, aml_pci_device_dsm());
+
 aml_append(parent_scope, dev);
 
 build_append_pcihp_notify_entry(notify_method, slot);
@@ -485,19 +495,7 @@ static void build_append_pci_bus_devices(Aml 
*parent_scope, PCIBus *bus,
  * enumeration order in linux kernel, so use another variable for 
it
  */
 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
-method = aml_method("_DSM", 4, AML_SERIALIZED);
-{
-Aml *params = aml_local(0);
-Aml *pkg = aml_package(2);
-aml_append(pkg, aml_name("BSEL"));
-aml_append(pkg, aml_name("ASUN"));
-aml_append(method, aml_store(pkg, params));
-aml_append(method, aml_return(
-aml_call5("PDSM", aml_arg(0), aml_arg(1), aml_arg(2),
-  aml_arg(3), params)
-));
-}
-aml_append(dev, method);
+aml_append(dev, aml_pci_device_dsm());
 }
 
 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
@@ -585,7 +583,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, 
PCIBus *bus,
 qobject_unref(bsel);
 }
 
-Aml *aml_pci_device_dsm(void)
+static Aml *aml_pci_pdsm(void)
 {
 Aml *method, *UUID, *ifctx, *ifctx1;
 Aml *ret = aml_local(0);
@@ -1368,7 +1366,7 @@ static void build_x86_acpi_pci_hotplug(Aml *table, 
uint64_t pcihp_addr)
 aml_append(method, aml_return(aml_local(0)));
 aml_append(scope, method);
 
-aml_append(scope, aml_pci_device_dsm());
+aml_append(scope, aml_pci_pdsm());
 
 aml_append(table, scope);
 }
-- 
2.31.1

[PATCH RESEND 01/11] target/ppc: receive DisasContext explicitly in GEN_PRIV

[Lucas Coutinho]

From: Matheus Ferst 

GEN_PRIV and related CHK_* macros just assumed that variable named
"ctx" would be in scope when they are used, and that it would be a
pointer to DisasContext. Change these macros to receive the pointer
explicitly.


Reviewed-by: Leandro Lupori 
Signed-off-by: Matheus Ferst 
Signed-off-by: Lucas Coutinho 
---
 target/ppc/translate.c | 299 +++--
 target/ppc/translate/fp-impl.c.inc |   4 +-
 2 files changed, 154 insertions(+), 149 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4fcb311c2d..920bb543cf 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1267,38 +1267,43 @@ typedef struct opcode_t {
 const char *oname;
 } opcode_t;
 
+static void gen_priv_opc(DisasContext *ctx)
+{
+gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+}
+
 /* Helpers for priv. check */
-#define GEN_PRIV\
-do {\
-gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
+#define GEN_PRIV(CTX)  \
+do {   \
+gen_priv_opc(CTX); return; \
 } while (0)
 
 #if defined(CONFIG_USER_ONLY)
-#define CHK_HV GEN_PRIV
-#define CHK_SV GEN_PRIV
-#define CHK_HVRM GEN_PRIV
+#define CHK_HV(CTX) GEN_PRIV(CTX)
+#define CHK_SV(CTX) GEN_PRIV(CTX)
+#define CHK_HVRM(CTX) GEN_PRIV(CTX)
 #else
-#define CHK_HV  \
-do {\
-if (unlikely(ctx->pr || !ctx->hv)) {\
-GEN_PRIV;   \
-}   \
+#define CHK_HV(CTX) \
+do {\
+if (unlikely(ctx->pr || !ctx->hv)) {\
+GEN_PRIV(CTX);  \
+}   \
 } while (0)
-#define CHK_SV   \
+#define CHK_SV(CTX)  \
 do { \
 if (unlikely(ctx->pr)) { \
-GEN_PRIV;\
+GEN_PRIV(CTX);   \
 }\
 } while (0)
-#define CHK_HVRM\
-do {\
-if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
-GEN_PRIV;   \
-}   \
+#define CHK_HVRM(CTX)   \
+do {\
+if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
+GEN_PRIV(CTX);  \
+}   \
 } while (0)
 #endif
 
-#define CHK_NONE
+#define CHK_NONE(CTX)
 
 /*/
 /* PowerPC instructions table*/
@@ -3252,7 +3257,7 @@ GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))
 static void glue(gen_, name##x)(DisasContext *ctx)\
 { \
 TCGv EA;  \
-chk;  \
+chk(ctx); \
 gen_set_access_type(ctx, ACCESS_INT); \
 EA = tcg_temp_new();  \
 gen_addr_reg_index(ctx, EA);  \
@@ -3270,7 +3275,7 @@ static void glue(gen_, name##x)(DisasContext *ctx)
\
 static void glue(gen_, name##epx)(DisasContext *ctx)  \
 { \
 TCGv EA;  \
-CHK_SV;   \
+CHK_SV(ctx);  \
 gen_set_access_type(ctx, ACCESS_INT); \
 EA = tcg_temp_new();  \
 gen_addr_reg_index(ctx, EA);  \
@@ -3298,7 +3303,7 @@ GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
 static void glue(gen_, name##x)(DisasContext *ctx)\
 { \
 TCGv EA;  \
-chk; 

[PATCH RESEND 00/11] target/ppc: Implement slbiag move slb* to decodetree

[Lucas Coutinho]

Resent after rebasing and fixing conflicts with master.
Add Leandro Lupori as reviewer.

Based-on: <20220624191424.190471-1-leandro.lup...@eldorado.org.br>

Implement the following PowerISA v3.0 instuction:
slbiag: SLB Invalidate All Global X-form

Move the following PowerISA v3.0 instuction to decodetree:
slbie: SLB Invalidate Entry X-form
slbieg: SLB Invalidate Entry Global X-form
slbia: SLB Invalidate All X-form
slbmte: SLB Move To Entry X-form
slbmfev: SLB Move From Entry VSID X-form
slbmfee: SLB Move From Entry ESID X-form
slbfee: SLB Find Entry ESID
slbsync: SLB Synchronize

Lucas Coutinho (9):
  target/ppc: Move slbie to decodetree
  target/ppc: Move slbieg to decodetree
  target/ppc: Move slbia to decodetree
  target/ppc: Move slbmte to decodetree
  target/ppc: Move slbmfev to decodetree
  target/ppc: Move slbmfee to decodetree
  target/ppc: Move slbfee to decodetree
  target/ppc: Move slbsync to decodetree
  target/ppc: Implement slbiag

Matheus Ferst (2):
  target/ppc: receive DisasContext explicitly in GEN_PRIV
  target/ppc: add macros to check privilege level

 target/ppc/helper.h  |  15 +-
 target/ppc/insn32.decode |  26 ++
 target/ppc/mmu-hash64.c  |  41 +-
 target/ppc/translate.c   | 417 +++
 target/ppc/translate/fixedpoint-impl.c.inc   |   7 +-
 target/ppc/translate/fp-impl.c.inc   |   4 +-
 target/ppc/translate/storage-ctrl-impl.c.inc | 146 +++
 7 files changed, 377 insertions(+), 279 deletions(-)

-- 
2.25.1

[PATCH 15/17] x86: pci: acpi: reorder Device's _DSM method

[Igor Mammedov]

align _DSM method in empty slot descriptor with
a populated slot position.
Expected change:
  +Device (SE8)
  +{
  +Name (_ADR, 0x001D)  // _ADR: Address
  +Name (ASUN, 0x1D)
   Method (_DSM, 4, Serialized)  // _DSM: Device-Specific Method
   {
   Local0 = Package (0x02)
   {
   BSEL,
   ASUN
   }
   Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
   }
  -}

  -Device (SE8)
  -{
  -Name (_ADR, 0x001D)  // _ADR: Address
  -Name (ASUN, 0x1D)
   Name (_SUN, 0x1D)  // _SUN: Slot User Number
   Method (_EJ0, 1, NotSerialized)  // _EJx: Eject Device
   {
   PCEJ (BSEL, _SUN)
   }
  +}

i.e. put _DSM right after ASUN, with _SUN/_EJ0 following it.

that will eliminate contextual changes (causing test failures)
when follow up patches merge code generating populated and empty
slots descriptors.

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index fd7f3253e5..406bbac1c7 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -444,15 +444,13 @@ static void build_append_pci_bus_devices(Aml 
*parent_scope, PCIBus *bus,
 dev = aml_device("S%.02X", devfn);
 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
 aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
+aml_append(dev, aml_pci_device_dsm());
 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
 aml_append(method,
 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
 );
 aml_append(dev, method);
-
-aml_append(dev, aml_pci_device_dsm());
-
 aml_append(parent_scope, dev);
 
 build_append_pcihp_notify_entry(notify_method, slot);
-- 
2.31.1

[PATCH RESEND 07/11] target/ppc: Move slbmfev to decodetree

[Lucas Coutinho]

Reviewed-by: Leandro Lupori 
Signed-off-by: Lucas Coutinho 
---
 target/ppc/helper.h  |  2 +-
 target/ppc/insn32.decode |  2 ++
 target/ppc/mmu-hash64.c  |  2 +-
 target/ppc/translate.c   | 12 
 target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
 5 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ad88073ae0..1d23de7358 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -692,7 +692,7 @@ DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
 env, tl, tl, i32)
 DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
 DEF_HELPER_2(load_slb_esid, tl, env, tl)
-DEF_HELPER_2(load_slb_vsid, tl, env, tl)
+DEF_HELPER_2(SLBMFEV, tl, env, tl)
 DEF_HELPER_2(find_slb_vsid, tl, env, tl)
 DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
 DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e255f9241b..9354014ca5 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -825,6 +825,8 @@ SLBIA   01 --... - - 010010 -   
@X_ih
 
 SLBMTE  01 . - . 0110010010 -   @X_tb
 
+SLBMFEV 01 . - . 1101010011 -   @X_tb
+
 ## TLB Management Instructions
 
 _tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 1922960608..7854b91043 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -343,7 +343,7 @@ target_ulong helper_find_slb_vsid(CPUPPCState *env, 
target_ulong rb)
 return rt;
 }
 
-target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBMFEV(CPUPPCState *env, target_ulong rb)
 {
 PowerPCCPU *cpu = env_archcpu(env);
 target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d421fe267c..6b44c6312b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5363,17 +5363,6 @@ static void gen_slbmfee(DisasContext *ctx)
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
-static void gen_slbmfev(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
 
 static void gen_slbfee_(DisasContext *ctx)
 {
@@ -6845,7 +6834,6 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 
0x0010F801, PPC_SEGMENT_64B),
 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
  PPC_SEGMENT_64B),
 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, 
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, 
PPC_SEGMENT_64B),
 GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F, 
PPC_SEGMENT_64B),
 #endif
 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc 
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 4c2dd758b5..a037fc2b95 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -77,6 +77,20 @@ static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
 return true;
 }
 
+static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBMFEV(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
 static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
 {
 #if defined(CONFIG_USER_ONLY)
-- 
2.25.1

[PATCH RESEND 09/11] target/ppc: Move slbfee to decodetree

[Lucas Coutinho]

Reviewed-by: Leandro Lupori 
Signed-off-by: Lucas Coutinho 
---
 target/ppc/helper.h  |  2 +-
 target/ppc/insn32.decode |  2 ++
 target/ppc/mmu-hash64.c  |  2 +-
 target/ppc/translate.c   | 26 ---
 target/ppc/translate/storage-ctrl-impl.c.inc | 34 
 5 files changed, 38 insertions(+), 28 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 848665a4f4..649b2a9c58 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -693,7 +693,7 @@ DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
 DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
 DEF_HELPER_2(SLBMFEE, tl, env, tl)
 DEF_HELPER_2(SLBMFEV, tl, env, tl)
-DEF_HELPER_2(find_slb_vsid, tl, env, tl)
+DEF_HELPER_2(SLBFEE, tl, env, tl)
 DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
 DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
 DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 0797a19896..a28d31e123 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -828,6 +828,8 @@ SLBMTE  01 . - . 0110010010 -   
@X_tb
 SLBMFEV 01 . - . 1101010011 -   @X_tb
 SLBMFEE 01 . - . 1110010011 -   @X_tb
 
+SLBFEE  01 . - . 010011 1   @X_tb
+
 ## TLB Management Instructions
 
 _tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 5d73d64436..7ec7a67a78 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -331,7 +331,7 @@ target_ulong helper_SLBMFEE(CPUPPCState *env, target_ulong 
rb)
 return rt;
 }
 
-target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBFEE(CPUPPCState *env, target_ulong rb)
 {
 PowerPCCPU *cpu = env_archcpu(env);
 target_ulong rt = 0;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index eadf4ca1b7..150318d70e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5351,31 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
-
-static void gen_slbfee_(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
-#else
-TCGLabel *l1, *l2;
-
-if (unlikely(ctx->pr)) {
-gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
-return;
-}
-gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-l1 = gen_new_label();
-l2 = gen_new_label();
-tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
-tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
-tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
-tcg_gen_br(l2);
-gen_set_label(l1);
-tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
-gen_set_label(l2);
-#endif
-}
 #endif /* defined(TARGET_PPC64) */
 
 /***  Lookaside buffer management  ***/
@@ -6821,7 +6796,6 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 
0x001F0001,
 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
  PPC_SEGMENT_64B),
-GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F, 
PPC_SEGMENT_64B),
 #endif
 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
 /*
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc 
b/target/ppc/translate/storage-ctrl-impl.c.inc
index b169bd6317..260bce35ac 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -105,6 +105,40 @@ static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE 
*a)
 return true;
 }
 
+static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+
+#if defined(CONFIG_USER_ONLY)
+gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+#else
+
+#if defined(TARGET_PPC64)
+TCGLabel *l1, *l2;
+
+if (unlikely(ctx->pr)) {
+gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+return true;
+}
+gen_helper_SLBFEE(cpu_gpr[a->rt], cpu_env,
+ cpu_gpr[a->rb]);
+l1 = gen_new_label();
+l2 = gen_new_label();
+tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
+tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], -1, l1);
+tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
+tcg_gen_br(l2);
+gen_set_label(l1);
+tcg_gen_movi_tl(cpu_gpr[a->rt], 0);
+gen_set_label(l2);
+#else
+qemu_build_not_reached();
+#endif
+#endif
+return true;
+}
+
 static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
 {
 #if defined(CONFIG_USER_ONLY)
-- 
2.25.1

[PATCH RESEND 05/11] target/ppc: Move slbia to decodetree

[Lucas Coutinho]

Reviewed-by: Leandro Lupori 
Signed-off-by: Lucas Coutinho 
---
 target/ppc/helper.h  |  2 +-
 target/ppc/insn32.decode |  5 +
 target/ppc/mmu-hash64.c  |  2 +-
 target/ppc/translate.c   | 17 -
 target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
 5 files changed, 21 insertions(+), 19 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 8f9dde6d3f..c2440a8854 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -694,7 +694,7 @@ DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, 
tl, tl)
 DEF_HELPER_2(load_slb_esid, tl, env, tl)
 DEF_HELPER_2(load_slb_vsid, tl, env, tl)
 DEF_HELPER_2(find_slb_vsid, tl, env, tl)
-DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
 DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
 DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
 #endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d3517d412c..1349c5e8a7 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -131,6 +131,9 @@
 _imm8 xt imm:uint8_t
 @X_imm8 .. . .. imm:8 .. .  _imm8 
xt=%x_xt
 
+_ih   ih:uint8_t
+@X_ih   .. .. ih:3 . . .. . _ih
+
 _rb   rb
 @X_rb   .. . . rb:5 .. ._rb
 
@@ -818,6 +821,8 @@ VMODUQ  000100 . . . 1101011@VX
 SLBIE   01 - - . 0110110010 -   @X_rb
 SLBIEG  01 . - . 0111010010 -   @X_tb
 
+SLBIA   01 --... - - 010010 -   @X_ih
+
 ## TLB Management Instructions
 
 _tlbierb rs ric prs:bool r:bool
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a842fbd6f6..dd2c7e588f 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -101,7 +101,7 @@ void dump_slb(PowerPCCPU *cpu)
 }
 
 #ifdef CONFIG_TCG
-void helper_slbia(CPUPPCState *env, uint32_t ih)
+void helper_SLBIA(CPUPPCState *env, uint32_t ih)
 {
 PowerPCCPU *cpu = env_archcpu(env);
 int starting_entry;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ad19a68f5c..5d2416143f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5450,22 +5450,6 @@ static void gen_tlbsync(DisasContext *ctx)
 }
 
 #if defined(TARGET_PPC64)
-/* slbia */
-static void gen_slbia(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-uint32_t ih = (ctx->opcode >> 21) & 0x7;
-TCGv_i32 t0 = tcg_const_i32(ih);
-
-CHK_SV(ctx);
-
-gen_helper_slbia(cpu_env, t0);
-tcg_temp_free_i32(t0);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
 /* slbsync */
 static void gen_slbsync(DisasContext *ctx)
 {
@@ -6885,7 +6869,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, 
PPC_MEM_TLBIA),
  */
 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
 #if defined(TARGET_PPC64)
-GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
 #endif
 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc 
b/target/ppc/translate/storage-ctrl-impl.c.inc
index b9bb950f7d..cbb8b81f13 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -49,6 +49,20 @@ static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
 return true;
 }
 
+static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS(ctx, SLBI);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIA(cpu_env, tcg_constant_i32(a->ih));
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
 static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
 {
 #if defined(CONFIG_USER_ONLY)
-- 
2.25.1

Re: [PATCH] qga: add command 'guest-get-cpustats'

[Konstantin Kostiuk]

On Fri, Jul 1, 2022 at 4:53 PM Marc-André Lureau 
wrote:

> Hi
>
> On Fri, Jul 1, 2022 at 7:11 AM zhenwei pi  wrote:
>
>> A vCPU thread always reaches 100% utilization when:
>> - guest uses idle=poll
>> - disable HLT vm-exit
>> - enable MWAIT
>>
>> Add new guest agent command 'guest-get-cpustats' to get guest CPU
>> statistics, we can know the guest workload and how busy the CPU is.
>>
>> Signed-off-by: zhenwei pi 
>> ---
>>  qga/commands-posix.c | 72 
>>  qga/commands-win32.c |  6 
>>  qga/qapi-schema.json | 49 ++
>>  3 files changed, 127 insertions(+)
>>
>> diff --git a/qga/commands-posix.c b/qga/commands-posix.c
>> index 0469dc409d..2847023876 100644
>> --- a/qga/commands-posix.c
>> +++ b/qga/commands-posix.c
>> @@ -2893,6 +2893,73 @@ GuestDiskStatsInfoList
>> *qmp_guest_get_diskstats(Error **errp)
>>  return guest_get_diskstats(errp);
>>  }
>>
>> +GuestCpuStatsList *qmp_guest_get_cpustats(Error **errp)
>> +{
>> +GuestCpuStatsList *head = NULL, **tail = 
>> +const char *cpustats = "/proc/stat";
>> +FILE *fp;
>> +size_t n;
>> +char *line = NULL;
>> +
>> +fp = fopen(cpustats, "r");
>> +if (fp  == NULL) {
>> +error_setg_errno(errp, errno, "open(\"%s\")", cpustats);
>> +return NULL;
>> +}
>> +
>> +while (getline(, , fp) != -1) {
>> +GuestCpuStats *cpustat = NULL;
>> +int i;
>> +unsigned long user, system, idle, iowait, irq, softirq, steal,
>> guest;
>> +unsigned long nice, guest_nice;
>> +char name[64];
>> +
>> +i = sscanf(line, "%s %lu %lu %lu %lu %lu %lu %lu %lu %lu %lu",
>> +   name, , , , , , ,
>> ,
>> +   , , _nice);
>> +
>> +/* drop "cpu 1 2 3 ...", get "cpuX 1 2 3 ..." only */
>> +if (strncmp(name, "cpu", 3) || (name[3] == '\0')) {
>>
>
> For extra safety, check !name as well
>
>
>> +continue;
>> +}
>> +
>>
>
> if i < 5, I guess you should warn and continue
>

Why should we skip lines where i < 5? We have CPU time of user and system
modes, I think this is good for reporting.


>
>
>> +cpustat = g_new0(GuestCpuStats, 1);
>> +cpustat->cpu = atoi([3]);
>> +cpustat->has_user = true;
>> +cpustat->user = user * 10;
>>
>
> proc(5) says that the value is given "in units of USER_HZ (1/100ths of a
> second on most architectures, use sysconf(_SC_CLK_TCK) to obtain the right
> value)", so we should adjust this code if we want to return correctly in ms.
>
>
>> +cpustat->has_system = true;
>> +cpustat->system = system * 10;
>> +cpustat->has_idle = true;
>> +cpustat->idle = idle * 10;
>> +
>> +/* Linux version >= 2.6 */
>>
>
> That's pretty old now (2003), not sure anyone would care about that
> comment, but np ;)
>
>
>> +if (i > 5) {
>> +cpustat->has_iowait = true;
>> +cpustat->iowait = iowait * 10;
>> +cpustat->has_irq = true;
>> +cpustat->irq = irq * 10;
>> +cpustat->has_softirq = true;
>> +cpustat->softirq = softirq * 10;
>> +}
>> +
>> +if (i > 8) {
>> +cpustat->has_steal = true;
>> +cpustat->steal = steal * 10;
>> +}
>> +
>> +if (i > 9) {
>> +cpustat->has_guest = true;
>> +cpustat->guest = guest * 10;
>> +}
>> +
>> +QAPI_LIST_APPEND(tail, cpustat);
>> +}
>> +
>> +free(line);
>> +fclose(fp);
>> +return head;
>> +}
>> +
>>  #else /* defined(__linux__) */
>>
>>  void qmp_guest_suspend_disk(Error **errp)
>> @@ -3247,6 +3314,11 @@ GuestDiskStatsInfoList
>> *qmp_guest_get_diskstats(Error **errp)
>>  return NULL;
>>  }
>>
>> +GuestCpuStatsList *qmp_guest_get_cpustats(Error **errp)
>> +{
>> +error_setg(errp, QERR_UNSUPPORTED);
>> +return NULL;
>> +}
>>
>>  #endif /* CONFIG_FSFREEZE */
>>
>> diff --git a/qga/commands-win32.c b/qga/commands-win32.c
>> index 36f94c0f9c..7ed7664715 100644
>> --- a/qga/commands-win32.c
>> +++ b/qga/commands-win32.c
>> @@ -2543,3 +2543,9 @@ GuestDiskStatsInfoList
>> *qmp_guest_get_diskstats(Error **errp)
>>  error_setg(errp, QERR_UNSUPPORTED);
>>  return NULL;
>>  }
>> +
>> +GuestCpuStatsList *qmp_guest_get_cpustats(Error **errp)
>> +{
>> +error_setg(errp, QERR_UNSUPPORTED);
>> +return NULL;
>> +}
>> diff --git a/qga/qapi-schema.json b/qga/qapi-schema.json
>> index 9fa20e791b..4859c887b2 100644
>> --- a/qga/qapi-schema.json
>> +++ b/qga/qapi-schema.json
>> @@ -1576,3 +1576,52 @@
>>  { 'command': 'guest-get-diskstats',
>>'returns': ['GuestDiskStatsInfo']
>>  }
>> +
>> +##
>> +# @GuestCpuStats:
>> +#
>> +# Get statistics of each CPU in millisecond.
>> +#
>> +# @cpu: CPU index in guest OS
>> +#
>> +# @user: CPU time of user mode
>>
>
> "Time spent in user mode." is more understandable (from man proc(5))
>
> Same for the other descriptions.
>
> +#
>> +# 

Re: [PATCH 01/12] pc-bios/s390-ccw: Add a proper prototype for main()

[Eric Farman]

On Tue, 2022-06-28 at 15:10 +0200, Thomas Huth wrote:
> Older versions of Clang complain if there is no prototype for main().
> Add one, and while we're at it, make sure that we use the same type
> for main.c and netmain.c - since the return value does not matter,
> declare the return type of main() as "void".
> 
> Reviewed-by: Cornelia Huck 
> Signed-off-by: Thomas Huth 

Reviewed-by: Eric Farman 

> ---
>  pc-bios/s390-ccw/s390-ccw.h | 1 +
>  pc-bios/s390-ccw/main.c | 3 +--
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/pc-bios/s390-ccw/s390-ccw.h b/pc-bios/s390-ccw/s390-
> ccw.h
> index 79db69ff54..b88e0550ab 100644
> --- a/pc-bios/s390-ccw/s390-ccw.h
> +++ b/pc-bios/s390-ccw/s390-ccw.h
> @@ -57,6 +57,7 @@ void write_subsystem_identification(void);
>  void write_iplb_location(void);
>  extern char stack[PAGE_SIZE * 8]
> __attribute__((__aligned__(PAGE_SIZE)));
>  unsigned int get_loadparm_index(void);
> +void main(void);
>  
>  /* sclp.c */
>  void sclp_print(const char *string);
> diff --git a/pc-bios/s390-ccw/main.c b/pc-bios/s390-ccw/main.c
> index 5d2b7ba94d..835341457d 100644
> --- a/pc-bios/s390-ccw/main.c
> +++ b/pc-bios/s390-ccw/main.c
> @@ -281,7 +281,7 @@ static void probe_boot_device(void)
>  sclp_print("Could not find a suitable boot device (none
> specified)\n");
>  }
>  
> -int main(void)
> +void main(void)
>  {
>  sclp_setup();
>  css_setup();
> @@ -294,5 +294,4 @@ int main(void)
>  }
>  
>  panic("Failed to load OS from hard disk\n");
> -return 0; /* make compiler happy */
>  }

Re: [PATCH v4 12/45] target/arm: Mark gather prefetch as non-streaming

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:42, Richard Henderson
 wrote:
>
> Mark these as a non-streaming instructions, which should trap if full
> a64 support is not enabled in streaming mode.  In this case, introduce
> PRF_ns (prefetch non-streaming) to handle the checks.
>
> Signed-off-by: Richard Henderson 
> ---
>  target/arm/sme-fa64.decode |  3 ---
>  target/arm/sve.decode  | 10 +-
>  target/arm/translate-sve.c | 11 +++
>  3 files changed, 16 insertions(+), 8 deletions(-)

Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [PATCH v4 11/45] target/arm: Mark gather/scatter load/store as non-streaming

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:38, Richard Henderson
 wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson 

Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [PATCH 1/2] target/riscv: Fixup MSECCFG minimum priv check

[Bin Meng]

On Thu, Jun 30, 2022 at 7:31 AM Alistair Francis
 wrote:
>
> From: Alistair Francis 
>
> There is nothing in the RISC-V spec that mandates version 1.12 is
> required for ePMP and there is currently hardware [1] that implements
> ePMP (a draft version though) with the 1.11 priv spec.
>
> 1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
>
> Fixes: a4b2fa433125af0305b0695d7f8dda61db3364b0 target/riscv: Introduce 
> privilege version field in the CSR ops.

The format is

Fixes: 12 digits commit id ("commit title")

> Signed-off-by: Alistair Francis 
> ---
>  target/riscv/csr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6dbe9b541f..6379bef5a5 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3561,7 +3561,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>
>  /* Physical Memory Protection */
>  [CSR_MSECCFG]= { "mseccfg",  epmp, read_mseccfg, write_mseccfg,
> - .min_priv_ver = PRIV_VERSION_1_12_0 },
> + .min_priv_ver = PRIV_VERSION_1_11_0 },
>  [CSR_PMPCFG0]= { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
>  [CSR_PMPCFG1]= { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
>  [CSR_PMPCFG2]= { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
> --
>

Other than that,
Reviewed-by: Bin Meng 

Re: [PATCH v4 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:28, Richard Henderson
 wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson 

Reviewed-by: Peter Maydell 

thanks
-- PMM

[PATCH 0/3] hw/cxl, hw/machine, hw/i386: Misc minor fixes / cleanup

[Jonathan Cameron via]

Three more or less less unrelated fixes for recently added CXL code.

Jonathan Cameron (3):
  hw/machine: Clear out left over CXL related pointer from move of state
handling to machines.
  hw/i386/pc: Always place CXL Memory Regions after device_memory
  hw/cxl: Fix size of constant in interleave granularity function.

 hw/i386/pc.c   | 6 ++
 include/hw/boards.h| 1 -
 include/hw/cxl/cxl_component.h | 2 +-
 3 files changed, 3 insertions(+), 6 deletions(-)

-- 
2.32.0

[PATCH 17/17] x86: pci: acpi: deduplate PCI slots creation

[Igor Mammedov]

No functional change nor AML bytcode change.
Consolidate code that generates empty and populated slots
descriptors. Beside of eliminating duplication,
it helps to consolidate conditions for generating
parts of Device{} desriptor in one place, which makes
code more compact and easier to read.

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c | 111 +--
 1 file changed, 54 insertions(+), 57 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 406bbac1c7..9d0512666d 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -427,13 +427,41 @@ static void build_append_pci_bus_devices(Aml 
*parent_scope, PCIBus *bus,
 int func = PCI_FUNC(devfn);
 /* ACPI spec: 1.0b: Table 6-2 _ADR Object Bus Types, PCI type */
 int adr = slot << 16 | func;
-bool hotplug_enabled_dev;
-bool bridge_in_acpi;
-bool cold_plugged_bridge;
+bool hotpluggbale_slot = false;
+bool bridge_in_acpi = false;
+bool cold_plugged_bridge = false;
+bool is_vga = false;
+
+if (pdev) {
+pc = PCI_DEVICE_GET_CLASS(pdev);
+dc = DEVICE_GET_CLASS(pdev);
+
+if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
+continue;
+}
+
+is_vga = pc->class_id == PCI_CLASS_DISPLAY_VGA;
 
-if (!pdev) {
 /*
- * add hotplug slots for non present devices.
+ * Cold plugged bridges aren't themselves hot-pluggable.
+ * Hotplugged bridges *are* hot-pluggable.
+ */
+cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
+bridge_in_acpi =  cold_plugged_bridge && pcihp_bridge_en;
+
+hotpluggbale_slot = bsel && dc->hotpluggable &&
+!cold_plugged_bridge;
+
+/*
+ * allow describing coldplugged bridges in ACPI even if they are 
not
+ * on function 0, as they are not unpluggable, for all other 
devices
+ * generate description only for function 0 per slot
+ */
+if (func && !bridge_in_acpi) {
+continue;
+}
+} else {
+/*
  * hotplug is supported only for non-multifunction device
  * so generate device description only for function 0
  */
@@ -441,46 +469,11 @@ static void build_append_pci_bus_devices(Aml 
*parent_scope, PCIBus *bus,
 if (pci_bus_is_express(bus) && slot > 0) {
 break;
 }
-dev = aml_device("S%.02X", devfn);
-aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
-aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
-aml_append(dev, aml_pci_device_dsm());
-aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
-method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
-aml_append(method,
-aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
-);
-aml_append(dev, method);
-aml_append(parent_scope, dev);
-
-build_append_pcihp_notify_entry(notify_method, slot);
+/* mark it as empty hotpluggable slot */
+hotpluggbale_slot = true;
+} else {
+continue;
 }
-continue;
-}
-
-pc = PCI_DEVICE_GET_CLASS(pdev);
-dc = DEVICE_GET_CLASS(pdev);
-
-/*
- * Cold plugged bridges aren't themselves hot-pluggable.
- * Hotplugged bridges *are* hot-pluggable.
- */
-cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
-bridge_in_acpi =  cold_plugged_bridge && pcihp_bridge_en;
-
-hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
-
-if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
-continue;
-}
-
-/*
- * allow describing coldplugged bridges in ACPI even if they are not
- * on function 0, as they are not unpluggable, for all other devices
- * generate description only for function 0 per slot
- */
-if (func && !bridge_in_acpi) {
-continue;
 }
 
 /* start to compose PCI device descriptor */
@@ -496,7 +489,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, 
PCIBus *bus,
 aml_append(dev, aml_pci_device_dsm());
 }
 
-if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
+if (is_vga) {
 /* add VGA specific AML methods */
 int s3d;
 
@@ -517,19 +510,10 @@ static void build_append_pci_bus_devices(Aml 
*parent_scope, PCIBus *bus,
 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
 aml_append(method, aml_return(aml_int(s3d)));
 aml_append(dev, method);
-   

[PATCH 11/17] tests: acpi: whitelist pc/q35 DSDT before moving _ADR field

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..1983fa596b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,15 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/pc/DSDT",
+"tests/data/acpi/pc/DSDT.acpierst",
+"tests/data/acpi/pc/DSDT.acpihmat",
+"tests/data/acpi/pc/DSDT.bridge",
+"tests/data/acpi/pc/DSDT.cphp",
+"tests/data/acpi/pc/DSDT.dimmpxm",
+"tests/data/acpi/pc/DSDT.hpbridge",
+"tests/data/acpi/pc/DSDT.ipmikcs",
+"tests/data/acpi/pc/DSDT.memhp",
+"tests/data/acpi/pc/DSDT.nohpet",
+"tests/data/acpi/pc/DSDT.numamem",
+"tests/data/acpi/pc/DSDT.roothp",
+"tests/data/acpi/q35/DSDT.bridge",
+"tests/data/acpi/q35/DSDT.multi-bridge",
-- 
2.31.1

[PATCH 08/17] tests: acpi: whitelist pc/q35 DSDT before switching _DSM to use ASUN

[Igor Mammedov]

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..1983fa596b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1 +1,15 @@
 /* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/pc/DSDT",
+"tests/data/acpi/pc/DSDT.acpierst",
+"tests/data/acpi/pc/DSDT.acpihmat",
+"tests/data/acpi/pc/DSDT.bridge",
+"tests/data/acpi/pc/DSDT.cphp",
+"tests/data/acpi/pc/DSDT.dimmpxm",
+"tests/data/acpi/pc/DSDT.hpbridge",
+"tests/data/acpi/pc/DSDT.ipmikcs",
+"tests/data/acpi/pc/DSDT.memhp",
+"tests/data/acpi/pc/DSDT.nohpet",
+"tests/data/acpi/pc/DSDT.numamem",
+"tests/data/acpi/pc/DSDT.roothp",
+"tests/data/acpi/q35/DSDT.bridge",
+"tests/data/acpi/q35/DSDT.multi-bridge",
-- 
2.31.1

[PATCH RESEND 04/11] target/ppc: Move slbieg to decodetree

[Lucas Coutinho]

Reviewed-by: Leandro Lupori 
Signed-off-by: Lucas Coutinho 
---
 target/ppc/helper.h  |  2 +-
 target/ppc/insn32.decode |  1 +
 target/ppc/mmu-hash64.c  |  2 +-
 target/ppc/translate.c   | 13 -
 target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
 5 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index b51b3d9f07..8f9dde6d3f 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -696,7 +696,7 @@ DEF_HELPER_2(load_slb_vsid, tl, env, tl)
 DEF_HELPER_2(find_slb_vsid, tl, env, tl)
 DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
 DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
-DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
 #endif
 DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
 DEF_HELPER_FLAGS_3(store_sr, TCG_CALL_NO_RWG, void, env, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d282cf00c1..d3517d412c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -816,6 +816,7 @@ VMODUQ  000100 . . . 1101011@VX
 ## SLB Management Instructions
 
 SLBIE   01 - - . 0110110010 -   @X_rb
+SLBIEG  01 . - . 0111010010 -   @X_tb
 
 ## TLB Management Instructions
 
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 03f71a82ec..a842fbd6f6 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -202,7 +202,7 @@ void helper_SLBIE(CPUPPCState *env, target_ulong addr)
 __helper_slbie(env, addr, false);
 }
 
-void helper_slbieg(CPUPPCState *env, target_ulong addr)
+void helper_SLBIEG(CPUPPCState *env, target_ulong addr)
 {
 __helper_slbie(env, addr, true);
 }
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 14881e637f..ad19a68f5c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -5466,18 +5466,6 @@ static void gen_slbia(DisasContext *ctx)
 #endif /* defined(CONFIG_USER_ONLY) */
 }
 
-/* slbieg */
-static void gen_slbieg(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
-GEN_PRIV(ctx);
-#else
-CHK_SV(ctx);
-
-gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
 /* slbsync */
 static void gen_slbsync(DisasContext *ctx)
 {
@@ -6898,7 +6886,6 @@ GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, 
PPC_MEM_TLBIA),
 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
 #if defined(TARGET_PPC64)
 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
-GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
 #endif
 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x0001, PPC_EXTERN),
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc 
b/target/ppc/translate/storage-ctrl-impl.c.inc
index 41fc5ade8b..b9bb950f7d 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -35,6 +35,20 @@ static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
 return true;
 }
 
+static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIEG(cpu_env, cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
 static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
 {
 #if defined(CONFIG_USER_ONLY)
-- 
2.25.1

[PATCH RESEND 02/11] target/ppc: add macros to check privilege level

[Lucas Coutinho]

From: Matheus Ferst 

Equivalent to CHK_SV and CHK_HV, but can be used in decodetree methods.

Reviewed-by: Leandro Lupori 
Signed-off-by: Matheus Ferst 
Signed-off-by: Lucas Coutinho 
---
 target/ppc/translate.c | 21 +
 target/ppc/translate/fixedpoint-impl.c.inc |  7 ++-
 2 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 920bb543cf..275cffb2a7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6575,6 +6575,27 @@ static int times_16(DisasContext *ctx, int x)
 }   \
 } while (0)
 
+#if !defined(CONFIG_USER_ONLY)
+#define REQUIRE_SV(CTX) \
+do {\
+if (unlikely((CTX)->pr)) {  \
+gen_priv_opc(CTX);  \
+return true;\
+}   \
+} while (0)
+
+#define REQUIRE_HV(CTX) \
+do {\
+if (unlikely((CTX)->pr || !(CTX)->hv))  \
+gen_priv_opc(CTX);  \
+return true;\
+}   \
+} while (0)
+#else
+#define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#endif
+
 /*
  * Helpers for implementing sets of trans_* functions.
  * Defer the implementation of NAME to FUNC, with optional extra arguments.
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc 
b/target/ppc/translate/fixedpoint-impl.c.inc
index 1aab32be03..77d449c3cd 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -79,11 +79,8 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool 
store, bool prefixed)
 REQUIRE_INSNS_FLAGS(ctx, 64BX);
 
 if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
-if (ctx->pr) {
-/* lq and stq were privileged prior to V. 2.07 */
-gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
-return true;
-}
+/* lq and stq were privileged prior to V. 2.07 */
+REQUIRE_SV(ctx);
 
 if (ctx->le_mode) {
 gen_align_no_le(ctx);
-- 
2.25.1

[PATCH RESEND 11/11] target/ppc: Implement slbiag

[Lucas Coutinho]

Reviewed-by: Leandro Lupori 
Signed-off-by: Lucas Coutinho 
---
 target/ppc/helper.h  |  1 +
 target/ppc/insn32.decode |  4 +++
 target/ppc/mmu-hash64.c  | 27 
 target/ppc/translate/storage-ctrl-impl.c.inc | 14 ++
 4 files changed, 46 insertions(+)

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 649b2a9c58..2e7c61e117 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -695,6 +695,7 @@ DEF_HELPER_2(SLBMFEE, tl, env, tl)
 DEF_HELPER_2(SLBMFEV, tl, env, tl)
 DEF_HELPER_2(SLBFEE, tl, env, tl)
 DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_3(SLBIAG, TCG_CALL_NO_RWG, void, env, tl, i32)
 DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
 DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
 #endif
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index fb53bce0c8..e4aa336bbf 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -137,6 +137,9 @@
 _rb   rb
 @X_rb   .. . . rb:5 .. ._rb
 
+_rs_l rs l:bool
+@X_rs_l .. rs:5  l:1 . .. . _rs_l
+
 _uim5 xt uim:uint8_t
 @X_uim5 .. . . uim:5 .. .   _uim5 
xt=%x_xt
 
@@ -822,6 +825,7 @@ SLBIE   01 - - . 0110110010 -   
@X_rb
 SLBIEG  01 . - . 0111010010 -   @X_tb
 
 SLBIA   01 --... - - 010010 -   @X_ih
+SLBIAG  01 . . - 1101010010 -   @X_rs_l
 
 SLBMTE  01 . - . 0110010010 -   @X_tb
 
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7ec7a67a78..b9b31fd276 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -173,6 +173,33 @@ void helper_SLBIA(CPUPPCState *env, uint32_t ih)
 }
 }
 
+#if defined(TARGET_PPC64)
+void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l)
+{
+PowerPCCPU *cpu = env_archcpu(env);
+int n;
+
+/*
+ * slbiag must always flush all TLB (which is equivalent to ERAT in ppc
+ * architecture). Matching on SLB_ESID_V is not good enough, because slbmte
+ * can overwrite a valid SLB without flushing its lookaside information.
+ *
+ * It would be possible to keep the TLB in synch with the SLB by flushing
+ * when a valid entry is overwritten by slbmte, and therefore slbiag would
+ * not have to flush unless it evicts a valid SLB entry. However it is
+ * expected that slbmte is more common than slbiag, and slbiag is usually
+ * going to evict valid SLB entries, so that tradeoff is unlikely to be a
+ * good one.
+ */
+env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
+
+for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
+ppc_slb_t *slb = >slb[n];
+slb->esid &= ~SLB_ESID_V;
+}
+}
+#endif
+
 static void __helper_slbie(CPUPPCState *env, target_ulong addr,
target_ulong global)
 {
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc 
b/target/ppc/translate/storage-ctrl-impl.c.inc
index c90cad10b4..6a4ba4089e 100644
--- a/target/ppc/translate/storage-ctrl-impl.c.inc
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -63,6 +63,20 @@ static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
 return true;
 }
 
+static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
+
 static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
 {
 REQUIRE_64BIT(ctx);
-- 
2.25.1

Re: [PULL 14/15] qdev: Base object creation on QDict rather than QemuOpts

[Peter Maydell]

On Fri, 15 Oct 2021 at 16:01, Kevin Wolf  wrote:
> QDicts are both what QMP natively uses and what the keyval parser
> produces. Going through QemuOpts isn't useful for either one, so switch
> the main device creation function to QDicts. By sharing more code with
> the -object/object-add code path, we can even reduce the code size a
> bit.
>
> This commit doesn't remove the detour through QemuOpts from any code
> path yet, but it allows the following commits to do so.
>
> Signed-off-by: Kevin Wolf 
> Message-Id: <20211008133442.141332-15-kw...@redhat.com>
> Reviewed-by: Michael S. Tsirkin 
> Tested-by: Peter Krempa 
> Signed-off-by: Kevin Wolf 

Hi; we discovered via a report on IRC this this commit broke
handling of "array properties", of which one example is:
qemu-system-x86_64 -netdev user,id=a -device rocker,len-ports=1,ports[0]=a

This used to work, and now fails with
 qemu-system-x86_64: -device rocker,len-ports=1,ports[0]=a: Property
'rocker.ports[0]' not found

I think this happens because array properties have the
requirement that the len-foo property is set first before
any of the foo[n] properties can be set. In the old code
I guess we used to set properties from the command line
in the order they were specified, whereas in the new code
we end up in object_set_properties_from_qdict() which
tries to set them in whatever order the qdict hash table
provides them, which turns out to be the wrong one :-(

Any suggestions for how to address this ?

thanks
-- PMM

Re: [PATCH] ebpf: replace deprecated bpf_program__set_socket_filter

[Peter Maydell]

On Wed, 8 Jun 2022 at 09:17, Jason Wang  wrote:
>
> On Tue, May 31, 2022 at 1:40 PM Zhang, Chen  wrote:
> >
> >
> >
> > > -Original Message-
> > > From: Qemu-devel  > > bounces+chen.zhang=intel@nongnu.org> On Behalf Of Haochen Tong
> > > Sent: Saturday, May 28, 2022 3:07 AM
> > > To: qemu-devel@nongnu.org
> > > Cc: qemu-triv...@nongnu.org; Haochen Tong 
> > > Subject: [PATCH] ebpf: replace deprecated bpf_program__set_socket_filter
> > >
> > > bpf_program__set_ functions have been deprecated since libbpf 0.8.
> > > Replace with the equivalent bpf_program__set_type call to avoid a
> > > deprecation warning.
> > >
> > > Signed-off-by: Haochen Tong 
> >
> > It looks good to me.
> > By the way, add eBPF maintainers.
> > Reviewed-by: Zhang Chen 
>
> Applied.

Hi -- did this patch get lost somewhere ? We just had a
report about it on irc and it doesn't seem to be in master yet.

thanks
-- PMM

Re: [PATCH 2/2] target/riscv: Ibex: Support priv version 1.11

[Bin Meng]

On Thu, Jun 30, 2022 at 7:31 AM Alistair Francis
 wrote:
>
> From: Alistair Francis 
>
> The Ibex CPU supports version 1.11 of the priv spec [1], so let's
> correct that in QEMU as well.
>
> 1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
>
> Signed-off-by: Alistair Francis 
> ---
>  target/riscv/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng 

Re: [PATCH v4 15/45] target/arm: Add SME enablement checks

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:32, Richard Henderson
 wrote:
>
> These functions will be used to verify that the cpu
> is in the correct state for a given instruction.
>
> Signed-off-by: Richard Henderson 
> ---


Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [PATCH 1/2] hw: m25p80: Add Block Protect and Top Bottom bits for write protect

[Francisco Iglesias]

On [2022 Jul 01] Fri 14:23:17, Cédric Le Goater wrote:
> On 7/1/22 13:40, Francisco Iglesias wrote:
> > Hi Iris,
> > 
> > Looks good, a couple of minor comments below!
> > 
> > On [2022 Jun 27] Mon 11:52:33, Iris Chen wrote:
> > > Signed-off-by: Iris Chen 
> > > ---
> > >   hw/block/m25p80.c | 74 +++
> > >   1 file changed, 62 insertions(+), 12 deletions(-)
> > > 
> > > diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> > > index 50b523e5b1..0156a70f5e 100644
> > > --- a/hw/block/m25p80.c
> > > +++ b/hw/block/m25p80.c
> > > @@ -38,21 +38,19 @@
> > >   #include "trace.h"
> > >   #include "qom/object.h"
> > > -/* Fields for FlashPartInfo->flags */
> > > -
> > > -/* erase capabilities */
> > > -#define ER_4K 1
> > > -#define ER_32K 2
> > > -/* set to allow the page program command to write 0s back to 1. Useful 
> > > for
> > > - * modelling EEPROM with SPI flash command set
> > > - */
> > > -#define EEPROM 0x100
> > > -
> > >   /* 16 MiB max in 3 byte address mode */
> > >   #define MAX_3BYTES_SIZE 0x100
> > > -
> > >   #define SPI_NOR_MAX_ID_LEN 6
> > > +/* Fields for FlashPartInfo->flags */
> > > +enum spi_nor_option_flags {
> > 
> > (A suggestion is to s/nor/flash/ above (and s/SNOR_F_//  below) since there
> > looks to be nand flashes as W25N01GV using the protocol to).
> > 
> > > +ER_4K  = BIT(0),
> > > +ER_32K = BIT(1),
> > > +EEPROM = BIT(2),
> > > +SNOR_F_HAS_SR_TB   = BIT(3),
> > > +SNOR_F_HAS_SR_BP3_BIT6 = BIT(4),
> > > +};
> > > +
> > >   typedef struct FlashPartInfo {
> > >   const char *part_name;
> > >   /*
> > > @@ -253,7 +251,8 @@ static const FlashPartInfo known_devices[] = {
> > >   { INFO("n25q512a11",  0x20bb20,  0,  64 << 10, 1024, ER_4K) },
> > >   { INFO("n25q512a13",  0x20ba20,  0,  64 << 10, 1024, ER_4K) },
> > >   { INFO("n25q128", 0x20ba18,  0,  64 << 10, 256, 0) },
> > > -{ INFO("n25q256a",0x20ba19,  0,  64 << 10, 512, ER_4K) },
> > > +{ INFO("n25q256a",0x20ba19,  0,  64 << 10, 512,
> > > +   ER_4K | SNOR_F_HAS_SR_BP3_BIT6 | SNOR_F_HAS_SR_TB) },
> > >   { INFO("n25q512a",0x20ba20,  0,  64 << 10, 1024, ER_4K) },
> > >   { INFO("n25q512ax3",  0x20ba20,  0x1000,  64 << 10, 1024, ER_4K) },
> > >   { INFO("mt25ql512ab", 0x20ba20, 0x1044, 64 << 10, 1024, ER_4K | 
> > > ER_32K) },
> > > @@ -480,6 +479,11 @@ struct Flash {
> > >   bool reset_enable;
> > >   bool quad_enable;
> > >   bool aai_enable;
> > > +bool block_protect0;
> > > +bool block_protect1;
> > > +bool block_protect2;
> > > +bool block_protect3;
> > > +bool top_bottom_bit;
> > >   bool status_register_write_disabled;
> > >   uint8_t ear;
> > > @@ -630,6 +634,29 @@ void flash_write8(Flash *s, uint32_t addr, uint8_t 
> > > data)
> > >   qemu_log_mask(LOG_GUEST_ERROR, "M25P80: write with write 
> > > protect!\n");
> > >   return;
> > >   }
> > > +uint32_t block_protect_value = (s->block_protect3 << 3) |
> > > +   (s->block_protect2 << 2) |
> > > +   (s->block_protect1 << 1) |
> > > +   (s->block_protect0 << 0);
> > > +
> > > + uint32_t num_protected_sectors = 1 << (block_protect_value - 1);
> > > + uint32_t sector = addr / s->pi->sector_size;
> > > +
> > > + /* top_bottom_bit == 0 means TOP */
> > 
> > Indentation needs minor fixing on above lines, also the declarations should
> > be at the top of the function.
> 

Hi Cédric,

> I agree in that case it would be better to have at the top
> but checkpatch does not complain. What's the rule ?
> 

Below is taken from docs/devel/style.rst:

"
Declarations


Mixed declarations (interleaving statements and declarations within
blocks) are generally not allowed; declarations should be at the beginning
of blocks.

Every now and then, an exception is made for declarations inside a
#ifdef or #ifndef block: if the code looks nicer, such declarations can
be placed at the top of the block even if there are statements above.
On the other hand, however, it's often best to move that #ifdef/#ifndef
block to a separate function altogether
"

I understand above as this is generally not allowed but in case you would
prefer to keep the declarations as they are placed one can see this as 'code
looks nicer' (to me the loop case is often cleaner in the way you are
mentioning). I should though have been more clear that 'moving to the top' was
a suggestion for not breaking this 'general rule' (also in case I've
interpreted this wrongly), sorry for that!

Best regards,
Francisco Iglesias

> For loop indexes, I do prefer to declare in the block
> statement.
> 
> > 
> > > +if (!s->top_bottom_bit) {
> > > +if (block_protect_value > 0 &&
> > > +s->pi->n_sectors <= sector + num_protected_sectors) {
> 

[PATCH 03/17] tests: acpi: update expected blobs after HPET move

[Igor Mammedov]

HPET AML moved after PCI host bridge description (no functional change)

diff example for PC machine:

@@ -54,47 +54,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)
 }
 }

-Scope (_SB)
-{
-Device (HPET)
-{
-Name (_HID, EisaId ("PNP0103") /* HPET System Timer */)  // _HID: 
Hardware ID
-Name (_UID, Zero)  // _UID: Unique ID
-OperationRegion (HPTM, SystemMemory, 0xFED0, 0x0400)
-Field (HPTM, DWordAcc, Lock, Preserve)
-{
-VEND,   32,
-PRD,32
-}
-
-Method (_STA, 0, NotSerialized)  // _STA: Status
-{
-Local0 = VEND /* \_SB_.HPET.VEND */
-Local1 = PRD /* \_SB_.HPET.PRD_ */
-Local0 >>= 0x10
-If (((Local0 == Zero) || (Local0 == 0x)))
-{
-Return (Zero)
-}
-
-If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
-{
-Return (Zero)
-}
-
-Return (0x0F)
-}
-
-Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-{
-Memory32Fixed (ReadOnly,
-0xFED0, // Address Base
-0x0400, // Address Length
-)
-})
-}
-}
-
 Scope (_SB.PCI0)
 {
 Device (ISA)
@@ -529,6 +488,47 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)
 }
 }

+Scope (_SB)
+{
+Device (HPET)
+{
+Name (_HID, EisaId ("PNP0103") /* HPET System Timer */)  // _HID: 
Hardware ID
+Name (_UID, Zero)  // _UID: Unique ID
+OperationRegion (HPTM, SystemMemory, 0xFED0, 0x0400)
+Field (HPTM, DWordAcc, Lock, Preserve)
+{
+VEND,   32,
+PRD,32
+}
+
+Method (_STA, 0, NotSerialized)  // _STA: Status
+{
+Local0 = VEND /* \_SB_.HPET.VEND */
+Local1 = PRD /* \_SB_.HPET.PRD_ */
+Local0 >>= 0x10
+If (((Local0 == Zero) || (Local0 == 0x)))
+{
+Return (Zero)
+}
+
+If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+{
+Return (Zero)
+}
+
+Return (0x0F)
+}
+
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+{
+Memory32Fixed (ReadOnly,
+0xFED0, // Address Base
+0x0400, // Address Length
+)
+})
+}
+}
+
 Scope (_SB)
 {
 Device (\_SB.PCI0.PRES)

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h |  32 
 tests/data/acpi/pc/DSDT | Bin 5987 -> 5987 bytes
 tests/data/acpi/pc/DSDT.acpierst| Bin 5954 -> 5954 bytes
 tests/data/acpi/pc/DSDT.acpihmat| Bin 7312 -> 7312 bytes
 tests/data/acpi/pc/DSDT.bridge  | Bin 8653 -> 8653 bytes
 tests/data/acpi/pc/DSDT.cphp| Bin 6451 -> 6451 bytes
 tests/data/acpi/pc/DSDT.dimmpxm | Bin 7641 -> 7641 bytes
 tests/data/acpi/pc/DSDT.hpbridge| Bin 5954 -> 5954 bytes
 tests/data/acpi/pc/DSDT.hpbrroot| Bin 3069 -> 3069 bytes
 tests/data/acpi/pc/DSDT.ipmikcs | Bin 6059 -> 6059 bytes
 tests/data/acpi/pc/DSDT.memhp   | Bin 7346 -> 7346 bytes
 tests/data/acpi/pc/DSDT.numamem | Bin 5993 -> 5993 bytes
 tests/data/acpi/pc/DSDT.roothp  | Bin 6195 -> 6195 bytes
 tests/data/acpi/q35/DSDT| Bin 8274 -> 8274 bytes
 tests/data/acpi/q35/DSDT.acpierst   | Bin 8291 -> 8291 bytes
 tests/data/acpi/q35/DSDT.acpihmat   | Bin 9599 -> 9599 bytes
 tests/data/acpi/q35/DSDT.applesmc   | Bin 8320 -> 8320 bytes
 tests/data/acpi/q35/DSDT.bridge | Bin 10988 -> 10988 bytes
 tests/data/acpi/q35/DSDT.cphp   | Bin 8738 -> 8738 bytes
 tests/data/acpi/q35/DSDT.cxl| Bin 9600 -> 9600 bytes
 tests/data/acpi/q35/DSDT.dimmpxm| Bin 9928 -> 9928 bytes
 tests/data/acpi/q35/DSDT.ipmibt | Bin 8349 -> 8349 bytes
 tests/data/acpi/q35/DSDT.ipmismbus  | Bin 8363 -> 8363 bytes
 tests/data/acpi/q35/DSDT.ivrs   | Bin 8291 -> 8291 bytes
 tests/data/acpi/q35/DSDT.memhp  | Bin 9633 -> 9633 bytes
 tests/data/acpi/q35/DSDT.mmio64 | Bin 9404 -> 9404 bytes
 tests/data/acpi/q35/DSDT.multi-bridge   | Bin 8568 -> 8568 bytes
 tests/data/acpi/q35/DSDT.numamem| Bin 8280 -> 8280 bytes
 tests/data/acpi/q35/DSDT.pvpanic-isa  

Re: [PATCH v4 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:28, Richard Henderson
 wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson 
> ---
>  target/arm/sme-fa64.decode |  3 ---
>  target/arm/translate-sve.c | 22 --
>  2 files changed, 12 insertions(+), 13 deletions(-)
>

Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: venv for python qtest bits? (was: Re: [PATCH 11/12] acpi/tests/bits: add README file for bits qtests)

[Michael S. Tsirkin]

On Fri, Jul 01, 2022 at 03:44:32PM +0530, Ani Sinha wrote:
> but I thought you were suggesting we built bits every time the test is run?

In my opinion 3 scenarios are worth supporting:
- people not touching ACPI, including users - simply don't run the tests,
comparing tables with expected output should be enough
- people making changes indirectly affecting ACPI -
use tests to validate that tables are still well formed,
using a pre built binary should be enough IMO
- people working on ACPI - use tests to analyse the tables,
building from source might be necessary for debugging,
sources change very rarely
- people developing the tests
building from source is required

So I would suggest basically two github repos, one with binaries one with
sources. We'll keep relevant hashes to use in the script.
All in all not that different from submodules but I guess
people have submodules and that is that.

And I personally would probably not tie it to CI whoever owns the
repository can worry about the builds, and I think keeping
things distributed is important.

So
- people not touching ACPI - make check should see directory not found
and skip the test
- people making changes indirectly affecting ACPI -
check out binaries and use
- people working on ACPI -
see that source directory is present, go there
and run make. should not rebuild each time right?
- people developing the tests
building from source is required


-- 
MST

Re: [PATCH v4 14/45] target/arm: Mark LD1RO as non-streaming

[Peter Maydell]

On Tue, 28 Jun 2022 at 05:49, Richard Henderson
 wrote:
>
> Mark these as a non-streaming instructions, which should trap
> if full a64 support is not enabled in streaming mode.
>
> Signed-off-by: Richard Henderson 
> ---
>  target/arm/sme-fa64.decode | 3 ---
>  target/arm/translate-sve.c | 2 ++
>  2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/sme-fa64.decode b/target/arm/sme-fa64.decode
> index 7a0b05cf2c..33bbd13bcb 100644
> --- a/target/arm/sme-fa64.decode
> +++ b/target/arm/sme-fa64.decode
> @@ -57,6 +57,3 @@ FAIL1100 1110         # 
> Advanced SIMD cryptography e
>  #   --11 1100 --0-        # Load/store FP register 
> (unscaled imm)
>  #   --11 1100 --1-     --10   # Load/store FP register 
> (register offset)
>  #   --11 1101         # Load/store FP register 
> (scaled imm)
> -
> -FAIL1010 010- -10-  000-      # SVE load & replicate 32 
> bytes (scalar+scalar)
> -FAIL1010 010- -100  001-      # SVE load & replicate 32 
> bytes (scalar+imm)
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index 11874a8e77..e5e9e1e0ca 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -5062,6 +5062,7 @@ static bool trans_LD1RO_zprr(DisasContext *s, 
> arg_rprr_load *a)
>  if (a->rm == 31) {
>  return false;
>  }
> +s->is_nonstreaming = true;
>  if (sve_access_check(s)) {
>  TCGv_i64 addr = new_tmp_a64(s);
>  tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
> @@ -5076,6 +5077,7 @@ static bool trans_LD1RO_zpri(DisasContext *s, 
> arg_rpri_load *a)
>  if (!dc_isar_feature(aa64_sve_f64mm, s)) {
>  return false;
>  }
> +s->is_nonstreaming = true;
>  if (sve_access_check(s)) {
>  TCGv_i64 addr = new_tmp_a64(s);
>  tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), a->imm * 32);

The sve.decode lines for these two trans functions:
LD1RO_zprr  1010010 .. 01 . 000 ... . . \
@rprr_load_msz nreg=0
LD1RO_zpri  1010010 .. 01 0 001 ... . . \
@rpri_load_msz nreg=0

don't match up with the FAIL line.

The FAIL lines correspond to unallocated encodings in the decode
tables in the main Arm ARM so we can assume this is an error in the SME
supplement.

We should use the right encoding lines in the original commit of
sme-fa64.decode and mention that in its commit message. They should
I believe be:

 FAIL1010 010- -01-  000-      # SVE load &
replicate 32 bytes (scalar+scalar)
 FAIL1010 010- -010  001-      # SVE load &
replicate 32 bytes (scalar+imm)

(differences only in bits [22:21]).

For this patch,
Reviewed-by: Peter Maydell 

thanks
-- PMM

[PATCH 3/3] hw/cxl: Fix size of constant in interleave granularity function.

[Jonathan Cameron via]

Whilst the interleave granularity is always small enough that this isn't
a real problem (much less than 4GiB) let's change the constant
to ULL to fix the coverity warning.

Reported-by: Peter Maydell 
Fixes: 829de299d1 ("hw/cxl/component: Add utils for interleave parameter 
encoding/decoding")
Fixes: Coverity CID 1488868
Signed-off-by: Jonathan Cameron 
---
 include/hw/cxl/cxl_component.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
index 70b5018156..94ec2f07d7 100644
--- a/include/hw/cxl/cxl_component.h
+++ b/include/hw/cxl/cxl_component.h
@@ -215,7 +215,7 @@ uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error 
**errp);
 
 static inline hwaddr cxl_decode_ig(int ig)
 {
-return 1 << (ig + 8);
+return 1ULL << (ig + 8);
 }
 
 CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb);
-- 
2.32.0

[PATCH 10/17] tests: acpi: update expected blobs

[Igor Mammedov]

It's expected that hotpluggable slots will, get ASUN variable
and use that instead of _SUN with its _DSM method.

For example:

  @@ -979,8 +979,9 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)

   Device (S18)
   {
  -Name (_SUN, 0x03)  // _SUN: Slot User Number
  +Name (ASUN, 0x03)
   Name (_ADR, 0x0003)  // _ADR: Address
  +Name (_SUN, 0x03)  // _SUN: Slot User Number
   Method (_EJ0, 1, NotSerialized)  // _EJx: Eject Device
   {
   PCEJ (BSEL, _SUN)
  @@ -991,7 +992,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC", 
0x0001)
   Local0 = Package (0x02)
   {
   BSEL,
  -_SUN
  +ASUN
   }
   Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
   }

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h |  14 --
 tests/data/acpi/pc/DSDT | Bin 6219 -> 6422 bytes
 tests/data/acpi/pc/DSDT.acpierst| Bin 6186 -> 6382 bytes
 tests/data/acpi/pc/DSDT.acpihmat| Bin 7544 -> 7747 bytes
 tests/data/acpi/pc/DSDT.bridge  | Bin 9078 -> 9496 bytes
 tests/data/acpi/pc/DSDT.cphp| Bin 6683 -> 6886 bytes
 tests/data/acpi/pc/DSDT.dimmpxm | Bin 7873 -> 8076 bytes
 tests/data/acpi/pc/DSDT.hpbridge| Bin 6186 -> 6382 bytes
 tests/data/acpi/pc/DSDT.ipmikcs | Bin 6291 -> 6494 bytes
 tests/data/acpi/pc/DSDT.memhp   | Bin 7578 -> 7781 bytes
 tests/data/acpi/pc/DSDT.nohpet  | Bin 6077 -> 6280 bytes
 tests/data/acpi/pc/DSDT.numamem | Bin 6225 -> 6428 bytes
 tests/data/acpi/pc/DSDT.roothp  | Bin 6434 -> 6656 bytes
 tests/data/acpi/q35/DSDT.bridge | Bin 11227 -> 11449 bytes
 tests/data/acpi/q35/DSDT.multi-bridge   | Bin 8628 -> 8640 bytes
 15 files changed, 14 deletions(-)

diff --git a/tests/qtest/bios-tables-test-allowed-diff.h 
b/tests/qtest/bios-tables-test-allowed-diff.h
index 1983fa596b..dfb8523c8b 100644
--- a/tests/qtest/bios-tables-test-allowed-diff.h
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
@@ -1,15 +1 @@
 /* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/pc/DSDT",
-"tests/data/acpi/pc/DSDT.acpierst",
-"tests/data/acpi/pc/DSDT.acpihmat",
-"tests/data/acpi/pc/DSDT.bridge",
-"tests/data/acpi/pc/DSDT.cphp",
-"tests/data/acpi/pc/DSDT.dimmpxm",
-"tests/data/acpi/pc/DSDT.hpbridge",
-"tests/data/acpi/pc/DSDT.ipmikcs",
-"tests/data/acpi/pc/DSDT.memhp",
-"tests/data/acpi/pc/DSDT.nohpet",
-"tests/data/acpi/pc/DSDT.numamem",
-"tests/data/acpi/pc/DSDT.roothp",
-"tests/data/acpi/q35/DSDT.bridge",
-"tests/data/acpi/q35/DSDT.multi-bridge",
diff --git a/tests/data/acpi/pc/DSDT b/tests/data/acpi/pc/DSDT
index 
cb718f1a8a591b27ca841f70f40762562c15c837..8282d449ceaefd914b419f507a13f3fb7b318aaf
 100644
GIT binary patch
delta 1170
zcmY++OHRU207l^w3Y0==%cD>pC2<9aFC2o!nHsImOu7UUx8MRCkhlsHV;r#tSKw}p
z=0C~3(~~dfd-1mP^CG`bQpc{>f3<%si%l7A_q&(iHM?<(!|6i-&8!>XqyK
zuI)Hg$1DHC?lwHweFX6zTQ0<0m@DR5j9U#>6RVl*h+7?27pq&0TLab*Ynbeqn+Nm6
zJd1H_!kS`Dlbvw$VZNAeF>WnbORQzGQ*LcoTdZv{ZUHP13ru##tpn?bbu7j$goR?E
z$yVGVSR@u%j9Uzg#bT44bL+yoVqJ@I>%n?rJ(I1u^w4F>W*1Ol)Sd
YOKuq~6U!{dZ4R4@=j5mI3(bW3jsO4v

delta 1329
zcmaLPIZnd>6aZ0MaT3R|9cQ((OR1cIN|u5%00*Fm#0e;
za19nQ<^S#IX`UyaV<$?}P$c5-$$
zOHN(G$Qg@!f3)-)=PxHodUSPtb34Cy_`#F$KeoV@f;s2Gc^R*9E`SRP=3E39WxUSW
z2HOheTmqM5yusN4I|}Ap2A5^L$=Lj6qH3f67gX=P$ac+Pc3g+AdH)R}iZh>10<{W}U8Sik8z>$JEx4~^0C!9Orj)FON
k!Ce{ea_)h93g+Ag_hr1tc>o?LnDY=k{KIDUu@Zin-wNzyDF6Tf

diff --git a/tests/data/acpi/pc/DSDT.acpierst b/tests/data/acpi/pc/DSDT.acpierst
index 
aebb29c2a4ae67b732bef3eb8e72c5665bb3a7b3..9520f3b7303a43091e8c77b64d1f76407e85f1f4
 100644
GIT binary patch
delta 1131
zcmY++OG?8~07l^y`bck+Cg~$hUn#hP`mV#))R_uKXJVG%B3wdu;Y38x6*zO^M!E(;
z{sZ?;4o^B_=NKiJXA2}5qR{6ZSxVuU-mC@|70cr

diff --git a/tests/data/acpi/pc/DSDT.acpihmat b/tests/data/acpi/pc/DSDT.acpihmat
index 
b7c5de46346d2777b33f7fc464d319bd762fda8d..33169838bed50710495d45e0d9486ac59b4e504c
 100644
GIT binary patch
delta 1170
zcmY++yGp}g07vl@dr8x@x%Hkl1)spXRb1MpZYmhvgv>sTLsvl`L2>HrQwTnYqbUCa
z-?tuqoS*a03okG7yH(~mmB)AQIrgr$4`s0|!}WIa7C)nb2Mx{Koe+S_r~6l}=#L%jiB(}$v8u(m)nGNTn#m5i)nRq9y2ZFPU=6W`$?WFjvgA
z7`G;@Db_UEF*gt9iFp>|)`GRfS|=EHn3-(uX_u(nv+WT)IZu#Q;AV%!2)AQqTx
z*RLGT9lo7#54g7UPz{60yW&3vOLlSFCF>Zar8}tY@+%w?3>d*0
z0c;>PFxiUR5H=JWT8!HWHWC||Eax_cjm5?mLNHQC_aJ@
zk@Hc9JG%H<4kOpRe}4XUETzER8ew@M-?y-315vba|9nS$ckK
z=d5g;oH~Y)Gv*Ke!s2h7KAt4$(d_c-dU|pDgIAXRaUPskFy{ieAmdfeMQ~BUoJ-)6
zjMq3@U`xTA%iyw%*E!o@Tfv+w;EIelI6GiR!JMn$s*E=|*T6LebFPEyG9Gbu!LEWi
zH^2=UZ*lg(o`N|y!A%*DIs0H=!JJ#*mW*T0ZE#z`oC9zm<6X`ja7V$MyWp;j6V5$w

[PATCH 12/17] x86: pci: acpi: reorder Device's _ADR and _SUN fields

[Igor Mammedov]

no functional change, align order of fields in empty slot
descriptor with a populated slot ordering.
Expected diff:
  -Name (_SUN, 0x0X)  // _SUN: Slot User Number
   Name (_ADR, 0xY)  // _ADR: Address
  ...
  +Name (_SUN, 0xX)  // _SUN: Slot User Number

that will eliminate contextual changes (causing test failures)
when follow up patches merge code generating populated and empty
slots descriptors.

Put mandatory _ADR as the 1st field, then ASUN as it can be
present for both pupulated and empty slots and only then _SUN
which is present only when slot is hotpluggable.

Signed-off-by: Igor Mammedov 
---
 hw/i386/acpi-build.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 36fe43c52f..fd7f3253e5 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -442,8 +442,8 @@ static void build_append_pci_bus_devices(Aml *parent_scope, 
PCIBus *bus,
 break;
 }
 dev = aml_device("S%.02X", devfn);
-aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
 aml_append(dev, aml_name_decl("_ADR", aml_int(adr)));
+aml_append(dev, aml_name_decl("ASUN", aml_int(slot)));
 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
 aml_append(method,
-- 
2.31.1

[PATCH 07/17] tests: acpi: update expected blobs

[Igor Mammedov]

An intermediate blobs update to keep changes (last 2 patches)
reviewable.

Includes refactored PDSM that uses Package argument for custom
parameters.

 = PDSM taking package as arguments

 Return (Local0)
 }

-Method (PDSM, 6, Serialized)
+Method (PDSM, 5, Serialized)
 {
-If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* 
Device Labeling Interface */))
+If ((Arg2 == Zero))
 {
-Local0 = AIDX (Arg4, Arg5)
-If ((Arg2 == Zero))
-{
-If ((Arg1 == 0x02))
+Local0 = Buffer (One)
 {
-If (!((Local0 == Zero) | (Local0 == 0x)))
-{
-Return (Buffer (One)
-{
- 0x81  
   // .
-})
-}
+ 0x00 // .
 }
+Local1 = Zero
+If ((Arg0 != ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") 
/* Device Labeling Interface */))
+{
+Return (Local0)
+}

-Return (Buffer (One)
-{
- 0x00 // .
-})
+If ((Arg1 < 0x02))
+{
+Return (Local0)
 }
-ElseIf ((Arg2 == 0x07))
+
+Local2 = AIDX (DerefOf (Arg4 [Zero]), DerefOf (Arg4 [One]
+))
+If (!((Local2 == Zero) | (Local2 == 0x)))
 {
-Local1 = Package (0x02)
-{
-Zero,
-""
-}
-Local1 [Zero] = Local0
-Return (Local1)
+Local1 |= One
+Local1 |= (One << 0x07)
 }
+
+Local0 [Zero] = Local1
+Return (Local0)
+}
+
+If ((Arg2 == 0x07))
+{
+Local0 = Package (0x02)
+{
+Zero,
+""
+}
+Local2 = AIDX (DerefOf (Arg4 [Zero]), DerefOf (Arg4 [One]
+))
+Local0 [Zero] = Local2
+Return (Local0)
 }
 }
 }

 =  PCI slot using Package to pass arguments to _DSM

 Name (ASUN, Zero)
 Method (_DSM, 4, Serialized)  // _DSM: Device-Specific Method
 {
-Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, ASUN))
+Local0 = Package (0x02)
+{
+BSEL,
+ASUN
+}
+Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
 }
 }

 = hotpluggable PCI slot using Package to pass arguments to _DSM

 Method (_DSM, 4, Serialized)  // _DSM: Device-Specific Method
 {
-Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN))
+Local0 = Package (0x02)
+{
+BSEL,
+_SUN
+}
+Return (PDSM (Arg0, Arg1, Arg2, Arg3, Local0))
 }
 }

Signed-off-by: Igor Mammedov 
---
 tests/qtest/bios-tables-test-allowed-diff.h |  34 
 tests/data/acpi/pc/DSDT | Bin 5987 -> 6219 bytes
 tests/data/acpi/pc/DSDT.acpierst| Bin 5954 -> 6186 bytes
 tests/data/acpi/pc/DSDT.acpihmat| Bin 7312 -> 7544 bytes
 tests/data/acpi/pc/DSDT.bridge  | Bin 8653 -> 9078 bytes
 tests/data/acpi/pc/DSDT.cphp| Bin 6451 -> 6683 bytes
 tests/data/acpi/pc/DSDT.dimmpxm | Bin 7641 -> 7873 bytes
 tests/data/acpi/pc/DSDT.hpbridge| Bin 5954 -> 6186 bytes
 tests/data/acpi/pc/DSDT.ipmikcs | Bin 6059 -> 6291 bytes
 tests/data/acpi/pc/DSDT.memhp   | Bin 7346 -> 7578 bytes
 tests/data/acpi/pc/DSDT.nohpet  | Bin 5845 -> 6077 bytes
 tests/data/acpi/pc/DSDT.numamem | Bin 5993 -> 6225 bytes
 tests/data/acpi/pc/DSDT.roothp  | Bin 6195 -> 6434 bytes
 tests/data/acpi/q35/DSDT| Bin 8274 -> 8320 bytes
 tests/data/acpi/q35/DSDT.acpierst   | Bin 8291 -> 8337 bytes
 tests/data/acpi/q35/DSDT.acpihmat   | Bin 9599 -> 9645 bytes
 tests/data/acpi/q35/DSDT.applesmc   | Bin 8320 -> 8366 bytes
 tests/data/acpi/q35/DSDT.bridge |