CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2017-12-03 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Sun Dec  3 10:29:12 UTC 2017

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: a9_mpsubr.S

Log Message:
Pull up following revision(s) (requested by skrll in ticket #1524):
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.52
Ensure CNTVOFF is 0 before dropping out of Hyp mode


To generate a diff of this commit:
cvs rdiff -u -r1.18.2.5 -r1.18.2.6 src/sys/arch/arm/cortex/a9_mpsubr.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/a9_mpsubr.S
diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.18.2.5 src/sys/arch/arm/cortex/a9_mpsubr.S:1.18.2.6
--- src/sys/arch/arm/cortex/a9_mpsubr.S:1.18.2.5	Sat Jul  8 17:01:52 2017
+++ src/sys/arch/arm/cortex/a9_mpsubr.S	Sun Dec  3 10:29:12 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: a9_mpsubr.S,v 1.18.2.5 2017/07/08 17:01:52 snj Exp $	*/
+/*	$NetBSD: a9_mpsubr.S,v 1.18.2.6 2017/12/03 10:29:12 snj Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -338,6 +338,10 @@ cortex_init:
 	teq	r0, #(PSR_HYP32_MODE)	/* Hyp Mode? */
 	bne	1f
 
+	/* Set CNTVOFF to 0 */
+	mov	r0, #0
+	mcrr	p15, 4, r0, r0, c14
+
 	/* Ensure that IRQ, and FIQ will be disabled after eret */
 	mrs	r0, cpsr
 	bic	r0, r0, #(PSR_MODE)

CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2017-12-03 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Sun Dec  3 10:29:12 UTC 2017

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: a9_mpsubr.S

Log Message:
Pull up following revision(s) (requested by skrll in ticket #1524):
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.52
Ensure CNTVOFF is 0 before dropping out of Hyp mode


To generate a diff of this commit:
cvs rdiff -u -r1.18.2.5 -r1.18.2.6 src/sys/arch/arm/cortex/a9_mpsubr.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2017-07-08 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Sat Jul  8 17:01:52 UTC 2017

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: a9_mpsubr.S

Log Message:
Pull up following revision(s) (requested by skrll in ticket #1444):
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.48
Make fp 0 on entry to idle_stack to ensure we mark that we're top of
stack


To generate a diff of this commit:
cvs rdiff -u -r1.18.2.4 -r1.18.2.5 src/sys/arch/arm/cortex/a9_mpsubr.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2017-07-08 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Sat Jul  8 17:01:52 UTC 2017

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: a9_mpsubr.S

Log Message:
Pull up following revision(s) (requested by skrll in ticket #1444):
sys/arch/arm/cortex/a9_mpsubr.S: revision 1.48
Make fp 0 on entry to idle_stack to ensure we mark that we're top of
stack


To generate a diff of this commit:
cvs rdiff -u -r1.18.2.4 -r1.18.2.5 src/sys/arch/arm/cortex/a9_mpsubr.S

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/a9_mpsubr.S
diff -u src/sys/arch/arm/cortex/a9_mpsubr.S:1.18.2.4 src/sys/arch/arm/cortex/a9_mpsubr.S:1.18.2.5
--- src/sys/arch/arm/cortex/a9_mpsubr.S:1.18.2.4	Fri Feb 26 22:52:53 2016
+++ src/sys/arch/arm/cortex/a9_mpsubr.S	Sat Jul  8 17:01:52 2017
@@ -1,4 +1,4 @@
-/*	$NetBSD: a9_mpsubr.S,v 1.18.2.4 2016/02/26 22:52:53 snj Exp $	*/
+/*	$NetBSD: a9_mpsubr.S,v 1.18.2.5 2017/07/08 17:01:52 snj Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -736,6 +736,7 @@ cortex_mpcontinuation:
 	movw	r2, #:lower16:MD_CPU_HATCH	// pass md_cpu_hatch
 	movt	r2, #:upper16:MD_CPU_HATCH	// pass md_cpu_hatch
 	bl	_C_LABEL(cpu_hatch)
+	mov	fp, #0// top stack frame
 	b	_C_LABEL(idle_loop)		// never to return
 ASEND(cortex_mpcontinuation)

CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2015-04-05 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Mon Apr  6 01:55:53 UTC 2015

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: gtmr.c

Log Message:
Pull up following revision(s) (requested by skrll in ticket #662):
sys/arch/arm/cortex/gtmr.c: revision 1.10-1.14
port-arm/49737: armgtmr0 timer broken
Use physical timer instead of virtual timer for timecounter. For platforms
that implement virtualization extensions, the CNTVOFF register defines a
virtual offset between the physical count and virtual count. Unfortunately,
the CNTVOFF register is only accessible in secure mode and the value is
per-CPU, so we may end up in a scenario where virtual count reads from
CPU A - B - A are not monotonic. No offset applied to physical timer,
so physical count reads are guaranteed to be monotonic.
--
Sprinkle some arm_isb() to force execution of the mcrr instructions to get
more accurate values.  (Given that the generic timer is usually running at
a 64th or less of the cpu clock, this only settle to a tick or so.)
--
Move isb's to before reading count.  Change interrupt to level.
--
Trailing whitespace.
--
Whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.8.2.1 -r1.8.2.2 src/sys/arch/arm/cortex/gtmr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gtmr.c
diff -u src/sys/arch/arm/cortex/gtmr.c:1.8.2.1 src/sys/arch/arm/cortex/gtmr.c:1.8.2.2
--- src/sys/arch/arm/cortex/gtmr.c:1.8.2.1	Wed Mar 11 20:22:55 2015
+++ src/sys/arch/arm/cortex/gtmr.c	Mon Apr  6 01:55:53 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: gtmr.c,v 1.8.2.1 2015/03/11 20:22:55 snj Exp $	*/
+/*	$NetBSD: gtmr.c,v 1.8.2.2 2015/04/06 01:55:53 snj Exp $	*/
 
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: gtmr.c,v 1.8.2.1 2015/03/11 20:22:55 snj Exp $);
+__KERNEL_RCSID(0, $NetBSD: gtmr.c,v 1.8.2.2 2015/04/06 01:55:53 snj Exp $);
 
 #include sys/param.h
 #include sys/bus.h
@@ -44,6 +44,8 @@ __KERNEL_RCSID(0, $NetBSD: gtmr.c,v 1.8
 
 #include prop/proplib.h
 
+#include arm/locore.h
+
 #include arm/cortex/gtmr_var.h
 
 #include arm/cortex/mpcore_var.h
@@ -94,14 +96,14 @@ static void
 gtmr_attach(device_t parent, device_t self, void *aux)
 {
 	struct mpcore_attach_args * const mpcaa = aux;
-struct gtmr_softc *sc = gtmr_sc;
+	struct gtmr_softc *sc = gtmr_sc;
 	prop_dictionary_t dict = device_properties(self);
 	char freqbuf[sizeof(X.XXX SHz)];
 
 	/*
 	 * This runs at a fixed frequency of 1 to 50MHz.
 	 */
-	prop_dictionary_get_uint32(dict, frequency, sc-sc_freq);
+	prop_dictionary_get_uint32(dict, frequency, sc-sc_freq);
 	KASSERT(sc-sc_freq != 0);
 
 	humanize_number(freqbuf, sizeof(freqbuf), sc-sc_freq, Hz, 1000);
@@ -112,7 +114,8 @@ gtmr_attach(device_t parent, device_t se
 	/*
 	 * Enable the virtual counter to be accessed from usermode.
 	 */
-	armreg_cntk_ctl_write(armreg_cntk_ctl_read() | ARM_CNTKCTL_PL0VCTEN);
+	armreg_cntk_ctl_write(armreg_cntk_ctl_read() |
+	ARM_CNTKCTL_PL0VCTEN | ARM_CNTKCTL_PL0PCTEN);
 
 	self-dv_private = sc;
 	sc-sc_dev = self;
@@ -125,7 +128,7 @@ gtmr_attach(device_t parent, device_t se
 	device_xname(self), missing interrupts);
 
 	sc-sc_global_ih = intr_establish(mpcaa-mpcaa_irq, IPL_CLOCK,
-	IST_EDGE | IST_MPSAFE, gtmr_intr, NULL);
+	IST_LEVEL | IST_MPSAFE, gtmr_intr, NULL);
 	if (sc-sc_global_ih == NULL)
 		panic(%s: unable to register timer interrupt, __func__);
 	aprint_normal_dev(self, interrupting on irq %d\n,
@@ -159,6 +162,7 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
 	 * enable timer and stop masking the timer.
 	 */
 	armreg_cntv_ctl_write(ARM_CNTCTL_ENABLE);
+	armreg_cntp_ctl_write(ARM_CNTCTL_ENABLE);
 #if 0
 	printf(%s: cntctl=%#x\n, __func__, armreg_cntv_ctl_read());
 #endif
@@ -166,6 +170,7 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
 	/*
 	 * Get now and update the compare timer.
 	 */
+	arm_isb();
 	ci-ci_lastintr = armreg_cntv_ct_read();
 	armreg_cntv_tval_write(sc-sc_autoinc);
 #if 0
@@ -182,21 +187,24 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
 
 	s = splsched();
 
+	arm_isb();
 	uint64_t now64;
 	uint64_t start64 = armreg_cntv_ct_read();
 	do {
+		arm_isb();
 		now64 = armreg_cntv_ct_read();
 	} while (start64 == now64);
 	start64 = now64;
 	uint64_t end64 = start64 + 64;
 	uint32_t start32 = armreg_pmccntr_read();
 	do {
+		arm_isb();
 		now64 = armreg_cntv_ct_read();
 	} while (end64 != now64);
 	uint32_t end32 = armreg_pmccntr_read();
 
 	uint32_t diff32 = end64 - start64;
-	printf(%s: %s: %u cycles per tick\n, 
+	printf(%s: %s: %u cycles per tick\n,
 	__func__, ci-ci_data.cpu_name, (end32 - start32) / diff32);
 
 	printf(%s: %s: status %#x cmp %#PRIx64 now %#PRIx64\n,
@@ -204,7 +212,7 @@ gtmr_init_cpu_clock(struct cpu_info *ci)
 	armreg_cntv_cval_read(), armreg_cntv_ct_read());
 	splx(s);
 #elif 0
-	delay(100 / hz + 1000); 
+

CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2015-04-05 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Mon Apr  6 01:55:53 UTC 2015

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: gtmr.c

Log Message:
Pull up following revision(s) (requested by skrll in ticket #662):
sys/arch/arm/cortex/gtmr.c: revision 1.10-1.14
port-arm/49737: armgtmr0 timer broken
Use physical timer instead of virtual timer for timecounter. For platforms
that implement virtualization extensions, the CNTVOFF register defines a
virtual offset between the physical count and virtual count. Unfortunately,
the CNTVOFF register is only accessible in secure mode and the value is
per-CPU, so we may end up in a scenario where virtual count reads from
CPU A - B - A are not monotonic. No offset applied to physical timer,
so physical count reads are guaranteed to be monotonic.
--
Sprinkle some arm_isb() to force execution of the mcrr instructions to get
more accurate values.  (Given that the generic timer is usually running at
a 64th or less of the cpu clock, this only settle to a tick or so.)
--
Move isb's to before reading count.  Change interrupt to level.
--
Trailing whitespace.
--
Whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.8.2.1 -r1.8.2.2 src/sys/arch/arm/cortex/gtmr.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2015-03-21 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Sat Mar 21 17:24:20 UTC 2015

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: gic.c

Log Message:
Pull up following revision(s) (requested by skrll in ticket #627):
sys/arch/arm/cortex/gic.c: revision 1.16
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.10.2.3 -r1.10.2.4 src/sys/arch/arm/cortex/gic.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.10.2.3 src/sys/arch/arm/cortex/gic.c:1.10.2.4
--- src/sys/arch/arm/cortex/gic.c:1.10.2.3	Sun Mar 15 22:46:38 2015
+++ src/sys/arch/arm/cortex/gic.c	Sat Mar 21 17:24:19 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: gic.c,v 1.10.2.3 2015/03/15 22:46:38 snj Exp $	*/
+/*	$NetBSD: gic.c,v 1.10.2.4 2015/03/21 17:24:19 snj Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -34,7 +34,7 @@
 #define _INTR_PRIVATE
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: gic.c,v 1.10.2.3 2015/03/15 22:46:38 snj Exp $);
+__KERNEL_RCSID(0, $NetBSD: gic.c,v 1.10.2.4 2015/03/21 17:24:19 snj Exp $);
 
 #include sys/param.h
 #include sys/bus.h
@@ -270,7 +270,7 @@ armgic_irq_handler(void *tf)
 #if 0
 		const int ipl = armgic_priority_to_ipl(gicc_read(sc, GICC_RPR));
 		KASSERTMSG(panicstr != NULL || ipl == is-is_ipl,
-		%s: irq %d: running ipl %d != source ipl %u, 
+		%s: irq %d: running ipl %d != source ipl %u,
 		ci-ci_data.cpu_name, irq, ipl, is-is_ipl);
 #else
 		const int ipl = is-is_ipl;
@@ -332,7 +332,7 @@ armgic_establish_irq(struct pic_softc *p
 	irq %u: not valid (group[%zu]=0x%08x [0x%08x]),
 	is-is_irq, group, sc-sc_gic_valid_lines[group],
 	(uint32_t)__BIT(irq));
-	
+
 	KASSERTMSG(is-is_type == IST_LEVEL || is-is_type == IST_EDGE,
 	irq %u: type %u unsupported, is-is_irq, is-is_type);
 
@@ -342,7 +342,7 @@ armgic_establish_irq(struct pic_softc *p
 	uint32_t cfg = gicd_read(sc, cfg_reg);
 
 	if (group  0) {
-		/* 
+		/*
 		 * There are 4 irqs per TARGETS register.  For now bind
 		 * to the primary cpu.
 		 */
@@ -357,7 +357,7 @@ armgic_establish_irq(struct pic_softc *p
 		targets |= 1  byte_shift;
 		gicd_write(sc, targets_reg, targets);
 
-		/* 
+		/*
 		 * There are 16 irqs per CFG register.  10=EDGE 00=LEVEL
 		 */
 		uint32_t new_cfg = cfg;
@@ -384,7 +384,7 @@ armgic_establish_irq(struct pic_softc *p
 #endif
 	}
 
-	/* 
+	/*
 	 * There are 4 irqs per PRIORITY register.  Map the IPL
 	 * to GIC priority.
 	 */
@@ -436,7 +436,7 @@ static void
 armgic_cpu_init_targets(struct armgic_softc *sc)
 {
 	/*
-	 * Update the mpsafe targets 
+	 * Update the mpsafe targets
 	 */
 	for (size_t irq = 32; irq  sc-sc_pic.pic_maxsources; irq++) {
 		struct intrsource * const is = sc-sc_pic.pic_sources[irq];

CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2015-03-21 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Sat Mar 21 17:24:20 UTC 2015

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: gic.c

Log Message:
Pull up following revision(s) (requested by skrll in ticket #627):
sys/arch/arm/cortex/gic.c: revision 1.16
Trailing whitespace


To generate a diff of this commit:
cvs rdiff -u -r1.10.2.3 -r1.10.2.4 src/sys/arch/arm/cortex/gic.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2015-03-15 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Sun Mar 15 22:46:38 UTC 2015

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: gic.c

Log Message:
Pull up following revision(s) (requested by skrll in ticket #591):
sys/arch/arm/cortex/gic.c: revision 1.15
G/C armgic_last_priority


To generate a diff of this commit:
cvs rdiff -u -r1.10.2.2 -r1.10.2.3 src/sys/arch/arm/cortex/gic.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.10.2.2 src/sys/arch/arm/cortex/gic.c:1.10.2.3
--- src/sys/arch/arm/cortex/gic.c:1.10.2.2	Sat Mar  7 05:04:49 2015
+++ src/sys/arch/arm/cortex/gic.c	Sun Mar 15 22:46:38 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: gic.c,v 1.10.2.2 2015/03/07 05:04:49 snj Exp $	*/
+/*	$NetBSD: gic.c,v 1.10.2.3 2015/03/15 22:46:38 snj Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -34,7 +34,7 @@
 #define _INTR_PRIVATE
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: gic.c,v 1.10.2.2 2015/03/07 05:04:49 snj Exp $);
+__KERNEL_RCSID(0, $NetBSD: gic.c,v 1.10.2.3 2015/03/15 22:46:38 snj Exp $);
 
 #include sys/param.h
 #include sys/bus.h
@@ -181,8 +181,6 @@ armgic_block_irqs(struct pic_softc *pic,
 	gicd_write(sc, GICD_ICENABLERn(group), irq_mask);
 }
 
-static uint32_t armgic_last_priority;
-
 static void
 armgic_set_priority(struct pic_softc *pic, int ipl)
 {
@@ -190,7 +188,6 @@ armgic_set_priority(struct pic_softc *pi
 
 	const uint32_t priority = armgic_ipl_to_priority(ipl);
 	gicc_write(sc, GICC_PMR, priority);
-	armgic_last_priority = priority;
 }
 
 #ifdef __HAVE_PIC_FAST_SOFTINTS

CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2015-03-15 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Sun Mar 15 22:46:38 UTC 2015

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: gic.c

Log Message:
Pull up following revision(s) (requested by skrll in ticket #591):
sys/arch/arm/cortex/gic.c: revision 1.15
G/C armgic_last_priority


To generate a diff of this commit:
cvs rdiff -u -r1.10.2.2 -r1.10.2.3 src/sys/arch/arm/cortex/gic.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2015-03-06 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Sat Mar  7 05:04:49 UTC 2015

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: gic.c

Log Message:
Pull up following revision(s) (requested by jmcneill in ticket #567):
sys/arch/arm/cortex/gic.c: revision 1.13, 1.14
in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn
when setting irq type (IST_LEVEL/IST_EDGE)
--
sc_gic_lines is the total number of valid lines but pic_sources[] is
sparse; when initializing mpsafe targets make sure to go all the way to
the end (sc_pic.pic_maxsources) instead


To generate a diff of this commit:
cvs rdiff -u -r1.10.2.1 -r1.10.2.2 src/sys/arch/arm/cortex/gic.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: src/sys/arch/arm/cortex/gic.c
diff -u src/sys/arch/arm/cortex/gic.c:1.10.2.1 src/sys/arch/arm/cortex/gic.c:1.10.2.2
--- src/sys/arch/arm/cortex/gic.c:1.10.2.1	Sun Nov  9 16:05:25 2014
+++ src/sys/arch/arm/cortex/gic.c	Sat Mar  7 05:04:49 2015
@@ -1,4 +1,4 @@
-/*	$NetBSD: gic.c,v 1.10.2.1 2014/11/09 16:05:25 martin Exp $	*/
+/*	$NetBSD: gic.c,v 1.10.2.2 2015/03/07 05:04:49 snj Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -34,7 +34,7 @@
 #define _INTR_PRIVATE
 
 #include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: gic.c,v 1.10.2.1 2014/11/09 16:05:25 martin Exp $);
+__KERNEL_RCSID(0, $NetBSD: gic.c,v 1.10.2.2 2015/03/07 05:04:49 snj Exp $);
 
 #include sys/param.h
 #include sys/bus.h
@@ -371,7 +371,7 @@ armgic_establish_irq(struct pic_softc *p
 			new_cfg |= 2  twopair_shift;
 		}
 		if (new_cfg != cfg) {
-			gicd_write(sc, cfg_reg, cfg);
+			gicd_write(sc, cfg_reg, new_cfg);
 #if 0
 			printf(%s: irq %u: cfg changed from %#x to %#x\n,
 			pic-pic_name, is-is_irq, cfg, new_cfg);
@@ -441,7 +441,7 @@ armgic_cpu_init_targets(struct armgic_so
 	/*
 	 * Update the mpsafe targets 
 	 */
-	for (size_t irq = 32; irq  sc-sc_gic_lines; irq++) {
+	for (size_t irq = 32; irq  sc-sc_pic.pic_maxsources; irq++) {
 		struct intrsource * const is = sc-sc_pic.pic_sources[irq];
 		const bus_size_t targets_reg = GICD_ITARGETSRn(irq / 4);
 		if (is != NULL  is-is_mpsafe) {

CVS commit: [netbsd-7] src/sys/arch/arm/cortex

2015-03-06 Thread Soren Jacobsen 
Module Name:src
Committed By:   snj
Date:   Sat Mar  7 05:04:49 UTC 2015

Modified Files:
src/sys/arch/arm/cortex [netbsd-7]: gic.c

Log Message:
Pull up following revision(s) (requested by jmcneill in ticket #567):
sys/arch/arm/cortex/gic.c: revision 1.13, 1.14
in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn
when setting irq type (IST_LEVEL/IST_EDGE)
--
sc_gic_lines is the total number of valid lines but pic_sources[] is
sparse; when initializing mpsafe targets make sure to go all the way to
the end (sc_pic.pic_maxsources) instead


To generate a diff of this commit:
cvs rdiff -u -r1.10.2.1 -r1.10.2.2 src/sys/arch/arm/cortex/gic.c

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.