Re: [PATCH V2 1/2] SPI: MIPS: lantiq: add FALC-ON spi driver
On Fri, 9 Dec 2011 15:17:02 +0100, John Crispin blo...@openwrt.org wrote: The external bus unit (EBU) found on the FALC-ON SoC has spi emulation that is designed for serial flash access. This driver has only been tested with m25p80 type chips. The hardware has no support for other types of spi peripherals. Signed-off-by: Thomas Langer thomas.lan...@lantiq.com Signed-off-by: John Crispin blo...@openwrt.org Cc: spi-devel-general@lists.sourceforge.net --- These 2 patches should go upstream via the MIPS tree Acked-by: Grant Likely grant.lik...@secretlab.ca (If I haven't already acked this one) Changes in V2 * remove several superflous calls to dev_dbg * make use of module_platform_driver * remove falcon_spi_cleanup as it was an empty function * return real error codes instead of -1 * fixes operator spacing errors * split arch and driver specific patches * squash some lines to make use of the full 80 available chars * Kconfig is now alphabetic again * replace BUG() with WARN_ON() drivers/spi/Kconfig |9 + drivers/spi/Makefile |1 + drivers/spi/spi-falcon.c | 445 ++ 3 files changed, 455 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/spi-falcon.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1fd73d..e5ce95d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -138,6 +138,15 @@ config SPI_EP93XX This enables using the Cirrus EP93xx SPI controller in master mode. +config SPI_FALCON + tristate Falcon SPI controller support + depends on SOC_FALCON + help + The external bus unit (EBU) found on the FALC-ON SoC has SPI + emulation that is designed for serial flash access. This driver + has only been tested with m25p80 type chips. The hardware has no + support for other types of spi peripherals. + config SPI_GPIO tristate GPIO-based bitbanging SPI Master depends on GENERIC_GPIO diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 61c3261..570894c 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o +obj-$(CONFIG_SPI_FALCON) += spi-falcon.o obj-$(CONFIG_SPI_FSL_LIB)+= spi-fsl-lib.o obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o obj-$(CONFIG_SPI_FSL_SPI)+= spi-fsl-spi.o diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c new file mode 100644 index 000..7aa044d --- /dev/null +++ b/drivers/spi/spi-falcon.c @@ -0,0 +1,445 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 Thomas Langer thomas.lan...@lantiq.com + */ + +#include linux/module.h +#include linux/device.h +#include linux/platform_device.h +#include linux/spi/spi.h +#include linux/delay.h +#include linux/workqueue.h + +#include lantiq_soc.h + +#define DRV_NAME falcon_spi + +#define FALCON_SPI_XFER_BEGIN(1 0) +#define FALCON_SPI_XFER_END (1 1) + +/* Bus Read Configuration Register0 */ +#define LTQ_BUSRCON0 0x0010 +/* Bus Write Configuration Register0 */ +#define LTQ_BUSWCON0 0x0018 +/* Serial Flash Configuration Register */ +#define LTQ_SFCON0x0080 +/* Serial Flash Time Register */ +#define LTQ_SFTIME 0x0084 +/* Serial Flash Status Register */ +#define LTQ_SFSTAT 0x0088 +/* Serial Flash Command Register */ +#define LTQ_SFCMD0x008C +/* Serial Flash Address Register */ +#define LTQ_SFADDR 0x0090 +/* Serial Flash Data Register */ +#define LTQ_SFDATA 0x0094 +/* Serial Flash I/O Control Register */ +#define LTQ_SFIO 0x0098 +/* EBU Clock Control Register */ +#define LTQ_EBUCC0x00C4 + +/* Dummy Phase Length */ +#define SFCMD_DUMLEN_OFFSET 16 +#define SFCMD_DUMLEN_MASK0x000F +/* Chip Select */ +#define SFCMD_CS_OFFSET 24 +#define SFCMD_CS_MASK0x0700 +/* field offset */ +#define SFCMD_ALEN_OFFSET20 +#define SFCMD_ALEN_MASK 0x0070 +/* SCK Rise-edge Position */ +#define SFTIME_SCKR_POS_OFFSET 8 +#define SFTIME_SCKR_POS_MASK 0x0F00 +/* SCK Period */ +#define SFTIME_SCK_PER_OFFSET0 +#define SFTIME_SCK_PER_MASK 0x000F +/* SCK Fall-edge Position */ +#define SFTIME_SCKF_POS_OFFSET 12 +#define SFTIME_SCKF_POS_MASK 0xF000 +/* Device Size */ +#define SFCON_DEV_SIZE_A23_0 0x0300 +#define SFCON_DEV_SIZE_MASK 0x0F00 +/* Read Data Position */ +#define SFTIME_RD_POS_MASK
[PATCH V2 1/2] SPI: MIPS: lantiq: add FALC-ON spi driver
The external bus unit (EBU) found on the FALC-ON SoC has spi emulation that is designed for serial flash access. This driver has only been tested with m25p80 type chips. The hardware has no support for other types of spi peripherals. Signed-off-by: Thomas Langer thomas.lan...@lantiq.com Signed-off-by: John Crispin blo...@openwrt.org Cc: spi-devel-general@lists.sourceforge.net --- These 2 patches should go upstream via the MIPS tree Changes in V2 * remove several superflous calls to dev_dbg * make use of module_platform_driver * remove falcon_spi_cleanup as it was an empty function * return real error codes instead of -1 * fixes operator spacing errors * split arch and driver specific patches * squash some lines to make use of the full 80 available chars * Kconfig is now alphabetic again * replace BUG() with WARN_ON() drivers/spi/Kconfig |9 + drivers/spi/Makefile |1 + drivers/spi/spi-falcon.c | 445 ++ 3 files changed, 455 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/spi-falcon.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1fd73d..e5ce95d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -138,6 +138,15 @@ config SPI_EP93XX This enables using the Cirrus EP93xx SPI controller in master mode. +config SPI_FALCON + tristate Falcon SPI controller support + depends on SOC_FALCON + help + The external bus unit (EBU) found on the FALC-ON SoC has SPI + emulation that is designed for serial flash access. This driver + has only been tested with m25p80 type chips. The hardware has no + support for other types of spi peripherals. + config SPI_GPIO tristate GPIO-based bitbanging SPI Master depends on GENERIC_GPIO diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 61c3261..570894c 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o +obj-$(CONFIG_SPI_FALCON) += spi-falcon.o obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c new file mode 100644 index 000..7aa044d --- /dev/null +++ b/drivers/spi/spi-falcon.c @@ -0,0 +1,445 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 Thomas Langer thomas.lan...@lantiq.com + */ + +#include linux/module.h +#include linux/device.h +#include linux/platform_device.h +#include linux/spi/spi.h +#include linux/delay.h +#include linux/workqueue.h + +#include lantiq_soc.h + +#define DRV_NAME falcon_spi + +#define FALCON_SPI_XFER_BEGIN (1 0) +#define FALCON_SPI_XFER_END(1 1) + +/* Bus Read Configuration Register0 */ +#define LTQ_BUSRCON0 0x0010 +/* Bus Write Configuration Register0 */ +#define LTQ_BUSWCON0 0x0018 +/* Serial Flash Configuration Register */ +#define LTQ_SFCON 0x0080 +/* Serial Flash Time Register */ +#define LTQ_SFTIME 0x0084 +/* Serial Flash Status Register */ +#define LTQ_SFSTAT 0x0088 +/* Serial Flash Command Register */ +#define LTQ_SFCMD 0x008C +/* Serial Flash Address Register */ +#define LTQ_SFADDR 0x0090 +/* Serial Flash Data Register */ +#define LTQ_SFDATA 0x0094 +/* Serial Flash I/O Control Register */ +#define LTQ_SFIO 0x0098 +/* EBU Clock Control Register */ +#define LTQ_EBUCC 0x00C4 + +/* Dummy Phase Length */ +#define SFCMD_DUMLEN_OFFSET16 +#define SFCMD_DUMLEN_MASK 0x000F +/* Chip Select */ +#define SFCMD_CS_OFFSET24 +#define SFCMD_CS_MASK 0x0700 +/* field offset */ +#define SFCMD_ALEN_OFFSET 20 +#define SFCMD_ALEN_MASK0x0070 +/* SCK Rise-edge Position */ +#define SFTIME_SCKR_POS_OFFSET 8 +#define SFTIME_SCKR_POS_MASK 0x0F00 +/* SCK Period */ +#define SFTIME_SCK_PER_OFFSET 0 +#define SFTIME_SCK_PER_MASK0x000F +/* SCK Fall-edge Position */ +#define SFTIME_SCKF_POS_OFFSET 12 +#define SFTIME_SCKF_POS_MASK 0xF000 +/* Device Size */ +#define SFCON_DEV_SIZE_A23_0 0x0300 +#define SFCON_DEV_SIZE_MASK0x0F00 +/* Read Data Position */ +#define SFTIME_RD_POS_MASK 0x000F +/* Data Output */ +#define SFIO_UNUSED_WD_MASK0x000F +/* Command Opcode mask */ +#define SFCMD_OPC_MASK 0x00FF +/* dlen bytes of data to write */ +#define SFCMD_DIR_WRITE0x0100 +/* Data
