Re: svn commit: r266083 - in head/sys/arm: arm include
On 17 Jun 2014, at 21:05, Mark R V Murray wrote: > > On 17 Jun 2014, at 19:58, Michael Tuexen wrote: >> So you want something like: > > Yup! Looks good! :-) > > If you want to blame me for reviewing this, thats fine, but I’ve not run it > (I’m waiting for a replacement RPI, still). OK, I'll commit it. How do you want to deal with your change in cpu.h? Will you commit it? > > Please don’t be offended if a follow-up commit of mine rearranges this > slightly! (It won’t be for a week or two). Not at all... Best regards Michael > > M > -- > Mark R V Murray > > ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 17 Jun 2014, at 19:58, Michael Tuexen wrote: > So you want something like: Yup! Looks good! :-) If you want to blame me for reviewing this, thats fine, but I’ve not run it (I’m waiting for a replacement RPI, still). Please don’t be offended if a follow-up commit of mine rearranges this slightly! (It won’t be for a week or two). M -- Mark R V Murray ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 17 Jun 2014, at 20:33, Mark R V Murray wrote:
> Hi Michael,
>
> If that works, then Brilliant! :-) :-)
>
> Could you please fix this so the _PMC_USER_READ_WRITE_ is all in one place
> (it’s too dangerous to split up), and put an architecture-specific #ifdef
> around just the MCR instruction we care about.
So you want something like:
Index: cpufunc.c
===
--- cpufunc.c (revision 267575)
+++ cpufunc.c (working copy)
@@ -1410,12 +1410,27 @@
* you want!
*/
#ifdef _PMC_USER_READ_WRITE_
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+ /* Use the Secure User and Non-secure Access Validation Control Register
+* to allow userland access
+*/
+ __asm volatile ("mcrp15, 0, %0, c15, c9, 0\n\t"
+ :
+ : "r"(0x0001));
+#else
/* Set PMUSERENR[0] to allow userland access */
__asm volatile ("mcrp15, 0, %0, c9, c14, 0\n\t"
:
: "r"(0x0001));
#endif
-/* Set up the PMCCNTR register as a cyclecounter:
+#endif
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+ /* Set PMCR[2,0] to enable counters and reset CCNT */
+ __asm volatile ("mcrp15, 0, %0, c15, c12, 0\n\t"
+ :
+ : "r"(0x0005));
+#else
+ /* Set up the PMCCNTR register as a cyclecounter:
* Set PMINTENCLR to 0x to block interrupts
* Set PMCR[2,0] to enable counters and reset CCNT
* Set PMCNTENSET to 0x8000 to enable CCNT */
@@ -1426,6 +1441,7 @@
: "r"(0x),
"r"(0x0005),
"r"(0x8000));
+#endif
}
#endif
>
> With that, its good to commit, I’d say. I’ll likely follow up and exclude the
> architectures that are unproven.
You can commit this and your patch to include/cpu.h. I think it would be good to
have both fixes in one commit...
Best regards
Michael
>
> M
>
> On 17 Jun 2014, at 10:52, Michael Tuexen wrote:
>
>> On 16 Jun 2014, at 22:13, Mark R V Murray wrote:
>> Hi Mark,
>>
>> I just adopted the comments to the code change. So here is the improved
>> patch:
>>
>> Index: cpufunc.c
>> ===
>> --- cpufunc.c(revision 267575)
>> +++ cpufunc.c(working copy)
>> @@ -1404,18 +1404,36 @@
>> static __inline void
>> cpu_scc_setup_ccnt(void)
>> {
>> -/* This is how you give userland access to the CCNT and PMCn
>> - * registers.
>> - * BEWARE! This gives write access also, which may not be what
>> - * you want!
>> - */
>> +#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
>> #ifdef _PMC_USER_READ_WRITE_
>> -/* Set PMUSERENR[0] to allow userland access */
>> +/* This is how you give userland access to the CCNT and PMCn
>> + * registers.
>> + * BEWARE! This gives write access also, which may not be what
>> + * you want!
>> + * Use the Secure User and Non-secure Access Validation Control Register
>> + * to allow userland access
>> + */
>> +__asm volatile ("mcrp15, 0, %0, c15, c9, 0\n\t"
>> +:
>> +: "r"(0x0001));
>> +#endif
>> +/* Set PMCR[2,0] to enable counters and reset CCNT */
>> +__asm volatile ("mcrp15, 0, %0, c15, c12, 0\n\t"
>> +:
>> +: "r"(0x0005));
>> +#else
>> +#ifdef _PMC_USER_READ_WRITE_
>> +/* This is how you give userland access to the CCNT and PMCn
>> + * registers.
>> + * BEWARE! This gives write access also, which may not be what
>> + * you want!
>> + * Set PMUSERENR[0] to allow userland access
>> + */
>> __asm volatile ("mcrp15, 0, %0, c9, c14, 0\n\t"
>> :
>> : "r"(0x0001));
>> #endif
>> -/* Set up the PMCCNTR register as a cyclecounter:
>> +/* Set up the PMCCNTR register as a cyclecounter:
>> * Set PMINTENCLR to 0x to block interrupts
>> * Set PMCR[2,0] to enable counters and reset CCNT
>> * Set PMCNTENSET to 0x8000 to enable CCNT */
>> @@ -1426,6 +1444,7 @@
>> : "r"(0x),
>>"r"(0x0005),
>>"r"(0x8000));
>> +#endif
>> }
>> #endif
>>
>> Let me know if I can help.
>>
>> Best regards
>> Michael
>>>
>>> On 16 Jun 2014, at 20:38, Michael Tuexen wrote:
Hmm, the documentation reads
>>>
>>> Which docs are you using?
>>>
>>> I’m using DDI0360F. (And that could easily be a wrong choice).
>>>
>>> M
>>> --
>>> Mark R V Murray
>>>
>>>
>>
>
> --
> Mark R V Murray
>
>
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Re: svn commit: r266083 - in head/sys/arm: arm include
Hi Michael,
If that works, then Brilliant! :-) :-)
Could you please fix this so the _PMC_USER_READ_WRITE_ is all in one place
(it’s too dangerous to split up), and put an architecture-specific #ifdef
around just the MCR instruction we care about.
With that, its good to commit, I’d say. I’ll likely follow up and exclude the
architectures that are unproven.
M
On 17 Jun 2014, at 10:52, Michael Tuexen wrote:
> On 16 Jun 2014, at 22:13, Mark R V Murray wrote:
> Hi Mark,
>
> I just adopted the comments to the code change. So here is the improved patch:
>
> Index: cpufunc.c
> ===
> --- cpufunc.c (revision 267575)
> +++ cpufunc.c (working copy)
> @@ -1404,18 +1404,36 @@
> static __inline void
> cpu_scc_setup_ccnt(void)
> {
> -/* This is how you give userland access to the CCNT and PMCn
> - * registers.
> - * BEWARE! This gives write access also, which may not be what
> - * you want!
> - */
> +#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
> #ifdef _PMC_USER_READ_WRITE_
> - /* Set PMUSERENR[0] to allow userland access */
> + /* This is how you give userland access to the CCNT and PMCn
> + * registers.
> + * BEWARE! This gives write access also, which may not be what
> + * you want!
> + * Use the Secure User and Non-secure Access Validation Control Register
> + * to allow userland access
> + */
> + __asm volatile ("mcrp15, 0, %0, c15, c9, 0\n\t"
> + :
> + : "r"(0x0001));
> +#endif
> + /* Set PMCR[2,0] to enable counters and reset CCNT */
> + __asm volatile ("mcrp15, 0, %0, c15, c12, 0\n\t"
> + :
> + : "r"(0x0005));
> +#else
> +#ifdef _PMC_USER_READ_WRITE_
> + /* This is how you give userland access to the CCNT and PMCn
> + * registers.
> + * BEWARE! This gives write access also, which may not be what
> + * you want!
> + * Set PMUSERENR[0] to allow userland access
> + */
> __asm volatile ("mcrp15, 0, %0, c9, c14, 0\n\t"
> :
> : "r"(0x0001));
> #endif
> -/* Set up the PMCCNTR register as a cyclecounter:
> + /* Set up the PMCCNTR register as a cyclecounter:
>* Set PMINTENCLR to 0x to block interrupts
>* Set PMCR[2,0] to enable counters and reset CCNT
>* Set PMCNTENSET to 0x8000 to enable CCNT */
> @@ -1426,6 +1444,7 @@
> : "r"(0x),
> "r"(0x0005),
> "r"(0x8000));
> +#endif
> }
> #endif
>
> Let me know if I can help.
>
> Best regards
> Michael
>>
>> On 16 Jun 2014, at 20:38, Michael Tuexen wrote:
>>> Hmm, the documentation reads
>>
>> Which docs are you using?
>>
>> I’m using DDI0360F. (And that could easily be a wrong choice).
>>
>> M
>> --
>> Mark R V Murray
>>
>>
>
--
Mark R V Murray
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Re: svn commit: r266083 - in head/sys/arm: arm include
On 16 Jun 2014, at 22:13, Mark R V Murray wrote:
Hi Mark,
I just adopted the comments to the code change. So here is the improved patch:
Index: cpufunc.c
===
--- cpufunc.c (revision 267575)
+++ cpufunc.c (working copy)
@@ -1404,18 +1404,36 @@
static __inline void
cpu_scc_setup_ccnt(void)
{
-/* This is how you give userland access to the CCNT and PMCn
- * registers.
- * BEWARE! This gives write access also, which may not be what
- * you want!
- */
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
#ifdef _PMC_USER_READ_WRITE_
- /* Set PMUSERENR[0] to allow userland access */
+ /* This is how you give userland access to the CCNT and PMCn
+* registers.
+* BEWARE! This gives write access also, which may not be what
+* you want!
+* Use the Secure User and Non-secure Access Validation Control Register
+* to allow userland access
+*/
+ __asm volatile ("mcrp15, 0, %0, c15, c9, 0\n\t"
+ :
+ : "r"(0x0001));
+#endif
+ /* Set PMCR[2,0] to enable counters and reset CCNT */
+ __asm volatile ("mcrp15, 0, %0, c15, c12, 0\n\t"
+ :
+ : "r"(0x0005));
+#else
+#ifdef _PMC_USER_READ_WRITE_
+ /* This is how you give userland access to the CCNT and PMCn
+* registers.
+* BEWARE! This gives write access also, which may not be what
+* you want!
+* Set PMUSERENR[0] to allow userland access
+*/
__asm volatile ("mcrp15, 0, %0, c9, c14, 0\n\t"
:
: "r"(0x0001));
#endif
-/* Set up the PMCCNTR register as a cyclecounter:
+ /* Set up the PMCCNTR register as a cyclecounter:
* Set PMINTENCLR to 0x to block interrupts
* Set PMCR[2,0] to enable counters and reset CCNT
* Set PMCNTENSET to 0x8000 to enable CCNT */
@@ -1426,6 +1444,7 @@
: "r"(0x),
"r"(0x0005),
"r"(0x8000));
+#endif
}
#endif
Let me know if I can help.
Best regards
Michael
>
> On 16 Jun 2014, at 20:38, Michael Tuexen wrote:
>> Hmm, the documentation reads
>
> Which docs are you using?
>
> I’m using DDI0360F. (And that could easily be a wrong choice).
>
> M
> --
> Mark R V Murray
>
>
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Re: svn commit: r266083 - in head/sys/arm: arm include
On 16 Jun 2014, at 22:41, Michael Tuexen wrote:
>
> On 16 Jun 2014, at 22:13, Mark R V Murray wrote:
>
>>
>> On 16 Jun 2014, at 20:38, Michael Tuexen wrote:
>>> Hmm, the documentation reads
>>
>> Which docs are you using?
>>
>> I’m using DDI0360F. (And that could easily be a wrong choice).
> That is what I'm also looking at. Selecting ARM1176...
>
> The code regarding _PMC_USER_READ_WRITE_ also needs to be adopted.
> I need to test it... I'll come back in a couple of hours...
Using the following updated patch in addition to your patch:
Index: cpufunc.c
===
--- cpufunc.c (revision 267555)
+++ cpufunc.c (working copy)
@@ -1409,7 +1409,20 @@
* BEWARE! This gives write access also, which may not be what
* you want!
*/
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
#ifdef _PMC_USER_READ_WRITE_
+ /* Use Secure User and Non-secure Access Validation Control Register
+ to allow userland access */
+ __asm volatile ("mcrp15, 0, %0, c15, c9, 0\n\t"
+ :
+ : "r"(0x0001));
+#endif
+ /* Set PMCR[2,0] to enable counters and reset CCNT */
+ __asm volatile ("mcrp15, 0, %0, c15, c12, 0\n\t"
+ :
+ : "r"(0x0005));
+#else
+#ifdef _PMC_USER_READ_WRITE_
/* Set PMUSERENR[0] to allow userland access */
__asm volatile ("mcrp15, 0, %0, c9, c14, 0\n\t"
:
@@ -1426,6 +1439,7 @@
: "r"(0x),
"r"(0x0005),
"r"(0x8000));
+#endif
}
#endif
allows your test program to run successfully without root privileges, if I
compile the
kernel with _PMC_USER_READ_WRITE_ defined.
Best regards
Michael
>
> Best regards
> Michael
>>
>> M
>> --
>> Mark R V Murray
>>
>>
>
>
>
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Re: svn commit: r266083 - in head/sys/arm: arm include
On 16 Jun 2014, at 22:13, Mark R V Murray wrote: > > On 16 Jun 2014, at 20:38, Michael Tuexen wrote: >> Hmm, the documentation reads > > Which docs are you using? > > I’m using DDI0360F. (And that could easily be a wrong choice). That is what I'm also looking at. Selecting ARM1176... The code regarding _PMC_USER_READ_WRITE_ also needs to be adopted. I need to test it... I'll come back in a couple of hours... Best regards Michael > > M > -- > Mark R V Murray > > ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 16 Jun 2014, at 20:38, Michael Tuexen wrote: > Hmm, the documentation reads Which docs are you using? I’m using DDI0360F. (And that could easily be a wrong choice). M -- Mark R V Murray ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 16 Jun 2014, at 21:29, Mark R V Murray wrote: > > On 16 Jun 2014, at 20:25, Michael Tuexen wrote: >>> Should print a whole lotta numbers, incrementing, unless you hit the >>> wraparound. >> Don't I need to compile a kernel with _PMC_USER_READ_WRITE_ being defined, >> since >> without it a user process can't access the register. When running it on a >> kernel >> not defining _PMC_USER_READ_WRITE_, I get a core with Illegal instruction. > > No. That only enables _write_ access. That’s on ARMv7. What’s in ARMv6 may > also work. Hmm, the documentation reads Access to the Cycle Counter Register in User mode depends on the V bit, see c15, Secure User and Non-secure Access Validation Control Register. The Cycle Counter Register is always accessible in Privileged modes. Table 3.139 lists the results of attempted access for each mode. and the table shows read/write access for Secure Privileged and Non-secure Privileged, but for User you need the V-bit. So in which modes are the user programs running? One the normal kernel I get the Illegal Instruction error when I run the program. Best regards Michael > >> Let me build a kernel with the above define and retest. > > Please try without it. > > M > -- > Mark R V Murray > > ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 16 Jun 2014, at 20:25, Michael Tuexen wrote: >> Should print a whole lotta numbers, incrementing, unless you hit the >> wraparound. > Don't I need to compile a kernel with _PMC_USER_READ_WRITE_ being defined, > since > without it a user process can't access the register. When running it on a > kernel > not defining _PMC_USER_READ_WRITE_, I get a core with Illegal instruction. No. That only enables _write_ access. That’s on ARMv7. What’s in ARMv6 may also work. > Let me build a kernel with the above define and retest. Please try without it. M -- Mark R V Murray ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 16 Jun 2014, at 19:36, Mark R V Murray wrote:
>
> On 16 Jun 2014, at 08:28, Michael Tuexen wrote:
>> your patch for accessing the value is correct. However, the initialisation
>> code also
>> needs to be adopted to the platform. So in addition to your patch, you also
>> need:
>
> Thanks!
>
>> Is there an easy test to see if the code actually works as expected and not
>> that it just
>> allows the system to boot?
>
> Yes. :-)
>
> #include
>
> #include
>
> static __inline uint64_t
> get_cyclecount(void)
> {
> uint32_t ccnt;
> uint64_t tsc;
>
> /* Read CCNT. */
> __asm __volatile("mrc p15, 0, %0, c15, c12, 1": "=r" (ccnt));
>
> tsc = (uint64_t)ccnt;
>
> return (tsc);
> }
>
> #define N 10
>
> int
> main(int argc, char *argv[])
> {
> int i;
> uint64_t ccnt[N];
>
> for (i = 0; i < N; i++)
> ccnt[i] = get_cyclecount();
>
> for (i = 1; i < N; i++)
> printf("%6d %016llX %16llu\n", i, ccnt[i], ccnt[i] - ccnt[i -
> 1]);
>
>
> return (0);
> }
>
> Should print a whole lotta numbers, incrementing, unless you hit the
> wraparound.
Don't I need to compile a kernel with _PMC_USER_READ_WRITE_ being defined, since
without it a user process can't access the register. When running it on a kernel
not defining _PMC_USER_READ_WRITE_, I get a core with Illegal instruction.
Let me build a kernel with the above define and retest.
>
>> Regarding the 32-bit limitation: Do we want to increment the register only
>> every
>> 64 clock cycle?
>
> Definitely not! The value is in the low bits; wrap is of little consequence.
OK.
Best regards
Michael
>
> M
> --
> Mark R V Murray
>
>
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Re: svn commit: r266083 - in head/sys/arm: arm include
On 16 Jun 2014, at 08:28, Michael Tuexen wrote:
> your patch for accessing the value is correct. However, the initialisation
> code also
> needs to be adopted to the platform. So in addition to your patch, you also
> need:
Thanks!
> Is there an easy test to see if the code actually works as expected and not
> that it just
> allows the system to boot?
Yes. :-)
#include
#include
static __inline uint64_t
get_cyclecount(void)
{
uint32_t ccnt;
uint64_t tsc;
/* Read CCNT. */
__asm __volatile("mrc p15, 0, %0, c15, c12, 1": "=r" (ccnt));
tsc = (uint64_t)ccnt;
return (tsc);
}
#define N 10
int
main(int argc, char *argv[])
{
int i;
uint64_t ccnt[N];
for (i = 0; i < N; i++)
ccnt[i] = get_cyclecount();
for (i = 1; i < N; i++)
printf("%6d %016llX %16llu\n", i, ccnt[i], ccnt[i] - ccnt[i -
1]);
return (0);
}
Should print a whole lotta numbers, incrementing, unless you hit the wraparound.
> Regarding the 32-bit limitation: Do we want to increment the register only
> every
> 64 clock cycle?
Definitely not! The value is in the low bits; wrap is of little consequence.
M
--
Mark R V Murray
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Re: svn commit: r266083 - in head/sys/arm: arm include
On 15 Jun 2014, at 17:13, Mark R V Murray wrote:
>
> On 30 May 2014, at 09:42, Michael Tuexen wrote:
>
>> On 29 May 2014, at 21:21, Mark R V Murray wrote:
>>
>>>
>>> On 29 May 2014, at 19:27, Michael Tuexen wrote:
>>>
On 29 May 2014, at 20:15, Mark R V Murray wrote:
>
> On 29 May 2014, at 19:13, Michael Tuexen wrote:
>
>>> I can make it work on RPI, but trying to find what else it will/won’t
>>> work on is more problematic.
>> Wouldn't it require to use different registers on the RPI? This would
>> mean you
>> would need more #ifdefs…
>
> Thats the problem; too many #ifdefs.
So you could just keep the code for now, but reduce the #ifdefs to the
ones you
know that work. Later on, you can replace it by the driver stuff…
>>>
>>> That’s what I was thinking, yes.
>> Great. Let me know if you need testing support on the RPI…
>
> I’ve come to the conclusion that my RPI-B is hosed. It doesn’t even boot
> Raspian properly. Sorry about how long this has taken.
>
> Please could someone with a working RPI please check that the following patch
> works (may need to apply by hand due to cut/paste).
Hi Mark,
your patch for accessing the value is correct. However, the initialisation code
also
needs to be adopted to the platform. So in addition to your patch, you also
need:
Index: arm/cpufunc.c
===
--- arm/cpufunc.c (revision 267519)
+++ arm/cpufunc.c (working copy)
@@ -1415,6 +1415,12 @@
:
: "r"(0x0001));
#endif
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+ /* Set PMCR[2,0] to enable counters and reset CCNT */
+ __asm volatile ("mcrp15, 0, %0, c15, c12, 0\n\t"
+ :
+ : "r"(0x0005));
+#else
/* Set up the PMCCNTR register as a cyclecounter:
* Set PMINTENCLR to 0x to block interrupts
* Set PMCR[2,0] to enable counters and reset CCNT
@@ -1426,6 +1432,7 @@
: "r"(0x),
"r"(0x0005),
"r"(0x8000));
+#endif
}
#endif
With both patches, the RPI boots up fine with r267519
Is there an easy test to see if the code actually works as expected and not
that it just
allows the system to boot?
Regarding the 32-bit limitation: Do we want to increment the register only every
64 clock cycle?
Best regards
Michael
>
> Thanks, with repeated apologies.
>
> M
> --
> Mark R V Murray
>
> --- include/cpu.h (revision 267507)
> +++ include/cpu.h (working copy)
> @@ -25,7 +25,16 @@
>* Read PMCCNTR. Curses! Its only 32 bits.
>* TODO: Fix this by catching overflow with interrupt?
>*/
> +/* The ARMv6 vs ARMv7 divide is going to need a better way of
> + * distinguishing between them.
> + */
> +#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
> + /* ARMv6 - Earlier model SCCs */
> + __asm __volatile("mrc p15, 0, %0, c15, c12, 1": "=r" (ccnt));
> +#else
> + /* ARMv7 - Later model SCCs */
> __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
> +#endif
> ccnt64 = (uint64_t)ccnt;
> return (ccnt64);
> #else /* No performance counters, so use binuptime(9). This is slow */
>
>
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Re: svn commit: r266083 - in head/sys/arm: arm include
On 15 Jun 2014, at 17:13, Mark R V Murray wrote:
>
> On 30 May 2014, at 09:42, Michael Tuexen wrote:
>
>> On 29 May 2014, at 21:21, Mark R V Murray wrote:
>>
>>>
>>> On 29 May 2014, at 19:27, Michael Tuexen wrote:
>>>
On 29 May 2014, at 20:15, Mark R V Murray wrote:
>
> On 29 May 2014, at 19:13, Michael Tuexen wrote:
>
>>> I can make it work on RPI, but trying to find what else it will/won’t
>>> work on is more problematic.
>> Wouldn't it require to use different registers on the RPI? This would
>> mean you
>> would need more #ifdefs…
>
> Thats the problem; too many #ifdefs.
So you could just keep the code for now, but reduce the #ifdefs to the
ones you
know that work. Later on, you can replace it by the driver stuff…
>>>
>>> That’s what I was thinking, yes.
>> Great. Let me know if you need testing support on the RPI…
>
> I’ve come to the conclusion that my RPI-B is hosed. It doesn’t even boot
> Raspian properly. Sorry about how long this has taken.
>
> Please could someone with a working RPI please check that the following patch
> works (may need to apply by hand due to cut/paste).
>
> Thanks, with repeated apologies.
I can test it and report if it works. It might take until tomorrow...
Thanks for working on a fix!
Best regards
Michael
>
> M
> --
> Mark R V Murray
>
> --- include/cpu.h (revision 267507)
> +++ include/cpu.h (working copy)
> @@ -25,7 +25,16 @@
>* Read PMCCNTR. Curses! Its only 32 bits.
>* TODO: Fix this by catching overflow with interrupt?
>*/
> +/* The ARMv6 vs ARMv7 divide is going to need a better way of
> + * distinguishing between them.
> + */
> +#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
> + /* ARMv6 - Earlier model SCCs */
> + __asm __volatile("mrc p15, 0, %0, c15, c12, 1": "=r" (ccnt));
> +#else
> + /* ARMv7 - Later model SCCs */
> __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
> +#endif
> ccnt64 = (uint64_t)ccnt;
> return (ccnt64);
> #else /* No performance counters, so use binuptime(9). This is slow */
>
>
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Re: svn commit: r266083 - in head/sys/arm: arm include
On 30 May 2014, at 09:42, Michael Tuexen wrote:
> On 29 May 2014, at 21:21, Mark R V Murray wrote:
>
>>
>> On 29 May 2014, at 19:27, Michael Tuexen wrote:
>>
>>> On 29 May 2014, at 20:15, Mark R V Murray wrote:
>>>
On 29 May 2014, at 19:13, Michael Tuexen wrote:
>> I can make it work on RPI, but trying to find what else it will/won’t
>> work on is more problematic.
> Wouldn't it require to use different registers on the RPI? This would
> mean you
> would need more #ifdefs…
Thats the problem; too many #ifdefs.
>>> So you could just keep the code for now, but reduce the #ifdefs to the ones
>>> you
>>> know that work. Later on, you can replace it by the driver stuff…
>>
>> That’s what I was thinking, yes.
> Great. Let me know if you need testing support on the RPI…
I’ve come to the conclusion that my RPI-B is hosed. It doesn’t even boot
Raspian properly. Sorry about how long this has taken.
Please could someone with a working RPI please check that the following patch
works (may need to apply by hand due to cut/paste).
Thanks, with repeated apologies.
M
--
Mark R V Murray
--- include/cpu.h (revision 267507)
+++ include/cpu.h (working copy)
@@ -25,7 +25,16 @@
* Read PMCCNTR. Curses! Its only 32 bits.
* TODO: Fix this by catching overflow with interrupt?
*/
+/* The ARMv6 vs ARMv7 divide is going to need a better way of
+ * distinguishing between them.
+ */
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
+ /* ARMv6 - Earlier model SCCs */
+ __asm __volatile("mrc p15, 0, %0, c15, c12, 1": "=r" (ccnt));
+#else
+ /* ARMv7 - Later model SCCs */
__asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
+#endif
ccnt64 = (uint64_t)ccnt;
return (ccnt64);
#else /* No performance counters, so use binuptime(9). This is slow */
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Re: svn commit: r266083 - in head/sys/arm: arm include
On 29 May 2014, at 21:21, Mark R V Murray wrote: > > On 29 May 2014, at 19:27, Michael Tuexen wrote: > >> On 29 May 2014, at 20:15, Mark R V Murray wrote: >> >>> >>> On 29 May 2014, at 19:13, Michael Tuexen wrote: >>> > I can make it work on RPI, but trying to find what else it will/won’t > work on is more problematic. Wouldn't it require to use different registers on the RPI? This would mean you would need more #ifdefs… >>> >>> Thats the problem; too many #ifdefs. >> So you could just keep the code for now, but reduce the #ifdefs to the ones >> you >> know that work. Later on, you can replace it by the driver stuff… > > That’s what I was thinking, yes. Great. Let me know if you need testing support on the RPI... Best regards Michael > > M > -- > Mark R V Murray > > ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 29 May 2014, at 19:27, Michael Tuexen wrote: > On 29 May 2014, at 20:15, Mark R V Murray wrote: > >> >> On 29 May 2014, at 19:13, Michael Tuexen wrote: >> I can make it work on RPI, but trying to find what else it will/won’t work on is more problematic. >>> Wouldn't it require to use different registers on the RPI? This would mean >>> you >>> would need more #ifdefs… >> >> Thats the problem; too many #ifdefs. > So you could just keep the code for now, but reduce the #ifdefs to the ones > you > know that work. Later on, you can replace it by the driver stuff… That’s what I was thinking, yes. M -- Mark R V Murray ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 29 May 2014, at 20:15, Mark R V Murray wrote: > > On 29 May 2014, at 19:13, Michael Tuexen wrote: > >>> I can make it work on RPI, but trying to find what else it will/won’t work >>> on is more problematic. >> Wouldn't it require to use different registers on the RPI? This would mean >> you >> would need more #ifdefs… > > Thats the problem; too many #ifdefs. So you could just keep the code for now, but reduce the #ifdefs to the ones you know that work. Later on, you can replace it by the driver stuff... Best regards Michael > > M > -- > Mark R V Murray > > > ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 29 May 2014, at 19:13, Michael Tuexen wrote: >> I can make it work on RPI, but trying to find what else it will/won’t work >> on is more problematic. > Wouldn't it require to use different registers on the RPI? This would mean you > would need more #ifdefs… Thats the problem; too many #ifdefs. M -- Mark R V Murray ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 29 May 2014, at 19:41, Mark R V Murray wrote: > > On 29 May 2014, at 12:05, Hans Petter Selasky wrote: > >> On 05/22/14 09:09, Mark R V Murray wrote: >>> >>> On 21 May 2014, at 21:15, Hans Petter Selasky wrote: >>> On 05/14/14 21:11, Mark Murray wrote: > Author: markm > Date: Wed May 14 19:11:15 2014 > New Revision: 266083 > URL: http://svnweb.freebsd.org/changeset/base/266083 > > Log: > Give suitably-endowed ARMs a register similar to the x86 TSC register. > Hi, Regression issue: This commit prevents RPI-B from booting. >>> >>> Thanks, I’ll look at it ASAP. >>> >>> M >>> >> >> Any news on this issue? > > Hi > > Yes, thanks! > > I can make it work on RPI, but trying to find what else it will/won’t work on > is more problematic. Wouldn't it require to use different registers on the RPI? This would mean you would need more #ifdefs... I can test things on the RPI, but can't test on other platforms... Best regards Michael > > I’m considering disabling this on RPI, and then spending a bit of time > writing a full driver for this counter, then the annoying details of the > problem can be solved in FDT code. > > M > -- > Mark R V Murray > > > ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 29 May 2014, at 12:05, Hans Petter Selasky wrote: > On 05/22/14 09:09, Mark R V Murray wrote: >> >> On 21 May 2014, at 21:15, Hans Petter Selasky wrote: >> >>> On 05/14/14 21:11, Mark Murray wrote: Author: markm Date: Wed May 14 19:11:15 2014 New Revision: 266083 URL: http://svnweb.freebsd.org/changeset/base/266083 Log: Give suitably-endowed ARMs a register similar to the x86 TSC register. >>> >>> Hi, >>> >>> Regression issue: >>> This commit prevents RPI-B from booting. >> >> Thanks, I’ll look at it ASAP. >> >> M >> > > Any news on this issue? Hi Yes, thanks! I can make it work on RPI, but trying to find what else it will/won’t work on is more problematic. I’m considering disabling this on RPI, and then spending a bit of time writing a full driver for this counter, then the annoying details of the problem can be solved in FDT code. M -- Mark R V Murray ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 05/22/14 09:09, Mark R V Murray wrote: On 21 May 2014, at 21:15, Hans Petter Selasky wrote: On 05/14/14 21:11, Mark Murray wrote: Author: markm Date: Wed May 14 19:11:15 2014 New Revision: 266083 URL: http://svnweb.freebsd.org/changeset/base/266083 Log: Give suitably-endowed ARMs a register similar to the x86 TSC register. Hi, Regression issue: This commit prevents RPI-B from booting. Thanks, I’ll look at it ASAP. M Any news on this issue? --HPS ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 24 May 2014, at 23:02, Andrew Turner wrote:
> On Sat, 24 May 2014 21:09:56 +0200
> Michael Tuexen wrote:
>
>> On 22 May 2014, at 09:09, Mark R V Murray wrote:
>>
>>>
>>> On 21 May 2014, at 21:15, Hans Petter Selasky
>>> wrote:
>>>
On 05/14/14 21:11, Mark Murray wrote:
> Author: markm
> Date: Wed May 14 19:11:15 2014
> New Revision: 266083
> URL: http://svnweb.freebsd.org/changeset/base/266083
>
> Log:
> Give suitably-endowed ARMs a register similar to the x86 TSC
> register.
>
Hi,
Regression issue:
This commit prevents RPI-B from booting.
>>>
>>> Thanks, I’ll look at it ASAP.
>> Doesn't the ARM1176 use for example
>> MRC p15, 0, , c15, c12, 1; Read Cycle Counter Register
>> to read the value, whereas the
>> you use
>> __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
>
> On ARMv6 there is no guarantee of a cycle count register. On the
> ARM1176 there is one in an implementation defined section of the system
> control coprocessor. This is the c15 section above, and is accessible
> as shown.
>
> On ARMv7 there are optional performance monitor extensions. These are
> in parts of the c9 section of the coprocessor. As it is optional there
> is no requirement for implementers to include this functionality,
> however I would expect the ARM designs to include it, and most non-ARM
> designs are likely aiming for performance so will also include them.
>
> If the ARMv7 processor has the performance extensions the existing code
> appears correct to retrieve it.
The code is #ifdef as
#if defined(CPU_ARM1136) || defined(CPU_ARM1176) \
|| defined(CPU_MV_PJ4B) \
|| defined(CPU_CORTEXA) || defined(CPU_KRAIT)
Isn't the Raspberry Pi defining CPU_ARM1176 and using ARMv6? So can we use
the same code for all plattforms in the #ifdef?
Best regards
Michael
>
> Andrew
>
>
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Re: svn commit: r266083 - in head/sys/arm: arm include
On Sat, 24 May 2014 21:09:56 +0200
Michael Tuexen wrote:
> On 22 May 2014, at 09:09, Mark R V Murray wrote:
>
> >
> > On 21 May 2014, at 21:15, Hans Petter Selasky
> > wrote:
> >
> >> On 05/14/14 21:11, Mark Murray wrote:
> >>> Author: markm
> >>> Date: Wed May 14 19:11:15 2014
> >>> New Revision: 266083
> >>> URL: http://svnweb.freebsd.org/changeset/base/266083
> >>>
> >>> Log:
> >>> Give suitably-endowed ARMs a register similar to the x86 TSC
> >>> register.
> >>>
> >>
> >> Hi,
> >>
> >> Regression issue:
> >> This commit prevents RPI-B from booting.
> >
> > Thanks, I’ll look at it ASAP.
> Doesn't the ARM1176 use for example
> MRC p15, 0, , c15, c12, 1; Read Cycle Counter Register
> to read the value, whereas the
> you use
> __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
On ARMv6 there is no guarantee of a cycle count register. On the
ARM1176 there is one in an implementation defined section of the system
control coprocessor. This is the c15 section above, and is accessible
as shown.
On ARMv7 there are optional performance monitor extensions. These are
in parts of the c9 section of the coprocessor. As it is optional there
is no requirement for implementers to include this functionality,
however I would expect the ARM designs to include it, and most non-ARM
designs are likely aiming for performance so will also include them.
If the ARMv7 processor has the performance extensions the existing code
appears correct to retrieve it.
Andrew
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Re: svn commit: r266083 - in head/sys/arm: arm include
On 22 May 2014, at 09:09, Mark R V Murray wrote:
>
> On 21 May 2014, at 21:15, Hans Petter Selasky wrote:
>
>> On 05/14/14 21:11, Mark Murray wrote:
>>> Author: markm
>>> Date: Wed May 14 19:11:15 2014
>>> New Revision: 266083
>>> URL: http://svnweb.freebsd.org/changeset/base/266083
>>>
>>> Log:
>>> Give suitably-endowed ARMs a register similar to the x86 TSC register.
>>>
>>
>> Hi,
>>
>> Regression issue:
>> This commit prevents RPI-B from booting.
>
> Thanks, I’ll look at it ASAP.
Doesn't the ARM1176 use for example
MRC p15, 0, , c15, c12, 1; Read Cycle Counter Register
to read the value, whereas the
you use
__asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
Best regards
Michael
>
> M
> --
> Mark R V Murray
>
>
>
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Re: svn commit: r266083 - in head/sys/arm: arm include
On 21 May 2014, at 21:15, Hans Petter Selasky wrote: > On 05/14/14 21:11, Mark Murray wrote: >> Author: markm >> Date: Wed May 14 19:11:15 2014 >> New Revision: 266083 >> URL: http://svnweb.freebsd.org/changeset/base/266083 >> >> Log: >> Give suitably-endowed ARMs a register similar to the x86 TSC register. >> > > Hi, > > Regression issue: > This commit prevents RPI-B from booting. Thanks, I’ll look at it ASAP. M -- Mark R V Murray ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
Re: svn commit: r266083 - in head/sys/arm: arm include
On 05/14/14 21:11, Mark Murray wrote: Author: markm Date: Wed May 14 19:11:15 2014 New Revision: 266083 URL: http://svnweb.freebsd.org/changeset/base/266083 Log: Give suitably-endowed ARMs a register similar to the x86 TSC register. Hi, Regression issue: This commit prevents RPI-B from booting. --HPS ___ svn-src-head@freebsd.org mailing list http://lists.freebsd.org/mailman/listinfo/svn-src-head To unsubscribe, send any mail to "svn-src-head-unsubscr...@freebsd.org"
svn commit: r266083 - in head/sys/arm: arm include
Author: markm
Date: Wed May 14 19:11:15 2014
New Revision: 266083
URL: http://svnweb.freebsd.org/changeset/base/266083
Log:
Give suitably-endowed ARMs a register similar to the x86 TSC register.
Here, "suitably endowed" means that the System Control Coprocessor
(#15) has Performance Monitoring Registers, including a CCNT (Cycle
Count) register.
The CCNT register is used in a way similar to the TSC register in
x86 processors by the get_cyclecount(9) function. The entropy-harvesting
thread is a heavy user of this function, and will benefit from not
having to call binuptime(9) instead.
One problem with the CCNT register is that it is 32-bit only, so
the upper 32-bits of the returned number are always 0. The entropy
harvester does not care, but in case any one else does, follow-up
work may include an interrup trap to increment an upper-32-bit
counter on CCNT overflow.
Another problem is that the CCNT register is not readable in user-mode
code; in can be made readable by userland, but then it is also
writable, and so is a good chunk of the PMU system. For that reason,
the CCNT is not enabled for user-mode access in this commit.
Like the x86, there is one CCNT per core, so they don't all run in
perfect sync.
Reviewed by: ian@ (an earlier version)
Tested by:ian@ (same earlier version)
Committed from: WANDBOARD-QUAD
Modified:
head/sys/arm/arm/cpufunc.c
head/sys/arm/include/cpu.h
Modified: head/sys/arm/arm/cpufunc.c
==
--- head/sys/arm/arm/cpufunc.c Wed May 14 19:02:00 2014(r266082)
+++ head/sys/arm/arm/cpufunc.c Wed May 14 19:11:15 2014(r266083)
@@ -1398,6 +1398,37 @@ arm10_setup(args)
}
#endif /* CPU_ARM9E || CPU_ARM10 */
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176) \
+ || defined(CPU_MV_PJ4B) \
+ || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
+static __inline void
+cpu_scc_setup_ccnt(void)
+{
+/* This is how you give userland access to the CCNT and PMCn
+ * registers.
+ * BEWARE! This gives write access also, which may not be what
+ * you want!
+ */
+#ifdef _PMC_USER_READ_WRITE_
+ /* Set PMUSERENR[0] to allow userland access */
+ __asm volatile ("mcrp15, 0, %0, c9, c14, 0\n\t"
+ :
+ : "r"(0x0001));
+#endif
+/* Set up the PMCCNTR register as a cyclecounter:
+* Set PMINTENCLR to 0x to block interrupts
+* Set PMCR[2,0] to enable counters and reset CCNT
+* Set PMCNTENSET to 0x8000 to enable CCNT */
+ __asm volatile ("mcrp15, 0, %0, c9, c14, 2\n\t"
+ "mcrp15, 0, %1, c9, c12, 0\n\t"
+ "mcrp15, 0, %2, c9, c12, 1\n\t"
+ :
+ : "r"(0x),
+ "r"(0x0005),
+ "r"(0x8000));
+}
+#endif
+
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
struct cpu_option arm11_options[] = {
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE) },
@@ -1501,6 +1532,8 @@ arm11x6_setup(char *args)
/* And again. */
cpu_idcache_wbinv_all();
+
+ cpu_scc_setup_ccnt();
}
#endif /* CPU_ARM1136 || CPU_ARM1176 */
@@ -1535,6 +1568,8 @@ pj4bv7_setup(args)
/* And again. */
cpu_idcache_wbinv_all();
+
+ cpu_scc_setup_ccnt();
}
#endif /* CPU_MV_PJ4B */
@@ -1582,6 +1617,8 @@ cortexa_setup(char *args)
#ifdef SMP
armv7_auxctrl((1 << 6) | (1 << 0), (1 << 6) | (1 << 0)); /* Enable SMP
+ TLB broadcasting */
#endif
+
+ cpu_scc_setup_ccnt();
}
#endif /* CPU_CORTEXA */
Modified: head/sys/arm/include/cpu.h
==
--- head/sys/arm/include/cpu.h Wed May 14 19:02:00 2014(r266082)
+++ head/sys/arm/include/cpu.h Wed May 14 19:11:15 2014(r266083)
@@ -14,11 +14,26 @@ voidswi_vm(void *);
static __inline uint64_t
get_cyclecount(void)
{
+/* This '#if' asks the question 'Does CP15/SCC include performance counters?'
*/
+#if defined(CPU_ARM1136) || defined(CPU_ARM1176) \
+ || defined(CPU_MV_PJ4B) \
+ || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
+ uint32_t ccnt;
+ uint64_t ccnt64;
+
+ /*
+* Read PMCCNTR. Curses! Its only 32 bits.
+* TODO: Fix this by catching overflow with interrupt?
+*/
+ __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt));
+ ccnt64 = (uint64_t)ccnt;
+ return (ccnt64);
+#else /* No performance counters, so use binuptime(9). This is slow */
struct bintime bt;
binuptime(&bt);
return ((uint64_t)bt.sec << 56 | bt.frac >> 8);
-
+#endif
}
#endif
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