Re: [U-Boot] [PATCH 0/9]EXYNOS5: Support for Exynos5250 Rev 1.0
Hi Jaehoon Chung, Thank you for comments. On Thu, Jun 21, 2012 at 5:31 AM, Jaehoon Chung jh80.ch...@samsung.com wrote: Hi Rajeshwari, On 06/20/2012 07:40 PM, Rajeshwari Shinde wrote: This patch set adds support for Exynos5250 Rev 1.0. Exynos5250 Rev 1.0 supports DDR3 Memory configuration and support for LPDDR2 is removed. Exynos5250 Rev 1.0 supports DWMMC driver but the support for same is not yet gone into Mainline. After DWMMC driver is added to Mainline support for generic S5P MMC driver will be removed. Due to Support of generic S5P MMC driver currently still being there in the Mainline you can see the following error on boot. mmc_reset: timeout error mmc_change_clock: timeout error mmc_send_cmd: waiting for status update MMC init failed Is this error produced at exynos5, otherwise all samsung-soc? I didn't understand why explain mmc issue in these patch series.. EVT1 of SMDK5250 does not support SDHCI controller required for MMC and DWMMC is still to added to the mainline. Same can be verified from the user manual. Best Regards, Jaehoon Chung Best Regards, Rajeshwari Shinde. Rajeshwari Shinde (9): ARCH: SPL: Add parametric board initializer SMDK5250: SPL: Define parametric board initializer SMDK5250: Add smdk5250-uboot-spl.lds EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0 Exynos5: DDR3: Adding the DDR3 memory setup for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0 SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0 arch/arm/cpu/armv7/exynos/clock.c | 12 +- arch/arm/cpu/armv7/exynos/pinmux.c | 18 +- arch/arm/include/asm/arch-exynos/clock.h | 37 +- arch/arm/include/asm/arch-exynos/dmc.h | 65 +++ arch/arm/include/asm/arch-exynos/spl.h | 95 +++ board/samsung/smdk5250/Makefile | 3 +- board/samsung/smdk5250/clock_init.c | 714 +++ board/samsung/smdk5250/clock_init.h | 149 + board/samsung/smdk5250/dmc_common.c | 199 +++ board/samsung/smdk5250/dmc_init.c | 462 --- board/samsung/smdk5250/dmc_init_ddr3.c | 228 board/samsung/smdk5250/setup.h | 765 +++-- board/samsung/smdk5250/smdk5250-uboot-spl.lds | 66 +++ board/samsung/smdk5250/smdk5250.c | 6 +- board/samsung/smdk5250/smdk5250_spl.c | 68 +++ include/configs/smdk5250.h | 7 +- 16 files changed, 1968 insertions(+), 926 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/spl.h create mode 100644 board/samsung/smdk5250/clock_init.h create mode 100644 board/samsung/smdk5250/dmc_common.c delete mode 100644 board/samsung/smdk5250/dmc_init.c create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c create mode 100644 board/samsung/smdk5250/smdk5250-uboot-spl.lds create mode 100644 board/samsung/smdk5250/smdk5250_spl.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] fdt: Include arch specific gpio.h
Also include arch specific gpio.h which can contain gpio function implementation. Signed-off-by: Michal Simek mon...@monstr.eu CC: Simon Glass s...@chromium.org --- lib/fdtdec.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/lib/fdtdec.c b/lib/fdtdec.c index cc09e06..b12eb77 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -25,6 +25,7 @@ #include fdtdec.h /* we need the generic GPIO interface here */ +#include asm/gpio.h #include asm-generic/gpio.h DECLARE_GLOBAL_DATA_PTR; -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5] microblaze: Add gpio.h
Gpio support is not implemented yet. Adding it because of fdtdec.
Signed-off-by: Michal Simek mon...@monstr.eu
---
arch/microblaze/include/asm/gpio.h | 41
1 files changed, 41 insertions(+), 0 deletions(-)
create mode 100644 arch/microblaze/include/asm/gpio.h
diff --git a/arch/microblaze/include/asm/gpio.h
b/arch/microblaze/include/asm/gpio.h
new file mode 100644
index 000..883f4d4
--- /dev/null
+++ b/arch/microblaze/include/asm/gpio.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_MICROBLAZE_GPIO_H_
+#define _ASM_MICROBLAZE_GPIO_H_
+
+#include asm/io.h
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
+static inline int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+ return 0;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+ return 0;
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+ return 0;
+}
+
+static inline int gpio_set_value(unsigned gpio, int value)
+{
+ return 0;
+}
+
+static inline int gpio_is_valid(int number)
+{
+ return 0;
+}
+#endif
+
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] microblaze: Add support for device tree driven board configuration
This is minimum code required to be able to use device-tree
for u-boot initialization.
Currently only for device driver initialization.
Linker script change ensures DTB to be aligned
for both options CONFIG_OF_EMBED and CONFIG_OF_SEPARATE.
Signed-off-by: Michal Simek mon...@monstr.eu
CC: Simon Glass s...@chromium.org
---
arch/microblaze/config.mk |2 ++
arch/microblaze/cpu/u-boot.lds|1 +
arch/microblaze/include/asm/global_data.h |1 +
arch/microblaze/lib/board.c | 23 +++
4 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/arch/microblaze/config.mk b/arch/microblaze/config.mk
index aca79e2..b4935f0 100644
--- a/arch/microblaze/config.mk
+++ b/arch/microblaze/config.mk
@@ -31,3 +31,5 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F0
PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
LDSCRIPT ?= $(SRCTREE)/$(CPUDIR)/u-boot.lds
+
+CONFIG_ARCH_DEVICE_TREE := microblaze
diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds
index ee41145..d033a28 100644
--- a/arch/microblaze/cpu/u-boot.lds
+++ b/arch/microblaze/cpu/u-boot.lds
@@ -45,6 +45,7 @@ SECTIONS
.data ALIGN(0x4):
{
__data_start = .;
+ dts/libdts.o (.data)
*(.data)
__data_end = .;
}
diff --git a/arch/microblaze/include/asm/global_data.h
b/arch/microblaze/include/asm/global_data.h
index 6e8537c..e802e4e 100644
--- a/arch/microblaze/include/asm/global_data.h
+++ b/arch/microblaze/include/asm/global_data.h
@@ -43,6 +43,7 @@ typedef struct global_data {
unsigned long precon_buf_idx; /* Pre-Console buffer index */
#endif
unsigned long env_addr; /* Address of Environment struct */
+ const void *fdt_blob; /* Our device tree, NULL if none */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long fb_base;/* base address of frame buffer */
void**jt; /* jump table */
diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c
index f3679d5..59d39a0 100644
--- a/arch/microblaze/lib/board.c
+++ b/arch/microblaze/lib/board.c
@@ -32,6 +32,7 @@
#include stdio_dev.h
#include net.h
#include asm/processor.h
+#include fdtdec.h
DECLARE_GLOBAL_DATA_PTR;
@@ -68,6 +69,9 @@ typedef int (init_fnc_t) (void);
init_fnc_t *init_sequence[] = {
env_init,
+#ifdef CONFIG_OF_CONTROL
+ fdtdec_check_fdt,
+#endif
serial_init,
console_init_f,
#ifdef CONFIG_SYS_GPIO_0
@@ -110,6 +114,17 @@ void board_init (void)
monitor_flash_len = __end - __text_start;
+#ifdef CONFIG_OF_EMBED
+ /* Get a pointer to the FDT */
+ gd-fdt_blob = _binary_dt_dtb_start;
+#elif defined CONFIG_OF_SEPARATE
+ /* FDT is at end of image */
+ gd-fdt_blob = (void *)__end;
+#endif
+ /* Allow the early environment to override the fdt address */
+ gd-fdt_blob = (void *)getenv_ulong(fdtcontroladdr, 16,
+ (uintptr_t)gd-fdt_blob);
+
/*
* The Malloc area is immediately below the monitor copy in DRAM
* aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off
@@ -124,6 +139,14 @@ void board_init (void)
}
}
+#ifdef CONFIG_OF_CONTROL
+ /* For now, put this check after the console is ready */
+ if (fdtdec_prepare_fdt()) {
+ panic(** CONFIG_OF_CONTROL defined but no FDT - please see
+ doc/README.fdt-control);
+ }
+#endif
+
puts (SDRAM :\n);
printf (\t\tIcache:%s\n, icache_status() ? ON : OFF);
printf (\t\tDcache:%s\n, dcache_status() ? ON : OFF);
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM CONFIG_OF_CONTROL status
On 06/29/2012 04:32 AM, Simon Glass wrote:
Hi,
On Wed, Jun 27, 2012 at 11:49 PM, Michal Simek mon...@monstr.eu
mailto:mon...@monstr.eu wrote:
On 06/28/2012 07:57 AM, Simon Glass wrote:
Hi Michal,
On Wed, Jun 27, 2012 at 10:50 PM, Michal Simek mon...@monstr.eu
mailto:mon...@monstr.eu mailto:mon...@monstr.eu mailto:mon...@monstr.eu
wrote:
Hi Simon,
On 06/28/2012 03:10 AM, Simon Glass wrote:
Hi Michal,
On Wed, Jun 27, 2012 at 7:35 AM, Michal Simek mon...@monstr.eu mailto:mon...@monstr.eu
mailto:mon...@monstr.eu mailto:mon...@monstr.eu mailto:mon...@monstr.eu mailto:mon...@monstr.eu
mailto:mon...@monstr.eu mailto:mon...@monstr.eu wrote:
Hi Simon,
On 06/27/2012 03:58 PM, Simon Glass wrote:
Hi,
On Wed, Jun 27, 2012 at 2:29 AM, Michal Simek mon...@monstr.eu mailto:mon...@monstr.eu mailto:mon...@monstr.eu
mailto:mon...@monstr.eu mailto:mon...@monstr.eu mailto:mon...@monstr.eu mailto:mon...@monstr.eu mailto:mon...@monstr.eu
mailto:mon...@monstr.eu mailto:mon...@monstr.eu mailto:mon...@monstr.eu mailto:mon...@monstr.eu mailto:mon...@monstr.eu
mailto:mon...@monstr.eu mailto:mon...@monstr.eu mailto:mon...@monstr.eu wrote:
Hi,
can you please update me about current state of
CONFIG_OF_CONTROL for ARM?
Are there any other archs/boards which will use
this option?
Or any other git repo out of mainline u-boot?
Exynos is in progress - development is happening in the
Chromium tree and being upstreamed in chunks (although no fdt patches have been
sent yet).
ok.
Has someone tried to look for devices based on
compatible property?
I see that in usb driver it is based on aliases
which is not the best solution.
U-Boot doesn't yet have a device model which would
allow this in the general case. For now, drivers look for their own compatible
nodes. This works well enough until we have a device model.
There are other limitations also - for example USB
supports only a single controller type working at one time (a restriction we
may need to look at to support USB2 and USB3 together). So even if two USB
drivers decided that they both found compatible nodes, only one of them could
operate. So for now aliases provide just an ordering, nothing else.
I have looked at the code and did some tests on Microblaze.
Firstly I have tried to change emaclite ethernet
initialization and I ended with this code fragment which could be
broadly used by other drivers.
int offset = 0;
do {
offset =
fdt_node_offset_by_compatible(__gd-fdt_blob, offset,
xlnx,xps-ethernetlite-1.00.a );
You could check if offset 0 here, or
!fdtdec_get_is_enabled(gd-fdt_blob, offset)
u32 rxpp = fdtdec_get_int(gd-fdt_blob, offset,
xlnx,rx-ping-pong, 0);
u32 txpp = fdtdec_get_int(gd-fdt_blob, offset,
xlnx,tx-ping-pong, 0);
u32 reg = fdtdec_get_int(gd-fdt_blob, offset,
reg, 0);
Maybe fdtdec_get_addr()
yeah right.
do {
offset = fdt_node_offset_by_compatible(gd-fdt_blob,
offset, xlnx,xps-ethernetlite-1.00.a );
u32 rxpp = fdtdec_get_int(gd-fdt_blob, offset,
xlnx,rx-ping-pong, 0);
u32 txpp = fdtdec_get_int(gd-fdt_blob, offset,
xlnx,tx-ping-pong, 0);
u32 reg = fdtdec_get_addr(gd-fdt_blob, offset,
reg);
if (reg != FDT_ADDR_T_NONE)
ret |= xilinx_emaclite_initialize(bis,
reg, txpp, rxpp);
} while (offset != -1);
if (reg)
ret |=
xilinx_emaclite_initialize(__bis, reg, txpp, rxpp);
} while (offset != -1);
What do you think? This code is in platform file.
Seems reasonable to me.
ok.
Also I have tested code around aliases which parse DTS
aliases list for console initialization
and I have also get it work for !CONSOLE_SERIAL_MULTI case.
Great - I did send a patch to the list for fdt serial, but
haven't really got back to it.
Can you give me link to it or just subject?
WIP: fdt: Add serial port controlled by device tree
Re: [U-Boot] Is it possible to boot the U-boot from the another U-boot from the flash area
Dear Ishwar Saunshi, I have gone through the FAQ section, this FAQ only talks about the condition where the other Uboot is in RAM but what I am thinking is to boot the Uboot from the flash location by another running Uboot. This doesn't make any difference. Read more carefully, and read to the end. Pay special attention to the part here: U-Boot expects to see a virgin CPU, i. e. the CPU state must match what you see if the processor starts executing the first instructions when it comes out of reset. If you want to start U-Boot from another boot loader, you must disable a lot of code ... This is really highly CPU-dependent. We are using something like that to implement a fallback u-boot image in case someone manages to kill the standard image, it was quite easy to do for e.g. mpc512x, but quite some coding effort for mpc85XX. The corresponding code always looks slightly insane. If you feel like diving in deep into the innards of your CPU, go for it. If you don't really need it, skip it. :-) Kolja Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de You don't have to stay up nights to succeed; you have to stay awake days. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: AT91: add at91sam9x5ek board support
Hi Andreas,
On 6/27/2012 21:47, Andreas Bießmann wrote:
On 22.05.2012 12:06, Bo Shen wrote:
Add at91sam9x5ek board support.
support AT91SAM9G15, G25, G35, X25, X35 SoC
Signed-off-by: Bo Shen voice.s...@atmel.com
In general:
---8---
total: 14 errors, 11 warnings, 1148 lines checked
NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX
MULTISTATEMENT_MACRO_USE_DO_WHILE
/tmp/[PATCH] arm: AT91: add at91sam9x5ek board support.eml has style
problems, please review.
---8---
please fix these.
Ok, I will fix this at next version patch.
[...]
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
new file mode 100644
index 000..e4262a5
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2012 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/arch/at91_common.h
+#include asm/arch/at91_pmc.h
+#include asm/arch/gpio.h
+#include asm/io.h
+
+#define AT91_CIDR_VERSION (0x1f 0) /* Version of the Device */
this should go into a header.
Ok, I will fix this at next version patch.
+
+unsigned int get_chip_id(void)
+{
+ return readl(ATMEL_BASE_DBGU + 0x40) ~AT91_CIDR_VERSION;
can we get some explanation of these magic numbers please (0x40 here and
0x44 later), maybe add these offsets to the header?
Ok, I will fix this at next version patch.
+
+}
[...]
+void at91_serial2_hw_init(void)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+
+ at91_set_a_periph(AT91_PIO_PORTA, 7, 1);/* TXD */
+ at91_set_a_periph(AT91_PIO_PORTA, 8, 0);/* RXD */
+
+ writel(1 ATMEL_ID_USART2, pmc-pcer);
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+ at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_PMC_BASE;
-^
please use same style everywhere (before there was no whitespace). I
personally favour to remove it, but all other at91 xx_init() do have a
whitespace here, so I tend to leave it as is and add the whitespace in
the lines above. If you have a strong meaning here send patches for the
other files too.
I will keep the old style. Keep the whitespace.
+
[...]
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c
b/arch/arm/cpu/arm926ejs/at91/clock.c
index a7085de..fd26faa 100644
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -154,7 +154,8 @@ int at91_clock_init(unsigned long main_clock)
* For now, assume this parentage won't change.
*/
mckr = readl(pmc-mckr);
-#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
+ || defined(CONFIG_AT91SAM9X5)
/* plla divisor by 2 */
gd-plla_rate_hz /= (1 ((mckr 1 12) 12));
#endif
@@ -168,7 +169,9 @@ int at91_clock_init(unsigned long main_clock)
freq / ((mckr AT91_PMC_MCKR_MDIV_MASK) 7) : freq;
if (mckr AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
-#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+ /* plla divisor by 2 */
Is this slipped in? This portion handles mck, plla was some lines above.
The comment has a mistake. I will correct this.
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
+ || defined(CONFIG_AT91SAM9X5)
gd-mck_rate_hz = (mckr AT91_PMC_MCKR_MDIV_MASK) ==
(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3
[...]
diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h
b/arch/arm/include/asm/arch-at91/at91sam9x5.h
new file mode 100644
index 000..30bad24
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h
@@ -0,0 +1,172 @@
+/*
+ * Chip-specific header file for the AT91SAM9x5 family
+ *
+ * Copyright (C) 2012 Atmel Corporation.
+ *
+ * Definitions for the SoC:
+ * AT91SAM9x5
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU
[U-Boot] [PATCH] powerpc/p2041: configure the CPLD lane_mux according to RCW
Lane muxing on p2041 is controlled by a reg in CPLD, offset of this reg
is 0xc, CPLD supports SATA by default, we should re-configure the lane
muxing according to RCW, which indicates what SerDes protocol it is running.
Default lane muxing map is as below:
Lane G on bank1 routes to SGMII, controlled by bit 1 of the reg;
Lane A on bank2 routes to AURORA, controlled by bit 0 of the reg;
Lane C/D on bank2 routes to SATA0 and SATA1, controlled by bit 2
and bit 3 respectively.
Default value of these bits for lane muxing is '1', we should set or clear
these bits accoring to RCW.
Signed-off-by: Shaohui Xie shaohui@freescale.com
Acked-by: Timur Tabi ti...@freescale.com
---
board/freescale/p2041rdb/eth.c | 39 +++
1 files changed, 39 insertions(+), 0 deletions(-)
diff --git a/board/freescale/p2041rdb/eth.c b/board/freescale/p2041rdb/eth.c
index 4b0d577..fec9777 100644
--- a/board/freescale/p2041rdb/eth.c
+++ b/board/freescale/p2041rdb/eth.c
@@ -136,6 +136,11 @@ void board_ft_fman_fixup_port(void *fdt, char *compat,
phys_addr_t addr,
}
#endif /* #ifdef CONFIG_FMAN_ENET */
+#define CPLD_LANE_A_SEL0x1
+#define CPLD_LANE_G_SEL0x2
+#define CPLD_LANE_C_SEL0x4
+#define CPLD_LANE_D_SEL0x8
+
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
@@ -143,6 +148,10 @@ int board_eth_init(bd_t *bis)
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
int lane;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ int srds_prtcl = (in_be32(gur-rcwsr[4])
+ FSL_CORENET_RCWSR4_SRDS_PRTCL) 26;
+ u8 mux = CPLD_READ(serdes_mux);
printf(Initializing Fman\n);
@@ -172,6 +181,36 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
+ mux = ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL);
+ switch (srds_prtcl) {
+ case 0x2:
+ case 0xf:
+ mux = ~CPLD_LANE_G_SEL;
+ break;
+ case 0x5:
+ case 0x9:
+ case 0xa:
+ case 0x17:
+ mux |= CPLD_LANE_G_SEL;
+ break;
+ case 0x14:
+ mux = (mux (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL;
+ break;
+ case 0x8:
+ case 0x16:
+ case 0x19:
+ case 0x1a:
+ mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
+ break;
+ case 0x1c:
+ mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
+ break;
+ default:
+ printf(Fman:Unsupported SerDes Protocol 0x%02x\n, srds_prtcl);
+ break;
+ }
+ CPLD_WRITE(serdes_mux, mux);
+
for (i = FM1_DTSEC1; i FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
--
1.6.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] KW: Move the memory register definitions into kirkwood.h
Dear Gerlando Falauto,
Dear Maruk,
I am currently trying to address the exact same issue (SDRAM size
detection and fixup).
My idea was however (as opposed to moving register definition as you
did), to add a fixup function to dram.c, say:
/*
* kw_sdram_bs - writes SDRAM Bank size
*/
void kw_sdram_bs_set(enum memory_bank bank, u32 size)
{
/* Read current register value */
u32 reg = readl(KW_REG_CPUCS_WIN_SZ(bank));
printf(Current value: %x\n, reg);
/* Clear window size */
reg = ~KW_REG_CPUCS_WIN_SIZE(0xFF);
/* Set new window size */
reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) 24);
printf(Writing: %x\n, reg);
writel(reg, KW_REG_CPUCS_WIN_SZ(bank));
}
which would then be called to fix the window size according to the total
memory size as reported by get_ram_size().
Read up at [1].
http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/133991
What do you think?
Thank you,
Gerlando
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/3] AM335x : Add USB support for AM335x in u-boot
-Original Message- From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Rini, Tom Sent: Wednesday, June 27, 2012 10:50 PM To: Sohanpal, Harman Cc: u-boot@lists.denx.de; Gene Zarkhin Subject: Re: [U-Boot] [PATCH v3 1/3] AM335x : Add USB support for AM335x in u-boot On Tue, Jun 26, 2012 at 03:08:01PM +0530, Harman Sohanpal wrote: From: Gene Zarkhin gene_zark...@bose.com Adds USB support in uboot for AM335x. By default the USB 1 module is enabled. The support for USB 0 can be enabled by changing the USB base address and the phy control register address in the header file am335x.h. USB 1 has a full size connector so acts in host mode and USB 0 has a mini connector so used in device mode. By default, the support is added for host mode hence USB 1 has been enabled by default. Signed-off-by: Gene Zarkhin gene_zark...@bose.com Signed-off-by: Harman Sohanpal harman_sohan...@ti.com What I was saying was that we want to make am335x.h do: #define AM335X_USB0_BASE 0x47401000 #define AM335X_USB1_BASE 0x47401800 Then: #ifdef CONFIG_AM335X_USB0 #define AM335X_USB_OTG_BASE AM335X_USB0_BASE #elif defined(CONFIG_AM335X_USB1) #define AM335X_USB_OTG_BASE AM335X_USB1_BASE #endif #define AM335X_USB_OTG_CORE_BASE (AM335X_USB_OTG_BASE + 0x400) So that in boards.cfg we could add an entry for am335x_evm_usb1 and set CONFIG_AM335X_USB1 dynamically. Then in am335x_evm.h set either MUSB_HCD or MUSB_UDC based on if CONFIG_AM335X_USB0 or CONFIG_AM335X_USB1 is set (and have boards.cfg set CONFIG_AM335X_USB0 for 'am335x_evm). Then you can test device mode on the evm :) And how did you test device mode on the beaglebone? I couldn't since I don't have the rest set of adapters here. Also: +++ b/drivers/usb/musb/am335x.h [snip] +/* Control Module Registers */ +#define CM_REGISTERS CTRL_BASE +#define USB_CTRL0_REG_OFFSET (0x628) +#define USB_CTRL1_REG_OFFSET (0x680) Please get all indentation out to a consistent level +#define PRCM_IDLEST 0x3 +#define DPLL_CLKDCOLDO_GATE_CTRL0x300 And always use tabs :) Hi Tom, Thanks for the review. I will send the patches doing all the modifications you have mentioned. Also there was some confusion regarding testing in the device mode. A new node /dev/ttyUSB0 was seen when beagle bone was connected to a linux machine, but it is not using USB as serial using usbtty. It was using the USB to serial chip in the beagle bone. Sorry for that. So I am still to confirm whether the device mode works with usbtty. But previously I have tested the device mode on both evm and beagle bone using some local DFU patches and it worked fine. Thanks, Harman ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] environment access before relocation does not work on (some) arm
Dear Matthias Fuchs, In message 4fed7877.2020...@esd.eu you wrote: I just noticed that using getenv (and friends) does not work on ARM (namely i.MX28) from board_init_f() after running through the init_sequence. This is normal, and documented. Before relocation, you must not use getenv(). Env access does not work before env_relocate() in board_init_r(). It does, but you have to play by the rules, i. e. use getenv_f() instead. Didn't this behave different sometimes before? Even after the big env rework? No. The use of getenv() before relocation has never been supported. It may have worked (by pure chance) on some systems, but that's all. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Time is an illusion perpetrated by the manufacturers of space. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 3/3] musb_udc : Fix compile warning.
Fix the compile warning : implicit declaration of musb_platform_init when CONFIG_MUSB_UDC is defined. The extern musb_platform_init was declared in musb_hcd.h but no such extern function was declared for musb_udc. So a common function has been declared in musb_core.h which can be used for both host mode and device mode. Signed-off-by: Harman Sohanpal harman_sohan...@ti.com --- Changes for v2: - none Changes for v3: - none Changes for v4: - none drivers/usb/musb/musb_core.h |2 ++ drivers/usb/musb/musb_hcd.h |3 --- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index a8adcce..14253f0 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -360,6 +360,8 @@ extern void musb_start(void); extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt); extern void write_fifo(u8 ep, u32 length, void *fifo_data); extern void read_fifo(u8 ep, u32 length, void *fifo_data); +extern int musb_platform_init(void); +extern void musb_platform_deinit(void); #if defined(CONFIG_USB_BLACKFIN) /* Every USB register is accessed as a 16-bit even if the value itself diff --git a/drivers/usb/musb/musb_hcd.h b/drivers/usb/musb/musb_hcd.h index dde7d37..5621f7e 100644 --- a/drivers/usb/musb/musb_hcd.h +++ b/drivers/usb/musb/musb_hcd.h @@ -105,8 +105,5 @@ extern unsigned char new[]; #define RH_REQ_ERR-1 #define RH_NACK 0x00 -/* extern functions */ -extern int musb_platform_init(void); -extern void musb_platform_deinit(void); #endif /* __MUSB_HCD_H__ */ -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/3] AM335x: Add USB support in u-boot.
Dear Harman Sohanpal, These patches add USB support in u-boot for AM335x. The support for host or device is selected depending on the config selected from boards.cfg file. Host mode is selected for USB1 and device mode is selected for USB0. Base addresses are selected accordingly. I'll go through these once I get some sleep ... aka in 12 hours or so Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] kirkwood: implement kw_sdram_bs_set()
Some boards might be equipped with different SDRAM configurations.
When that is the case, CPU CS Window Size Register (CS[0]n Size) should
be set to the biggest value through board.cfg file; then its value
can be fixed at runtime according to the detected SDRAM size.
Therefore, implement kw_sdram_bs_set(), to be called for instance within
board_early_init_f().
Signed-off-by: Gerlando Falauto gerlando.fala...@keymile.com
Cc: Marek Vasut ma...@denx.de
Cc: Prafulla Wadaskar prafu...@marvell.com
Cc: Wolfgang Denk w...@denx.de
Cc: Valentin Longchamp valentin.longch...@keymile.com
Cc: Holger Brunck holger.bru...@keymile.com
---
arch/arm/cpu/arm926ejs/kirkwood/dram.c | 28 ++--
arch/arm/include/asm/arch-kirkwood/cpu.h |2 ++
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
index 2441554..e5409f1 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
@@ -28,8 +28,15 @@
DECLARE_GLOBAL_DATA_PTR;
-#define KW_REG_CPUCS_WIN_BAR(x)(KW_REGISTER(0x1500) + (x *
0x08))
-#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08))
+/* Kirkwood memory registers */
+#define KW_REG_CPUCS_WIN_BAR(x)(KW_REGISTER(0x1500) + ((x) *
0x08))
+#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + ((x) * 0x08))
+
+#define KW_REG_CPUCS_WIN_ENABLE(1 0)
+#define KW_REG_CPUCS_WIN_WR_PROTECT(1 1)
+#define KW_REG_CPUCS_WIN_WIN0_CS(x)(((x) 0x3) 2)
+#define KW_REG_CPUCS_WIN_SIZE(x) (((x) 0xff) 24)
+
/*
* kw_sdram_bar - reads SDRAM Base Address Register
*/
@@ -60,6 +67,23 @@ u32 kw_sdram_bs(enum memory_bank bank)
return result;
}
+/*
+ * kw_sdram_bs_set - writes SDRAM Bank size
+ */
+void kw_sdram_bs_set(enum memory_bank bank, u32 size)
+{
+ /* Read current register value */
+ u32 reg = readl(KW_REG_CPUCS_WIN_SZ(bank));
+
+ /* Clear window size */
+ reg = ~KW_REG_CPUCS_WIN_SIZE(0xFF);
+
+ /* Set new window size */
+ reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) 24);
+
+ writel(reg, KW_REG_CPUCS_WIN_SZ(bank));
+}
+
#ifndef CONFIG_SYS_BOARD_DRAM_INIT
int dram_init(void)
{
diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h
b/arch/arm/include/asm/arch-kirkwood/cpu.h
index d28c51a..807154e 100644
--- a/arch/arm/include/asm/arch-kirkwood/cpu.h
+++ b/arch/arm/include/asm/arch-kirkwood/cpu.h
@@ -159,6 +159,8 @@ void reset_cpu(unsigned long ignored);
unsigned char get_random_hex(void);
unsigned int kw_sdram_bar(enum memory_bank bank);
unsigned int kw_sdram_bs(enum memory_bank bank);
+void kw_sdram_bs_set(enum memory_bank bank, u32 size);
+
int kw_config_adr_windows(void);
void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
unsigned int gpp0_oe, unsigned int gpp1_oe);
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 00/10 V3] EXYNOS5: Support for Exynos5250 Rev 1.0
This patch set adds support for Exynos5250 Rev 1.0. Exynos5250 Rev 1.0 supports DDR3 Memory configuration and support for LPDDR2 is removed. Exynos5250 Rev 1.0 supports DWMMC controller and does not support SDHCI controller. After DWMMC driver is added to Mainline support for generic S5P MMC driver will be removed. Due to Support of SDHCI controller currently still there for EXYNOS5 you can see the following error on boot. mmc_reset: timeout error mmc_change_clock: timeout error mmc_send_cmd: waiting for status update MMC init failed Changes in V2: - Included Paramateric structure with in #ifndef __ASSEMBLY__. Chnages in V3: - Incorporated the review comments. - Added support for BPLL. - Corrected the gpio pinmux settings. Rajeshwari Shinde (10): ARCH: SPL: Add parametric board initializer SMDK5250: SPL: Define parametric board initializer SMDK5250: Add smdk5250-uboot-spl.lds EXYNOS5: CLOCK: define additional clock registers for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Add clock support for Exynos5250 Rev 1.0 Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 EXYNOS5: CLOCK: Add BPLL support EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0 SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0 arch/arm/cpu/armv7/exynos/clock.c | 28 +- arch/arm/cpu/armv7/exynos/pinmux.c| 22 +- arch/arm/include/asm/arch-exynos/clk.h|1 + arch/arm/include/asm/arch-exynos/clock.h | 237 + arch/arm/include/asm/arch-exynos/dmc.h| 65 +++ arch/arm/include/asm/arch-exynos/gpio.h |7 +- arch/arm/include/asm/arch-exynos/spl.h| 97 board/samsung/smdk5250/Makefile |3 +- board/samsung/smdk5250/clock_init.c | 714 +++ board/samsung/smdk5250/clock_init.h | 149 + board/samsung/smdk5250/dmc_common.c | 199 +++ board/samsung/smdk5250/dmc_init.c | 462 --- board/samsung/smdk5250/dmc_init_ddr3.c| 228 board/samsung/smdk5250/setup.h| 762 +++-- board/samsung/smdk5250/smdk5250-uboot-spl.lds | 66 +++ board/samsung/smdk5250/smdk5250.c |6 +- board/samsung/smdk5250/smdk5250_spl.c | 68 +++ include/configs/smdk5250.h|7 +- 18 files changed, 2099 insertions(+), 1022 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/spl.h create mode 100644 board/samsung/smdk5250/clock_init.h create mode 100644 board/samsung/smdk5250/dmc_common.c delete mode 100644 board/samsung/smdk5250/dmc_init.c create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c create mode 100644 board/samsung/smdk5250/smdk5250-uboot-spl.lds create mode 100644 board/samsung/smdk5250/smdk5250_spl.c -- 1.7.4.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/10 V3] ARCH: SPL: Add parametric board initializer
Add a structure for table-driven configuration mechanism such that no
recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.
Signed-off-by: Che-Liang Chiou clch...@chromium.org
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Tom Wai-Hong Tam waih...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- Included Paramateric structure with in #ifndef __ASSEMBLY__.
Changes in V3:
- None
arch/arm/include/asm/arch-exynos/spl.h | 97
1 files changed, 97 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/spl.h
diff --git a/arch/arm/include/asm/arch-exynos/spl.h
b/arch/arm/include/asm/arch-exynos/spl.h
new file mode 100644
index 000..306b41d
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/spl.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SPL_H__
+#define __ASM_ARCH_EXYNOS_SPL_H__
+
+#include asm/arch-exynos/dmc.h
+
+enum boot_mode {
+ /*
+* Assign the OM pin values for respective boot modes.
+* Exynos4 does not support spi boot and the mmc boot OM
+* pin values are the same across Exynos4 and Exynos5.
+*/
+ BOOT_MODE_MMC = 4,
+ BOOT_MODE_SERIAL = 20,
+ /* Boot based on Operating Mode pin settings */
+ BOOT_MODE_OM = 32,
+ BOOT_MODE_USB, /* Boot using USB download */
+};
+
+#ifndef __ASSEMBLY__
+/* Parameters of early board initialization in SPL */
+struct spl_machine_param {
+ /* Add fields as and when required */
+ u32 signature;
+ u32 version;/* Version number */
+ u32 size; /* Size of block */
+ /**
+* Parameters we expect, in order, terminated with \0. Each parameter
+* is a single character representing one 32-bit word in this
+* structure.
+*
+* Valid characters in this string are:
+*
+* Code Name
+* vmem_iv_size
+* mmem_type
+* uuboot_size
+* bboot_source
+* ffrequency_mhz (memory frequency in MHz)
+* aARM clock frequency in MHz
+* sserial base address
+* ii2c base address for early access (meant for PMIC)
+* rboard rev GPIO numbers used to read board revision
+* (lower halfword=bit 0, upper=bit 1)
+* MMemory Manufacturer name
+* \0 termination
+*/
+ charparams[12]; /* Length must be word-aligned */
+ u32 mem_iv_size;/* Memory channel interleaving size */
+ enum ddr_mode mem_type; /* Type of on-board memory */
+ /*
+* U-boot size - The iROM mmc copy function used by the SPL takes a
+* block count paramter to describe the u-boot size unlike the spi
+* boot copy function which just uses the u-boot size directly. Align
+* the u-boot size to block size (512 bytes) when populating the SPL
+* table only for mmc boot.
+*/
+ u32 uboot_size;
+ enum boot_mode boot_source;/* Boot device */
+ enum mem_manuf mem_manuf; /* Memory Manufacturer */
+ unsignedfrequency_mhz; /* Frequency of memory in MHz */
+ unsignedarm_freq_mhz; /* ARM Frequency in MHz */
+ u32 serial_base;/* Serial base address */
+ u32 i2c_base; /* i2c base address */
+} __attribute__((__packed__));
+#endif
+
+/**
+ * Validate signature and return a pointer to the parameter table. If the
+ * signature is invalid, call panic() and never return.
+ *
+ * @return pointer to the parameter table if signature matched or never return.
+ */
+struct spl_machine_param *spl_get_machine_params(void);
+
+#endif /* __ASM_ARCH_EXYNOS_SPL_H__ */
--
1.7.4.4
[U-Boot] [PATCH 02/10 V3] SMDK5250: SPL: Define parametric board initializer
Define table-driven configuration mechanism for SMDK5250
rather than hard-coding board initialization parameters.
Signed-off-by: Che-Liang Chiou clch...@chromium.org
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Tom Wai-Hong Tam waih...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- None
Changes in V3:
- None
board/samsung/smdk5250/Makefile |1 +
board/samsung/smdk5250/smdk5250_spl.c | 68 +
2 files changed, 69 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk5250/smdk5250_spl.c
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 226db1f..3675fad 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -29,6 +29,7 @@ SOBJS := lowlevel_init.o
COBJS := clock_init.o
COBJS += dmc_init.o
COBJS += tzpc_init.o
+COBJS += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
COBJS += smdk5250.o
diff --git a/board/samsung/smdk5250/smdk5250_spl.c
b/board/samsung/smdk5250/smdk5250_spl.c
new file mode 100644
index 000..1d453ca
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250_spl.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/arch/cpu.h
+#include asm/arch/spl.h
+#include asm/arch/clk.h
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(.machine_param))) = {
+ .signature = SIGNATURE,
+ .version= 1,
+ .params = vmubfasirM,
+ .size = sizeof(machine_param),
+
+ .mem_iv_size= 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+* Set uboot_size to 0x10 bytes.
+*
+* This is an overly conservative value chosen to accommodate all
+* possible U-Boot image. You are advised to set this value to a
+* smaller realistic size via scripts that modifies the .machine_param
+* section of output U-Boot image.
+*/
+ .uboot_size = 0x10,
+
+ .boot_source= BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 1700,
+ .serial_base= 0x12c3,
+ .i2c_base = 0x12c6,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return machine_param;
+}
--
1.7.4.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 06/10 V3] Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0
The patch adds the memory initialization sequence of DDR3.
Signed-off-by: Hatim Ali hatim...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- None.
Chnages in V3:
- None.
arch/arm/include/asm/arch-exynos/dmc.h | 65 +
board/samsung/smdk5250/Makefile|2 +-
board/samsung/smdk5250/dmc_common.c| 199 ++
board/samsung/smdk5250/dmc_init.c | 462
board/samsung/smdk5250/dmc_init_ddr3.c | 228
board/samsung/smdk5250/setup.h | 59 -
6 files changed, 551 insertions(+), 464 deletions(-)
create mode 100644 board/samsung/smdk5250/dmc_common.c
delete mode 100644 board/samsung/smdk5250/dmc_init.c
create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h
b/arch/arm/include/asm/arch-exynos/dmc.h
index bd52d16..f65c676 100644
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -251,5 +251,70 @@ struct exynos5_phy_control {
unsigned int phy_con41;
unsigned int phy_con42;
};
+
+enum ddr_mode {
+ DDR_MODE_DDR2,
+ DDR_MODE_DDR3,
+ DDR_MODE_LPDDR2,
+ DDR_MODE_LPDDR3,
+
+ DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+ MEM_MANUF_AUTODETECT,
+ MEM_MANUF_ELPIDA,
+ MEM_MANUF_SAMSUNG,
+
+ MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT28
+#define CONCONTROL_RD_FETCH_SHIFT 12
+#define CONCONTROL_RD_FETCH_MASK (0x7 CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT 5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT 24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT 17
+#define PHY_CON0_T_WRRDCMD_MASK(0x7
PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT 24
+#define PHY_CON12_CTRL_INC_SHIFT 16
+#define PHY_CON12_CTRL_FORCE_SHIFT 8
+#define PHY_CON12_CTRL_START_SHIFT 6
+#define PHY_CON12_CTRL_START_MASK (1 PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT5
+#define PHY_CON12_CTRL_DLL_ON_MASK (1 PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT 1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT24
+#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK(0x7 PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT8
+#define PHY_CON42_CTRL_BSTLEN_MASK (0xff PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+#define PHY_CON42_CTRL_RDLAT_MASK (0x1f PHY_CON42_CTRL_RDLAT_SHIFT)
+
#endif
#endif
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 3675fad..1474fa8 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -27,7 +27,7 @@ LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
COBJS := clock_init.o
-COBJS += dmc_init.o
+COBJS += dmc_common.o dmc_init_ddr3.o
COBJS += tzpc_init.o
COBJS += smdk5250_spl.o
diff --git a/board/samsung/smdk5250/dmc_common.c
b/board/samsung/smdk5250/dmc_common.c
new file mode 100644
index 000..109602a
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_common.c
@@ -0,0 +1,199 @@
+/*
+ * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/arch/spl.h
+
+#include clock_init.h
+#include setup.h
+
+#define ZQ_INIT_TIMEOUT1
+
+int dmc_config_zq(struct mem_timings *mem,
+ struct exynos5_phy_control *phy0_ctrl,
+
[U-Boot] [PATCH 08/10 V3] EXYNOS5: CLOCK: Add BPLL support
This patch adds support for BPLL clock.
Signed-off-b: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V3:
- New Patch.
arch/arm/cpu/armv7/exynos/clock.c| 26 --
arch/arm/include/asm/arch-exynos/clk.h |1 +
arch/arm/include/asm/arch-exynos/clock.h |2 ++
3 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index dbd5f11..13e3641 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
- unsigned int freq, pll_div2_sel, mpll_fout_sel;
+ unsigned int freq, pll_div2_sel, fout_sel;
switch (pllreg) {
case APLL:
@@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
r = readl(clk-vpll_con0);
k = readl(clk-vpll_con1);
break;
+ case BPLL:
+ r = readl(clk-bpll_con0);
+ break;
default:
printf(Unsupported PLL (%d)\n, pllreg);
return 0;
@@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
* MPLL_CON: MIDV [25:16]
* EPLL_CON: MIDV [24:16]
* VPLL_CON: MIDV [24:16]
+* BPLL_CON: MIDV [25:16]
*/
- if (pllreg == APLL || pllreg == MPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
mask = 0x3ff;
else
mask = 0x1ff;
@@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
fout = m * (freq / (p * (1 (s - 1;
}
- /* According to the user manual, in EVT1 MPLL always gives
+ /* According to the user manual, in EVT1 MPLL and BPLL always gives
* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
- if (pllreg == MPLL) {
+ if (pllreg == MPLL | pllreg == BPLL) {
pll_div2_sel = readl(clk-pll_div2_sel);
- mpll_fout_sel = (pll_div2_sel MPLL_FOUT_SEL_SHIFT)
+
+ switch (pllreg) {
+ case MPLL:
+ fout_sel = (pll_div2_sel MPLL_FOUT_SEL_SHIFT)
MPLL_FOUT_SEL_MASK;
- if (mpll_fout_sel == 0)
+ break;
+ case BPLL:
+ fout_sel = (pll_div2_sel BPLL_FOUT_SEL_SHIFT)
+BPLL_FOUT_SEL_MASK;
+ break;
+ }
+
+ if (fout_sel == 0)
fout /= 2;
}
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index 637fb4b..e99339a 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -27,6 +27,7 @@
#define EPLL 2
#define HPLL 3
#define VPLL 4
+#define BPLL 5
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index bf41c19..fce38ef 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -599,4 +599,6 @@ struct exynos5_clock {
#define MPLL_FOUT_SEL_SHIFT4
#define MPLL_FOUT_SEL_MASK 0x1
+#define BPLL_FOUT_SEL_SHIFT0
+#define BPLL_FOUT_SEL_MASK 0x1
#endif
--
1.7.4.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] kw_spi: fix clock prescaler computation
The computation was not correct with low clock values: setting a 1MHz
clock would result in an overlap that would then configure a 25Mhz
clock.
This patch implements a correct computation method according to the
kirkwood functionnal spec. table 629 (Serial Memory Interface
Configuration Register).
Signed-off-by: Valentin Longchamp valentin.longch...@keymile.com
cc: Holger Brunck holger.bru...@keymile.com
cc: Prafulla Wadaskar prafu...@marvell.com
---
arch/arm/include/asm/arch-kirkwood/spi.h |1 +
drivers/spi/kirkwood_spi.c |5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h
b/arch/arm/include/asm/arch-kirkwood/spi.h
index 1d5043f..5a38dc5 100644
--- a/arch/arm/include/asm/arch-kirkwood/spi.h
+++ b/arch/arm/include/asm/arch-kirkwood/spi.h
@@ -38,6 +38,7 @@ struct kwspi_registers {
};
#define KWSPI_CLKPRESCL_MASK 0x1f
+#define KWSPI_CLKPRESCL_MIN0x12
#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */
#define KWSPI_SMEMRDY (1 1) /* SerMem Data xfer ready */
#define KWSPI_IRQUNMASK1 /* unmask SPI interrupt */
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index ee14669..9b3f6a4 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -57,8 +57,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned
int cs,
writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, spireg-ctrl);
/* calculate spi clock prescaller using max_hz */
- data = ((CONFIG_SYS_TCLK / 2) / max_hz) KWSPI_CLKPRESCL_MASK;
- data |= 0x10;
+ data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
+ data = data KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
+ data = data KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
/* program spi clock prescaller using max_hz */
writel(KWSPI_ADRLEN_3BYTE | data, spireg-cfg);
--
1.7.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/10 V4] ARCH: SPL: Add parametric board initializer
Add a structure for table-driven configuration mechanism such that no
recompilation
is needed to update the configuration parameters, rather than hard-coding
board initialization parameters.
Signed-off-by: Che-Liang Chiou clch...@chromium.org
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Tom Wai-Hong Tam waih...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- Included Paramateric structure with in #ifndef __ASSEMBLY__.
Changes in V3:
- None
Changes in V4:
- None
arch/arm/include/asm/arch-exynos/spl.h | 97
1 files changed, 97 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-exynos/spl.h
diff --git a/arch/arm/include/asm/arch-exynos/spl.h
b/arch/arm/include/asm/arch-exynos/spl.h
new file mode 100644
index 000..306b41d
--- /dev/null
+++ b/arch/arm/include/asm/arch-exynos/spl.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SPL_H__
+#define __ASM_ARCH_EXYNOS_SPL_H__
+
+#include asm/arch-exynos/dmc.h
+
+enum boot_mode {
+ /*
+* Assign the OM pin values for respective boot modes.
+* Exynos4 does not support spi boot and the mmc boot OM
+* pin values are the same across Exynos4 and Exynos5.
+*/
+ BOOT_MODE_MMC = 4,
+ BOOT_MODE_SERIAL = 20,
+ /* Boot based on Operating Mode pin settings */
+ BOOT_MODE_OM = 32,
+ BOOT_MODE_USB, /* Boot using USB download */
+};
+
+#ifndef __ASSEMBLY__
+/* Parameters of early board initialization in SPL */
+struct spl_machine_param {
+ /* Add fields as and when required */
+ u32 signature;
+ u32 version;/* Version number */
+ u32 size; /* Size of block */
+ /**
+* Parameters we expect, in order, terminated with \0. Each parameter
+* is a single character representing one 32-bit word in this
+* structure.
+*
+* Valid characters in this string are:
+*
+* Code Name
+* vmem_iv_size
+* mmem_type
+* uuboot_size
+* bboot_source
+* ffrequency_mhz (memory frequency in MHz)
+* aARM clock frequency in MHz
+* sserial base address
+* ii2c base address for early access (meant for PMIC)
+* rboard rev GPIO numbers used to read board revision
+* (lower halfword=bit 0, upper=bit 1)
+* MMemory Manufacturer name
+* \0 termination
+*/
+ charparams[12]; /* Length must be word-aligned */
+ u32 mem_iv_size;/* Memory channel interleaving size */
+ enum ddr_mode mem_type; /* Type of on-board memory */
+ /*
+* U-boot size - The iROM mmc copy function used by the SPL takes a
+* block count paramter to describe the u-boot size unlike the spi
+* boot copy function which just uses the u-boot size directly. Align
+* the u-boot size to block size (512 bytes) when populating the SPL
+* table only for mmc boot.
+*/
+ u32 uboot_size;
+ enum boot_mode boot_source;/* Boot device */
+ enum mem_manuf mem_manuf; /* Memory Manufacturer */
+ unsignedfrequency_mhz; /* Frequency of memory in MHz */
+ unsignedarm_freq_mhz; /* ARM Frequency in MHz */
+ u32 serial_base;/* Serial base address */
+ u32 i2c_base; /* i2c base address */
+} __attribute__((__packed__));
+#endif
+
+/**
+ * Validate signature and return a pointer to the parameter table. If the
+ * signature is invalid, call panic() and never return.
+ *
+ * @return pointer to the parameter table if signature matched or never return.
+ */
+struct spl_machine_param *spl_get_machine_params(void);
+
+#endif /*
[U-Boot] [PATCH 02/10 V4] SMDK5250: SPL: Define parametric board initializer
Define table-driven configuration mechanism for SMDK5250
rather than hard-coding board initialization parameters.
Signed-off-by: Che-Liang Chiou clch...@chromium.org
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Tom Wai-Hong Tam waih...@chromium.org
Signed-off-by: Simon Glass s...@chromium.org
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- None
board/samsung/smdk5250/Makefile |1 +
board/samsung/smdk5250/smdk5250_spl.c | 68 +
2 files changed, 69 insertions(+), 0 deletions(-)
create mode 100644 board/samsung/smdk5250/smdk5250_spl.c
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 226db1f..3675fad 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -29,6 +29,7 @@ SOBJS := lowlevel_init.o
COBJS := clock_init.o
COBJS += dmc_init.o
COBJS += tzpc_init.o
+COBJS += smdk5250_spl.o
ifndef CONFIG_SPL_BUILD
COBJS += smdk5250.o
diff --git a/board/samsung/smdk5250/smdk5250_spl.c
b/board/samsung/smdk5250/smdk5250_spl.c
new file mode 100644
index 000..1d453ca
--- /dev/null
+++ b/board/samsung/smdk5250/smdk5250_spl.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/arch/cpu.h
+#include asm/arch/spl.h
+#include asm/arch/clk.h
+
+#define SIGNATURE 0xdeadbeef
+
+/* Parameters of early board initialization in SPL */
+static struct spl_machine_param machine_param
+ __attribute__((section(.machine_param))) = {
+ .signature = SIGNATURE,
+ .version= 1,
+ .params = vmubfasirM,
+ .size = sizeof(machine_param),
+
+ .mem_iv_size= 0x1f,
+ .mem_type = DDR_MODE_DDR3,
+
+ /*
+* Set uboot_size to 0x10 bytes.
+*
+* This is an overly conservative value chosen to accommodate all
+* possible U-Boot image. You are advised to set this value to a
+* smaller realistic size via scripts that modifies the .machine_param
+* section of output U-Boot image.
+*/
+ .uboot_size = 0x10,
+
+ .boot_source= BOOT_MODE_OM,
+ .frequency_mhz = 800,
+ .arm_freq_mhz = 1700,
+ .serial_base= 0x12c3,
+ .i2c_base = 0x12c6,
+ .mem_manuf = MEM_MANUF_SAMSUNG,
+};
+
+struct spl_machine_param *spl_get_machine_params(void)
+{
+ if (machine_param.signature != SIGNATURE) {
+ /* Will hang if SIGNATURE dont match */
+ while (1)
+ ;
+ }
+
+ return machine_param;
+}
--
1.7.4.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 06/10 V4] Exynos5: DDR3: Add DDR3 memory setup for Exynos5250 Rev 1.0
The patch adds the memory initialization sequence of DDR3.
Signed-off-by: Hatim Ali hatim...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- None
Changes in V3:
- None
Changes in V4:
- None
arch/arm/include/asm/arch-exynos/dmc.h | 65 +
board/samsung/smdk5250/Makefile|2 +-
board/samsung/smdk5250/dmc_common.c| 199 ++
board/samsung/smdk5250/dmc_init.c | 462
board/samsung/smdk5250/dmc_init_ddr3.c | 228
board/samsung/smdk5250/setup.h | 59 -
6 files changed, 551 insertions(+), 464 deletions(-)
create mode 100644 board/samsung/smdk5250/dmc_common.c
delete mode 100644 board/samsung/smdk5250/dmc_init.c
create mode 100644 board/samsung/smdk5250/dmc_init_ddr3.c
diff --git a/arch/arm/include/asm/arch-exynos/dmc.h
b/arch/arm/include/asm/arch-exynos/dmc.h
index bd52d16..f65c676 100644
--- a/arch/arm/include/asm/arch-exynos/dmc.h
+++ b/arch/arm/include/asm/arch-exynos/dmc.h
@@ -251,5 +251,70 @@ struct exynos5_phy_control {
unsigned int phy_con41;
unsigned int phy_con42;
};
+
+enum ddr_mode {
+ DDR_MODE_DDR2,
+ DDR_MODE_DDR3,
+ DDR_MODE_LPDDR2,
+ DDR_MODE_LPDDR3,
+
+ DDR_MODE_COUNT,
+};
+
+enum mem_manuf {
+ MEM_MANUF_AUTODETECT,
+ MEM_MANUF_ELPIDA,
+ MEM_MANUF_SAMSUNG,
+
+ MEM_MANUF_COUNT,
+};
+
+/* CONCONTROL register fields */
+#define CONCONTROL_DFI_INIT_START_SHIFT28
+#define CONCONTROL_RD_FETCH_SHIFT 12
+#define CONCONTROL_RD_FETCH_MASK (0x7 CONCONTROL_RD_FETCH_SHIFT)
+#define CONCONTROL_AREF_EN_SHIFT 5
+
+/* PRECHCONFIG register field */
+#define PRECHCONFIG_TP_CNT_SHIFT 24
+
+/* PWRDNCONFIG register field */
+#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
+#define PWRDNCONFIG_DSREF_CYC_SHIFT16
+
+/* PHY_CON0 register fields */
+#define PHY_CON0_T_WRRDCMD_SHIFT 17
+#define PHY_CON0_T_WRRDCMD_MASK(0x7
PHY_CON0_T_WRRDCMD_SHIFT)
+#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
+
+/* PHY_CON1 register fields */
+#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT0
+
+/* PHY_CON12 register fields */
+#define PHY_CON12_CTRL_START_POINT_SHIFT 24
+#define PHY_CON12_CTRL_INC_SHIFT 16
+#define PHY_CON12_CTRL_FORCE_SHIFT 8
+#define PHY_CON12_CTRL_START_SHIFT 6
+#define PHY_CON12_CTRL_START_MASK (1 PHY_CON12_CTRL_START_SHIFT)
+#define PHY_CON12_CTRL_DLL_ON_SHIFT5
+#define PHY_CON12_CTRL_DLL_ON_MASK (1 PHY_CON12_CTRL_DLL_ON_SHIFT)
+#define PHY_CON12_CTRL_REF_SHIFT 1
+
+/* PHY_CON16 register fields */
+#define PHY_CON16_ZQ_MODE_DDS_SHIFT24
+#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 PHY_CON16_ZQ_MODE_DDS_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
+#define PHY_CON16_ZQ_MODE_TERM_MASK(0x7 PHY_CON16_ZQ_MODE_TERM_SHIFT)
+
+#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 19)
+
+/* PHY_CON42 register fields */
+#define PHY_CON42_CTRL_BSTLEN_SHIFT8
+#define PHY_CON42_CTRL_BSTLEN_MASK (0xff PHY_CON42_CTRL_BSTLEN_SHIFT)
+
+#define PHY_CON42_CTRL_RDLAT_SHIFT 0
+#define PHY_CON42_CTRL_RDLAT_MASK (0x1f PHY_CON42_CTRL_RDLAT_SHIFT)
+
#endif
#endif
diff --git a/board/samsung/smdk5250/Makefile b/board/samsung/smdk5250/Makefile
index 3675fad..1474fa8 100644
--- a/board/samsung/smdk5250/Makefile
+++ b/board/samsung/smdk5250/Makefile
@@ -27,7 +27,7 @@ LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
COBJS := clock_init.o
-COBJS += dmc_init.o
+COBJS += dmc_common.o dmc_init_ddr3.o
COBJS += tzpc_init.o
COBJS += smdk5250_spl.o
diff --git a/board/samsung/smdk5250/dmc_common.c
b/board/samsung/smdk5250/dmc_common.c
new file mode 100644
index 000..109602a
--- /dev/null
+++ b/board/samsung/smdk5250/dmc_common.c
@@ -0,0 +1,199 @@
+/*
+ * Mem setup common file for different types of DDR present on SMDK5250 boards.
+ *
+ * Copyright (C) 2012 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/arch/spl.h
+
+#include clock_init.h
+#include setup.h
+
+#define ZQ_INIT_TIMEOUT1
+
+int dmc_config_zq(struct mem_timings *mem,
+ struct
[U-Boot] [PATCH 08/10 V4] EXYNOS5: CLOCK: Add BPLL support
This patch adds support for BPLL clock.
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V3:
- New Patch
Changes in V4:
- Removed the warning message.
arch/arm/cpu/armv7/exynos/clock.c| 26 --
arch/arm/include/asm/arch-exynos/clk.h |1 +
arch/arm/include/asm/arch-exynos/clock.h |2 ++
3 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index dbd5f11..13e3641 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -98,7 +98,7 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
- unsigned int freq, pll_div2_sel, mpll_fout_sel;
+ unsigned int freq, pll_div2_sel, fout_sel;
switch (pllreg) {
case APLL:
@@ -115,6 +115,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
r = readl(clk-vpll_con0);
k = readl(clk-vpll_con1);
break;
+ case BPLL:
+ r = readl(clk-bpll_con0);
+ break;
default:
printf(Unsupported PLL (%d)\n, pllreg);
return 0;
@@ -125,8 +128,9 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
* MPLL_CON: MIDV [25:16]
* EPLL_CON: MIDV [24:16]
* VPLL_CON: MIDV [24:16]
+* BPLL_CON: MIDV [25:16]
*/
- if (pllreg == APLL || pllreg == MPLL)
+ if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
mask = 0x3ff;
else
mask = 0x1ff;
@@ -155,13 +159,23 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
fout = m * (freq / (p * (1 (s - 1;
}
- /* According to the user manual, in EVT1 MPLL always gives
+ /* According to the user manual, in EVT1 MPLL and BPLL always gives
* 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
- if (pllreg == MPLL) {
+ if (pllreg == MPLL || pllreg == BPLL) {
pll_div2_sel = readl(clk-pll_div2_sel);
- mpll_fout_sel = (pll_div2_sel MPLL_FOUT_SEL_SHIFT)
+
+ switch (pllreg) {
+ case MPLL:
+ fout_sel = (pll_div2_sel MPLL_FOUT_SEL_SHIFT)
MPLL_FOUT_SEL_MASK;
- if (mpll_fout_sel == 0)
+ break;
+ case BPLL:
+ fout_sel = (pll_div2_sel BPLL_FOUT_SEL_SHIFT)
+BPLL_FOUT_SEL_MASK;
+ break;
+ }
+
+ if (fout_sel == 0)
fout /= 2;
}
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index 637fb4b..e99339a 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -27,6 +27,7 @@
#define EPLL 2
#define HPLL 3
#define VPLL 4
+#define BPLL 5
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index bf41c19..fce38ef 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -599,4 +599,6 @@ struct exynos5_clock {
#define MPLL_FOUT_SEL_SHIFT4
#define MPLL_FOUT_SEL_MASK 0x1
+#define BPLL_FOUT_SEL_SHIFT0
+#define BPLL_FOUT_SEL_MASK 0x1
#endif
--
1.7.4.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 10/10 V4] SMDK5250: Enable UART and MMC for Exynos5250 Rev 1.0
This patch sets UART3 and MMC channle 0 for Exynos5250 Rev 1.0
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- None.
Changes in V3:
- None
Changes in V4:
- None
board/samsung/smdk5250/smdk5250.c |6 +++---
include/configs/smdk5250.h|2 +-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/board/samsung/smdk5250/smdk5250.c
index 3b078da..b593325 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -130,13 +130,13 @@ int board_mmc_init(bd_t *bis)
{
int err;
- err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+ err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err) {
- debug(SDMMC2 not configured\n);
+ debug(SDMMC0 not configured\n);
return err;
}
- err = s5p_mmc_init(2, 4);
+ err = s5p_mmc_init(0, 8);
return err;
}
#endif
diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h
index 405abd5..d4d370f 100644
--- a/include/configs/smdk5250.h
+++ b/include/configs/smdk5250.h
@@ -69,7 +69,7 @@
/* select serial console configuration */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_SERIAL1 /* use SERIAL 1 */
+#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_BAUDRATE115200
#define EXYNOS5_DEFAULT_UART_OFFSET0x01
--
1.7.4.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/10 V4] EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0
This patch modifies the pinmux settings of MMC and UART as per
Exynos5250 Rev 1.0.
It also corrects the gpio offset calculations.
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes in V2:
- None.
Changes in V3:
- Corrected the pinmux settings and offset calcuation of gpio banks.
Changes in V4:
- None
arch/arm/cpu/armv7/exynos/pinmux.c | 22 +-
arch/arm/include/asm/arch-exynos/gpio.h |7 +--
2 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c
b/arch/arm/cpu/armv7/exynos/pinmux.c
index d2b7d2c..822410e 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -40,8 +40,8 @@ static void exynos5_uart_config(int peripheral)
count = 4;
break;
case PERIPH_ID_UART1:
- bank = gpio1-a0;
- start = 4;
+ bank = gpio1-d0;
+ start = 0;
count = 4;
break;
case PERIPH_ID_UART2:
@@ -66,23 +66,27 @@ static int exynos5_mmc_config(int peripheral, int flags)
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank, *bank_ext;
- int i;
+ int i, start, gpio_func;
switch (peripheral) {
case PERIPH_ID_SDMMC0:
bank = gpio1-c0;
bank_ext = gpio1-c1;
+ start = 0;
+ gpio_func = GPIO_FUNC(0x2);
break;
case PERIPH_ID_SDMMC1:
- bank = gpio1-c1;
+ bank = gpio1-c2;
bank_ext = NULL;
break;
case PERIPH_ID_SDMMC2:
- bank = gpio1-c2;
- bank_ext = gpio1-c3;
+ bank = gpio1-c3;
+ bank_ext = gpio1-c4;
+ start = 3;
+ gpio_func = GPIO_FUNC(0x3);
break;
case PERIPH_ID_SDMMC3:
- bank = gpio1-c3;
+ bank = gpio1-c4;
bank_ext = NULL;
break;
}
@@ -92,8 +96,8 @@ static int exynos5_mmc_config(int peripheral, int flags)
return -1;
}
if (flags PINMUX_FLAG_8BIT_MODE) {
- for (i = 3; i = 6; i++) {
- s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3));
+ for (i = start; i = (start + 3); i++) {
+ s5p_gpio_cfg_pin(bank_ext, i, gpio_func);
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
}
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 7a9bb90..97be4ea 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -100,7 +100,9 @@ struct exynos5_gpio_part1 {
struct s5p_gpio_bank y4;
struct s5p_gpio_bank y5;
struct s5p_gpio_bank y6;
- struct s5p_gpio_bank res1[0x980];
+ struct s5p_gpio_bank res1[0x3];
+ struct s5p_gpio_bank c4;
+ struct s5p_gpio_bank res2[0x48];
struct s5p_gpio_bank x0;
struct s5p_gpio_bank x1;
struct s5p_gpio_bank x2;
@@ -122,9 +124,10 @@ struct exynos5_gpio_part2 {
struct exynos5_gpio_part3 {
struct s5p_gpio_bank v0;
struct s5p_gpio_bank v1;
+ struct s5p_gpio_bank res1[0x1];
struct s5p_gpio_bank v2;
struct s5p_gpio_bank v3;
- struct s5p_gpio_bank res1[0x20];
+ struct s5p_gpio_bank res2[0x1];
struct s5p_gpio_bank v4;
};
--
1.7.4.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 06/29/2012 02:36 AM, Tetsuyuki Kobayashi wrote: save_boot_params_default() in cpu.c accesses uninitialized stack area when it compiled with -O0 (not optimized). Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp Acked-by: Tom Rini tr...@ti.com - -- Tom -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQIcBAEBAgAGBQJP7boFAAoJENk4IS6UOR1WX18P/i+/SO3IcUVfLfuKHbc60W10 bZO7amiudkVDngroXJUl8jDZ6ersCsawOA+WxkuEOS0SjcwQsU8bfM0XbR7TiQMG XJDpD4/woLzEFjkrSqpw0BTsYadAFJWhLVKIx60+4LTUdcL/JNktaCtsKuXWJI21 yG4lWmzECBGmT1JT3AXT3KtQ0WKKlWVxtPpluw8qniEYnUdiXmKSBC42OqRfJWRc ZJjn7ZLNqszf+C3W4H170vwLcpEEjw6KBi2joSaaaEJrJT/ll6jkZEMP0ZUPxGPo +aJeUVwoUWFsnCuPfIxQ6vNZjDm/slJaTh+B7ZMQ05cNlFYBt/WwSDfJrCnzIgda rHxs8DbNU4z3WCCjIkvFk87WMIR2aNXv0ojpmy7thliP/nJNfDHwbuTZuvQlL+1l keeMfIuGQpeWU+qRPrB92bb+vOmaO3tgKVmXGeJ6eT8h5uDJpMagVdYfe6wVb+Cl ukgQctTWm4L846acHwhOIq2r+GQCTZpVktNgANnZHufMZ2p2uxnRMklZYswJW8Ko +EigMMe3dcw6BgWfwkPK20FdzGT3OBSVuTwbxw6lCJVzITzPQmB/GY2lxUzDmURi x9ssawTWgIAap+OBM7oR9+TOaPRMtkbqWFziClWbwmVgjAxI3k8VFzN+mk1nEcYO KkdqOLTSccjOgKSZH5pn =lr2Y -END PGP SIGNATURE- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Relocation issue on armv7 targets
Dear JagannadhaSutradharudu Teki, In message loom.20120629t174245-...@post.gmane.org you wrote: Does anyone having any idea about this issue. [u-boot XIP is not working because of this relocation issue] I have still debugging able to find some solution but needs some to clarify. Please read http://www.catb.org/~esr/faqs/smart-questions.html especially section http://www.catb.org/~esr/faqs/smart-questions.html#beprecise Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de You get a wonderful view from the point of no return. - Terry Pratchett, _Making_Money_ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] microblaze: Wire up fdt emaclite initialization
Am Freitag, den 29.06.2012, 09:37 +0200 schrieb Michal Simek:
Call emaclite FDT registration when CONFIG_OF_CONTROL is used.
Signed-off-by: Michal Simek mon...@monstr.eu
---
.../xilinx/microblaze-generic/microblaze-generic.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c
b/board/xilinx/microblaze-generic/microblaze-generic.c
index a1e2bfe..4a719ba 100644
--- a/board/xilinx/microblaze-generic/microblaze-generic.c
+++ b/board/xilinx/microblaze-generic/microblaze-generic.c
@@ -73,6 +73,9 @@ int board_eth_init(bd_t *bis)
{
int ret = 0;
+#ifdef CONFIG_OF_CONTROL
+ ret |= xilinx_emaclite_init(bis);
+#else
First of all: I've successful tested on an AXI system on Avnet S6LX9
micro-module.
Now some words to the different configuration strategy. I prefer a
seperation between the ongoing development without device tree support
and the upcoming development with fdt support.
Could you split the development in the context of boards, for example:
OLD: Development w/o fdt in:
- board/xilinx/microblaze-generic/*
- configuration in include/configs/microblaze-generic.h
NEW: Development with fdt in:
- board/xilinx/microblaze-fdt/*
- configuration in include/configs/microblaze-fdt.h
So you can start with a really clean and slimmed board configuration for
fdt development (especially the content of config header) and the old
generic board support would be retained. Anytime in the future, when the
generic configuration will become obsolete you can remove it.
br,
Stephan
#ifdef CONFIG_XILINX_AXIEMAC
ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
XILINX_AXIDMA_BASEADDR);
@@ -125,6 +128,6 @@ int board_eth_init(bd_t *bis)
# endif
# endif
#endif
-
+#endif
return ret;
}
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] ARM CONFIG_OF_CONTROL status
Am Freitag, den 29.06.2012, 10:18 +0200 schrieb Michal Simek:
On 06/29/2012 04:32 AM, Simon Glass wrote:
Hi,
--snip--
I have sent support for Microblaze. Currently without dts because I want to
clear this part a little bit.
Hi Michal,
looks good, I've been waiting a long time on the FDT support in U-Boot
for Microblaze -- great -- PS: see my comment on patch 5 ...
Tegra is using ./arch/arm/dts/tegra20.dtsi and
board/nvidia/dts/tegra2-seaboard.dts
and they are composed together in dts/Makefile by calling preprocessor.
Microblaze will be totally different case because every Microblaze hw design
is different.
Yes, that's right. We will never be in the position to define a skeleton
or a basic platform configuration.
We can use two main buses (little and big endian) and cpu is also
configurable.
Based on this for Microblaze is the best solution directly to use dts.
(DTS for Microblaze is also generated directly from design tool).
... directly in the context of a board, not arch/cpu, right?
Anyway - here is the bug message I am getting if I use full dts in
board/name/dts/microblaze.dts
and empty arch/microblaze/dts/microblaze.dtsi
stdin:34:3: error: invalid preprocessing directive #address
stdin:35:3: error: invalid preprocessing directive #size
stdin:52:4: error: invalid preprocessing directive #address
stdin:53:4: error: invalid preprocessing directive #cpus
stdin:54:4: error: invalid preprocessing directive #size
stdin:155:4: error: invalid preprocessing directive #address
stdin:156:4: error: invalid preprocessing directive #size
stdin:160:5: error: invalid preprocessing directive #gpio
stdin:192:5: error: invalid preprocessing directive #gpio
stdin:209:5: error: invalid preprocessing directive #gpio
stdin:241:5: error: invalid preprocessing directive #gpio
stdin:267:5: error: invalid preprocessing directive #address
stdin:268:5: error: invalid preprocessing directive #size
stdin:394:5: error: invalid preprocessing directive #interrupt
This is error for opposite case - empty microblaze.dts and full
microblaze.dtsi.
That are CPP errors, because the auto generated xilinx.dts is full of
CPP pragma like syntax (#something) that are wrong (invalid).
make[1]: Entering directory `/mnt/projects/u-boot/dts'
rc=$( cat /mnt/projects/u-boot/board/petalogix/dts/microblaze.dts |
microblaze-unknown-linux-gnu-gcc -E
-P
-DARCH_CPU_DTS=\/mnt/projects/u-boot/arch/microblaze/dts/microblaze.dtsi\ -
| { { dtc -R 4 -p 0x1000
-O dtb -o dt.dtb - 21 ; echo $? 3 ; } | grep -v '^DTC: dts-dtb on file'
; } 31 ) ; \
exit $rc
/bin/sh: line 1: exit: too many arguments
make[1]: *** [dt.dtb] Error 1
make[1]: Leaving directory `/mnt/projects/u-boot/dts'
I have just tried to fix it by introducing new CONFIG option for skipping
that preprocessor
part.
Instead of disable / skipp the CPP step you can hide the auto generated
xilinx.dts with a second include stage, for example:
board/microblaze/dts/microblaze.dts looks like:
/include/ ARCH_CPU_DTS
/include/ BOARD_DTS
Right, only two lines. The arch/microblaze/dts/microblaze.dtsi remains
empty as you have said above. Just new is BOARD_DTS -- with the attached
patch for dts/Makefile you can copy the auto generated xilinx.dts into
the specific board directory and the CPP step substitute the right place
to board/microblaze/microblaze-generic/dts/microblaze.dts
I think there are no side effects with other ports like the tegra2.
If you want you can omit the ARCH_CPU_DTS inclusion. The architectural
microblaze.dtsi file is empty and (!!) have to be empty, because the DTC
will break with an error on multiple /dts-v1/; lines!
Here is the patch:
diff --git a/dts/Makefile b/dts/Makefile
index 914e479..b1f47a1 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -36,7 +36,8 @@ $(error Your architecture does not have device tree
support enabled. \
Please define CONFIG_ARCH_DEVICE_TREE))
# We preprocess the device tree file provide a useful define
-DTS_CPPFLAGS := -DARCH_CPU_DTS=
\$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\
+DTS_CPPFLAGS := -DARCH_CPU_DTS=
\$(SRCTREE)/arch/$(ARCH)/dts/$(CONFIG_ARCH_DEVICE_TREE).dtsi\ \
+ -DBOARD_DTS=
\$(SRCTREE)/board/$(VENDOR)/$(BOARD)/dts/$(DEVICE_TREE).dts\
all: $(obj).depend $(LIB)
br,
Stephan
It will be good for Microblaze (probably there is any smarter solution for
SKIP case not to have two cats there).
The same situation will happen for Xilinx ppc support and partially for
upcoming ARM zynq where
full DTS is generated for unique hw design.
Here is the patch to show you what phase I would like to skip.
diff --git a/dts/Makefile b/dts/Makefile
index 914e479..d670cb8 100644
--- a/dts/Makefile
+++ b/dts/Makefile
@@ -45,9 +45,15 @@ all: $(obj).depend $(LIB)
# the filename.
DT_BIN := $(obj)dt.dtb
+ifndef CONFIG_DTS_SKIP_PREPROCESSOR
+SKIP := $(CPP) -P $(DTS_CPPFLAGS) -
+else
+SKIP := cat
+endif
+
[U-Boot] [PATCH] microblaze: add missing undefs for UBI and UBIFS
In the case of missing flash usage disaple (undef) all the UBI support in the same way as for JFFS2. Signed-off-by: Stephan Linz l...@li-pro.net --- include/configs/microblaze-generic.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 2fd2279..2c7ed5d 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -284,6 +284,8 @@ # undef CONFIG_CMD_IMLS # undef CONFIG_CMD_FLASH # undef CONFIG_CMD_JFFS2 +# undef CONFIG_CMD_UBI +# undef CONFIG_CMD_UBIFS #endif #if defined(CONFIG_CMD_JFFS2) -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] nand: Hack to support 4k page in fsl_elbc_nand
On 06/28/2012 09:13 PM, Rafael Beims wrote:
On Thu, Jun 28, 2012 at 10:36 PM, Scott Wood scottw...@freescale.com wrote:
On 06/28/2012 03:47 PM, Rafael Beims wrote:
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip with pagesize larger than 2K bytes,
we read/write 2k data repeatedly by issuing FIR_OP_RB/FIR_OP_WB and save
them to a large buffer.
Because of this, the in flash layout of the oob is different from the
default for 4096kiB page sizes. Therefore, we need to migrate the
factory bad block markers from the original position to the new layout.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
Signed-off-by: Liu Shuo b35...@freescale.com
Signed-off-by: Rafael Beims rafael.be...@datacom.ind.br
---
Changes in v2:
- Added check to disallow the migration code to run in devices with
page size = 2048
drivers/mtd/nand/fsl_elbc_nand.c | 447
+++---
1 files changed, 419 insertions(+), 28 deletions(-)
Thanks for working on this! I've been meaning to for a while, but have
been busy with other things.
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c
b/drivers/mtd/nand/fsl_elbc_nand.c
index 9076ad4..3b6bb1d 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -76,15 +76,17 @@ struct fsl_elbc_ctrl {
/* device info */
fsl_lbc_t *regs;
- u8 __iomem *addr;/* Address of assigned FCM buffer*/
- unsigned int page; /* Last page written to / read from */
- unsigned int read_bytes; /* Number of bytes read during command */
- unsigned int column; /* Saved column from SEQIN */
- unsigned int index; /* Pointer to next byte to 'read'*/
- unsigned int status; /* status read from LTESR after last op */
- unsigned int mdr;/* UPM/FCM Data Register value */
- unsigned int use_mdr;/* Non zero if the MDR is to be set */
- unsigned int oob;/* Non zero if operating on OOB data */
+ u8 __iomem *addr; /* Address of assigned FCM buffer */
+ unsigned int page; /* Last page written to / read from */
+ unsigned int read_bytes;/* Number of bytes read during command */
+ unsigned int column;/* Saved column from SEQIN */
+ unsigned int index; /* Pointer to next byte to 'read' */
+ unsigned int status;/* status read from LTESR after last op */
+ unsigned int mdr; /* UPM/FCM Data Register value */
+ unsigned int use_mdr; /* Non zero if the MDR is to be set */
+ unsigned int oob; /* Non zero if operating on OOB data*/
+ char *buffer; /* Just used when pagesize is greater */
+ /* than FCM RAM 2K limitation */
};
/* These map to the positions used by the FCM hardware ECC generator */
@@ -131,6 +133,15 @@ static struct nand_bbt_descr largepage_memorybased = {
.pattern = scan_ff_pattern,
};
+static u8 migrated_pattern[] = { 0xde, 0xad, 0xde, 0xad };
Let's generate a proper random number here -- or at least a meaningful
ASCII string. Things like the above are too common and invite magic
number collision.
Will do it.
+static int fsl_elbc_migrate_badblocks(struct mtd_info *mtd,
+ struct nand_bbt_descr *bd)
+{
+ struct nand_chip *this = mtd-priv;
+ int len, numblocks, i;
+ int startblock;
+ loff_t from;
+ uint8_t *newoob, *buf;
+
+ struct fsl_elbc_mtd *priv = this-priv;
+ struct fsl_elbc_ctrl *ctrl = priv-ctrl;
+
+ int num_subpages = mtd-writesize / 2048-1;
+ len = mtd-writesize + mtd-oobsize;
+ numblocks = this-chipsize (this-phys_erase_shift - 1);
+ startblock = 0;
+ from = 0;
+
+ newoob = vmalloc(mtd-oobsize);
Even if this were Linux, oobsize should never be big enough to need vmalloc.
+ memset(newoob, 0xff, mtd-writesize+mtd-oobsize);
You're writing beyond the end of that buffer.
I should have reviewed this code better... Will fix that.
+ for (i = startblock; i numblocks; i += 2) {
+ int page = (from this-page_shift) this-pagemask;
+ fsl_elbc_cmdfunc(mtd, NAND_CMD_READ0, 0, page);
+
+ /* As we are already using the hack to read the bytes
+ * from NAND, the original badblock marker is offset
+ * from its original location in the internal buffer.
+ * This is because the hack reads 2048 + 64 and already
+ * positions the spare in the correct region
+ * (after the 4096 offset)
+ */
+ uint8_t *badblock_pattern = (ctrl-buffer+
+ mtd-writesize-(num_subpages*64))+bd-offs;
Spaces around
Re: [U-Boot] [PATCH v4 0/3] AM335x: Add USB support in u-boot.
Dear Harman Sohanpal, These patches add USB support in u-boot for AM335x. The support for host or device is selected depending on the config selected from boards.cfg file. Host mode is selected for USB1 and device mode is selected for USB0. Base addresses are selected accordingly. Gene Zarkhin (1): AM335x : Add USB support for AM335x in u-boot Harman Sohanpal (2): AM335x : Configs to add USB host support. musb_udc : Fix compile warning. Dumb question ... but, can this not be made part of am35x USB ? drivers/usb/musb/Makefile|1 + drivers/usb/musb/am335x.c| 121 ++ drivers/usb/musb/am335x.h| 113 +++ drivers/usb/musb/musb_core.h | 2 + drivers/usb/musb/musb_hcd.h |3 - include/configs/am335x_evm.h | 41 ++ include/usb.h|3 +- 7 files changed, 280 insertions(+), 4 deletions(-) create mode 100644 drivers/usb/musb/am335x.c create mode 100644 drivers/usb/musb/am335x.h Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/3] AM335x: Add USB support in u-boot.
Dear Harman Sohanpal,
On Sat, Jun 30, 2012 at 6:15 AM, Marek Vasut ma...@denx.de wrote:
Dear Harman Sohanpal,
These patches add USB support in u-boot for AM335x.
The support for host or device is selected
depending on the config selected from boards.cfg file.
Host mode is selected for USB1 and device mode is
selected for USB0.
Base addresses are selected accordingly.
Gene Zarkhin (1):
AM335x : Add USB support for AM335x in u-boot
Harman Sohanpal (2):
AM335x : Configs to add USB host support.
musb_udc : Fix compile warning.
Dumb question ... but, can this not be made part of am35x USB ?
Hi Marek,
Well this can always be made part of am35x.c.
But there would be a lot of changes required in the file.
Why? They use different IP block or something?
And also I believe it would not make much sense.
It would require ifdefs at a lot of places.
Best example I can give to support what i said is
that the control register
is at an offset of 4 in am35x and 14 in am335x.
So what, define two sets of register structures and pass them according to CPU
ID.
I am sure adding an ifdef at that place would not seem
good to you to change address from 4 to 14 acc to platform.
well ...
struct regs_a {
uint32_t padding[?];
uint32_t reg;
...
};
struct regs_b {
uint32_t reg;
...
};
Create IO accessors ... like ... my_usb_writel() and my_usb_readl() to read and
write the registers. And those accessors will cover the differences. Or is
there
more?
Is there much pain to add these 2 files?
Yes, duplication of code is always bad.
In my opinion we must need to have a separate file for this.
Why? If it's only about the registers, won't the approach above work?
This is as per my understanding.
It could also cause confusions to some due to name. maybe :)
I'm no omap guru, Tom is. Tom?
Kindly give your thoughts.
Oh my brain is spinning from this :-)
In case still some changes are required, we can think upon it :)
I'm really glad to hear that, let's do our best to find the best possible
solution :-)
Thanks,
Harman
Best regards,
Marek Vasut
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
