Re: [U-Boot] [PATCH] arm, ubifs: fix gcc5.x compiler warning
Hello Tom,
On Mon, 30 Nov 2015 11:28:53 -0500, Tom Rini wrote:
> On Mon, Nov 30, 2015 at 11:03:53AM +0100, Heiko Schocher wrote:
> > Hello Jeroen,
> >
> > Am 30.11.2015 um 10:20 schrieb Jeroen Hofstee:
> > >Hello Heiko,
> > >
> > >On 30-11-15 08:47, Heiko Schocher wrote:
> > >>compiling U-Boot for openrd_base_defconfig with
> > >>gcc 5.x shows the following warning:
> > >>
> > >> CC fs/ubifs/super.o
> > >>In file included from fs/ubifs/ubifs.h:35:0,
> > >> from fs/ubifs/super.c:37:
> > >>fs/ubifs/super.c: In function 'atomic_inc':
> > >>./arch/arm/include/asm/atomic.h:55:2: warning: 'flags' is used
> > >>uninitialized in this function
> > >>[-Wuninitialized]
> > >> local_irq_save(flags);
> > >> ^
> > >>fs/ubifs/super.c: In function 'atomic_dec':
> > >>./arch/arm/include/asm/atomic.h:64:2: warning: 'flags' is used
> > >>uninitialized in this function
> > >>[-Wuninitialized]
> > >> local_irq_save(flags);
> > >> ^
> > >> CC fs/ubifs/sb.o
> > >>[...]
> > >> CC fs/ubifs/lpt.o
> > >>In file included from include/linux/bitops.h:123:0,
> > >> from include/common.h:20,
> > >> from include/ubi_uboot.h:17,
> > >> from fs/ubifs/ubifs.h:37,
> > >> from fs/ubifs/lpt.c:35:
> > >>fs/ubifs/lpt.c: In function 'test_and_set_bit':
> > >>./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used
> > >>uninitialized in this function
> > >>[-Wuninitialized]
> > >> local_irq_save(flags);
> > >> ^
> > >> CC fs/ubifs/lpt_commit.o
> > >>In file included from include/linux/bitops.h:123:0,
> > >> from include/common.h:20,
> > >> from include/ubi_uboot.h:17,
> > >> from fs/ubifs/ubifs.h:37,
> > >> from fs/ubifs/lpt_commit.c:26:
> > >>fs/ubifs/lpt_commit.c: In function 'test_and_set_bit':
> > >>./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used
> > >>uninitialized in this function
> > >>[-Wuninitialized]
> > >> local_irq_save(flags);
> > >> ^
> > >> CC fs/ubifs/scan.o
> > >> CC fs/ubifs/lprops.o
> > >> CC fs/ubifs/tnc.o
> > >>In file included from include/linux/bitops.h:123:0,
> > >> from include/common.h:20,
> > >> from include/ubi_uboot.h:17,
> > >> from fs/ubifs/ubifs.h:37,
> > >> from fs/ubifs/tnc.c:30:
> > >>fs/ubifs/tnc.c: In function 'test_and_set_bit':
> > >>./arch/arm/include/asm/bitops.h:57:2: warning: 'flags' is used
> > >>uninitialized in this function
> > >>[-Wuninitialized]
> > >> local_irq_save(flags);
> > >> ^
> > >> CC fs/ubifs/tnc_misc.o
> > >>
> > >>Fix it.
> > >>
> > >>Signed-off-by: Heiko Schocher
> > >>---
> > >>
> > >> arch/arm/include/asm/atomic.h | 14 +++---
> > >> arch/arm/include/asm/bitops.h | 4 ++--
> > >> 2 files changed, 9 insertions(+), 9 deletions(-)
> > >>
> > >>diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
> > >>index 34c07fe..9b79506 100644
> > >>--- a/arch/arm/include/asm/atomic.h
> > >>+++ b/arch/arm/include/asm/atomic.h
> > >>@@ -32,7 +32,7 @@ typedef struct { volatile int counter; } atomic_t;
> > >> static inline void atomic_add(int i, volatile atomic_t *v)
> > >> {
> > >>-unsigned long flags;
> > >>+unsigned long flags = 0;
> > >> local_irq_save(flags);
> > >> v->counter += i;
> > >>@@ -41,7 +41,7 @@ static inline void atomic_add(int i, volatile atomic_t
> > >>*v)
> > >
> > >Since flags is an "out" argument, something else must be wrong.
> > >There should be no need to initialize it, since local_irq_save should
> > >do that afaik.
> >
> > yes, you are right, it should be, but gcc 5.x seems to have problems
> > with it ... compiled code size for the openrd_base config is same with
> > my patch ...
> >
> > Hmm... for the openrd_base compile local_irq_save() is used from:
> > arch/arm/thumb1/include/asm/proc-armv/system.h
> >
> > with:
> > static inline void local_irq_save(
> > unsigned long flags __attribute__((unused)))
> > {
> > __asm__ __volatile__ ("" : : : "memory");
> > }
> >
> > flasg marked as unused ... seems correct to me, but I have
> > no idea, why gcc 5.x prints a warning ... any ideas?
>
> Well, gcc does get more vigerous in its checking now and yeah, it feels
> like it's flagging false positives. In this case I think the answer is
> that we need to nop out the various calls a bit harder on ARM. Glancing
> at the kernel, I think for thumb1 we should just do what we do for
> non-thumb, or translate that into thumb1 only code.
Not sure I'm following what you mean, both about nop-ing out and about
thumb-1. Can you clarify?
> Tom
Amicalement,
--
Albert.
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Re: [U-Boot] [PATCH v5 00/21] Bring up rk3036 uboot
Hey Simon, On Mon, 2015-11-30 at 16:17 -0700, Simon Glass wrote: > Hi Sjeord, > Yes. Maybe some #ifdefs for each subsystem in > rk3288_pinctrl_request() > would help. > > But in general it is too close to the limit. With the bug-fixed gcc > it > is fine, but we are stuck with the bug for a while. ooi do you have a reference to that gcc bug ? :) > Would be great if we could move to tiny printf(). Adding sprintf() > requires refactoring but should be doable. Yeah, though it didn't seem to hard to get rid of the sprintf usage in the calling code either.. > Regards, > Simon > > > > > > Hi, > > > > > > On 15 November 2015 at 16:58, hl wrote: > > > > Hi Simon, > > > > > > > > > > > > On 14/11/15 02:14, Simon Glass wrote: > > > > > > > > > > Hi Lin, > > > > > > > > > > On 10 November 2015 at 03:24, Lin Huang > > > > > wrote: > > > > > > > > > > > > This series patch bring up rk3036 uboot, since rk3036 only > > > > > > 4K > > > > > > size > > > > > > SRAM for SPL, so in SPL stage only support timer, uart, > > > > > > sdram > > > > > > driver, > > > > > > and back to bootrom when finish ddr initial, and boot up > > > > > > second > > > > > > stage > > > > > > from bootrom.You can boot to command line(mmc info etc) for > > > > > > now > > > > > > use > > > > > > this patchset. > > > > > > > > > > > > Jeffy Chen (2): > > > > > > rockchip: Add max init size & chip tag configs > > > > > > rockchip: Add support for rk's second level loader > > > > > > > > > > > > Lin Huang (19): > > > > > > rockchip: add timer driver > > > > > > rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig > > > > > > rockchip: rename board-spl.c to rk3288-board-spl.c > > > > > > rockchip: add config decide whether to build common.c > > > > > > dm: core: Add SPL Kconfig for REGMAP and SYSCON > > > > > > rockchip: serial driver support rk3036 > > > > > > rockchip: Bring in RK3036 device tree file includes and > > > > > > bindings > > > > > > rockchip: rk3036: Add clock driver > > > > > > rockchip: rk3036: Add header files for GRF > > > > > > rockchip: rk3036: Add Soc reset driver > > > > > > rockchip: rk3036: Add a simple syscon driver > > > > > > rockchip: rk3036: Add pinctrl driver > > > > > > mmc: dw_mmc: support fifo mode in dwc mmc driver > > > > > > rockchip: mmc: get the fifo mode and fifo depth property > > > > > > from dts > > > > > > rockchip: add early uart driver > > > > > > rockchip: add rk3036 sdram driver > > > > > > rockchip: rk3036: Add core Soc start-up code > > > > > > rockchip: Add basic support for evb-rk3036 board > > > > > > rockchip: doc: show packet rk3036 uboot image > > > > > > > > > > > > arch/arm/dts/Makefile | 3 > > > > > > +- > > > > > > arch/arm/dts/rk3036-sdk.dts | 46 > > > > > > ++ > > > > > > arch/arm/dts/rk3036.dtsi | 428 > > > > > > > > > > > > arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 > > > > > > + > > > > > > arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 > > > > > > ++ > > > > > > arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 > > > > > > ++ > > > > > > arch/arm/include/asm/arch-rockchip/timer.h| 22 + > > > > > > arch/arm/include/asm/arch-rockchip/uart.h | 44 > > > > > > ++ > > > > > > arch/arm/mach-rockchip/Kconfig| 24 > > > > > > +- > > > > > > arch/arm/mach-rockchip/Makefile | 10 > > > > > > +- > > > > > > arch/arm/mach-rockchip/board-spl.c| 294 > > > > > > --- > > > > > > -- > > > > > > arch/arm/mach-rockchip/board.c| 1 + > > > > > > arch/arm/mach-rockchip/rk3036-board-spl.c | 53 > > > > > > ++ > > > > > > arch/arm/mach-rockchip/rk3036/Kconfig | 23 + > > > > > > arch/arm/mach-rockchip/rk3036/Makefile| 13 + > > > > > > arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 > > > > > > ++ > > > > > > arch/arm/mach-rockchip/rk3036/save_boot_param.S | 34 + > > > > > > arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 766 > > > > > > ++ > > > > > > arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + > > > > > > arch/arm/mach-rockchip/rk3288-board-spl.c | 277 > > > > > > > > > > > > arch/arm/mach-rockchip/rk3288/Kconfig | 9 + > > > > > > arch/arm/mach-rockchip/rk_early_print.c | 56 > > > > > > ++ > > > > > > arch/arm/mach-rockchip/rk_timer.c | 48 > > > > > > ++ > > > > > > board/evb_rk3036/evb_rk3036/Kconfig | 15 + > > > > > > board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 > > > > > > board/evb_rk3036/evb_rk3036/Makefile | 7 + > > > > > > board/evb_rk3036/evb_rk3036/evb_rk3036.c | 48 > > > > > > ++ > > > > > > configs/chromebook_jerry_defconfig
Re: [U-Boot] [PATCH] dm: core: Enable SPL_SIMPLE_BUS by default
Hi Michal, On 01.12.2015 08:39, Michal Simek wrote: This option is needed for all SoCs which have nodes on bus. Without enabling this drivers are not found and probed. Issue was found on Zynq MMC probe. Enable this option by default. Signed-off-by: Michal Simek --- drivers/core/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 15681df6d379..74eee1066092 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -115,7 +115,7 @@ config SIMPLE_BUS config SPL_SIMPLE_BUS bool "Support simple-bus driver in SPL" depends on SPL_DM && SPL_OF_CONTROL - default n + default y help Supports the 'simple-bus' driver, which is used on some systems in SPL. I stumbled over this missing option while porting DM_SPL to mvebu as well. So: Reviewed-by: Stefan Roese Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM: zynq: Enable debug console for zc702
Signed-off-by: Michal Simek --- configs/zynq_zc702_defconfig | 4 1 file changed, 4 insertions(+) diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index 5f7637a26492..8c216c9f8dc4 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -17,4 +17,8 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHYLIB=y CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0001000 +CONFIG_DEBUG_UART_CLOCK=5000 CONFIG_ZYNQ_QSPI=y -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] dm: core: Enable SPL_SIMPLE_BUS by default
This option is needed for all SoCs which have nodes on bus. Without enabling this drivers are not found and probed. Issue was found on Zynq MMC probe. Enable this option by default. Signed-off-by: Michal Simek --- drivers/core/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 15681df6d379..74eee1066092 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -115,7 +115,7 @@ config SIMPLE_BUS config SPL_SIMPLE_BUS bool "Support simple-bus driver in SPL" depends on SPL_DM && SPL_OF_CONTROL - default n + default y help Supports the 'simple-bus' driver, which is used on some systems in SPL. -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board
Hi Yuan
On 01/12/15 01:41 AM, Yuantian Tang wrote:
Hi Sinan Akman,
-Original Message-
From: Sinan Akman [mailto:si...@writeme.com]
Sent: Tuesday, December 01, 2015 2:29 PM
To: Tang Yuantian-B29983 ; Sun York-R58495
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
ARMv8 board
Hi Yuan
On 01/12/15 01:16 AM, Yuantian Tang wrote:
Hi Sinan Akman,
Please see my explanation inline.
-Original Message-
From: Sinan Akman [mailto:si...@writeme.com]
Sent: Tuesday, December 01, 2015 1:28 AM
To: Tang Yuantian-B29983 ; Sun
York-R58495
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
ARMv8 board
Hi Yuan
On 30/11/15 02:44 AM, yuantian.t...@freescale.com wrote:
From: Tang Yuantian
Freescale ARM-based Layerscape contains a SATA controller which
comply with the serial ATA 3.0 specification and the AHCI 1.3
specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: Tang Yuantian
---
v4:
- rebase to lastest git tree
- add another ARMv8 platform which is ls1043aqds
v3:
- rename ls2085a to ls2080a
- rebase to the latest git tree
- replace the magic number with micro variable
v2:
- rebase to the latest git tree
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43
+++
arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++
arch/arm/include/asm/arch-fsl-layerscape/soc.h| 31
include/configs/ls1043aqds.h | 17 +
4 files changed, 109 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8896b70..574ffc4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -6,6 +6,8 @@
#include
#include
+#include
+#include
#include
#include
#include
@@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
}
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+ struct ccsr_ahci __iomem *ccsr_ahci;
+
+ ccsr_ahci = (void *)CONFIG_SYS_SATA2;
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ccsr_ahci = (void *)CONFIG_SYS_SATA1;
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ahci_init((void __iomem *)CONFIG_SYS_SATA1);
+ scsi_scan(0);
+
+ return 0;
+}
+#endif
+
#elif defined(CONFIG_LS1043A)
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+ struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
+
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ahci_init((void __iomem *)CONFIG_SYS_SATA);
+ scsi_scan(0);
+
+ return 0;
+}
+#endif
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400
*)CONFIG_SYS_CCI400_ADDR; @@ -141,6 +180,10 @@ void
fsl_lsch2_early_init_f(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ sata_init();
+#endif
+
return 0;
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b5a2d28..be3acc3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -54,6 +54,24 @@
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR
+ 0x0220)
+#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR
+ 0x0221)
Why do we have CONFIG_SYS_SATA1 and CONFIG_SYS_SATA2 here
and
then CONFIG_SYS_SATA in another file (see later below)?
CONFIG_SYS_SATA1 and CONFIG_SYS_SATA seem to have the same
macro
value : (CONFIG_SYS_IMMR + 0x0220)
normally we put all those definitions in board specific head file.
but config.h is created for all layerscape ARMv8 board too which include
ls2080a and ls1043a.
So I add those definitions here for ls2080a to avoid defining them in every
ls2080a board head file.
For ls1043a, only ls1043aqds supports SATA, so, I put all those definitions in
board head file which is the normal way.
What is the real reason ls1043aqds is not using that config.h ?
Config.h is used for both ls1043aqds and ls1043ardb. Since ls1043ardb doesn't
support SATA, it's better to not us
Re: [U-Boot] [PATCH 2/2] altera_qspi: fix erase and write error code
On Sun, 2015-11-29 at 19:38 +0800, Thomas Chou wrote: > Fix erase and write error code, which should be "protected". > > Signed-off-by: Thomas Chou > --- > drivers/mtd/altera_qspi.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Acked-by: Chin Liang See Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] common: board_f: Dont relocate FDT incase of CONFIG_OF_EMBED
On 1.12.2015 00:17, Simon Glass wrote:
> Hi Michal,
>
> On 27 November 2015 at 00:28, Michal Simek wrote:
>> From: Siva Durga Prasad Paladugu
>>
>> Don't relocate fdt in case of CONFIG_OF EMBED as the fdt is
>> already embedded with u-boot image. Also update the fdt_blob
>> correctly in this case
>>
>> Signed-off-by: Siva Durga Prasad Paladugu
>> Signed-off-by: Michal Simek
>> Reviewed-by: Alexey Brodkin
>> ---
>>
>> Changes in v2:
>> - Fix commit message reported by Alexey
>>
>> common/board_f.c | 11 +--
>> 1 file changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/common/board_f.c b/common/board_f.c
>> index b035c90ff3b7..91bf8beea1c6 100644
>> --- a/common/board_f.c
>> +++ b/common/board_f.c
>> @@ -508,7 +508,7 @@ static int reserve_global_data(void)
>> return 0;
>> }
>>
>> -static int reserve_fdt(void)
>> +static int __maybe_unused reserve_fdt(void)
>> {
>> /*
>> * If the device tree is sitting immediately above our image then we
>> @@ -658,7 +658,7 @@ static int setup_dram_config(void)
>> return 0;
>> }
>>
>> -static int reloc_fdt(void)
>> +static int __maybe_unused reloc_fdt(void)
>> {
>> if (gd->flags & GD_FLG_SKIP_RELOC)
>> return 0;
>> @@ -687,6 +687,9 @@ static int setup_reloc(void)
>> gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
>> #endif
>> #endif
>> +#ifdef CONFIG_OF_EMBED
>> + gd->fdt_blob += gd->reloc_off;
>> +#endif
>> memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
>>
>> debug("Relocation Offset is: %08lx\n", gd->reloc_off);
>> @@ -938,7 +941,9 @@ static init_fnc_t init_sequence_f[] = {
>> #endif
>> setup_machine,
>> reserve_global_data,
>> +#ifndef CONFIG_OF_EMBED
>> reserve_fdt,
>> +#endif
>
> Can you please put the #ifdef in the function? At some point we are
> hoping to get rid of all these #ifdefs.
Do you think that this is the best way how to handle this?
We are targeting small uboot running from OCM on Zynq. Moving ifdef to
function itself will caused that we will waste some bytes which do nothing.
Reference in table stays there and then return from that function too.
It it is not huge but this way seems to me better.
But no problem to change it if you think that this is the best way how
to handle this.
Thanks,
Michal
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Re: [U-Boot] [PATCH 12/14] net: gem: Move driver to DM
Hi Simon,
On 1.12.2015 00:17, Simon Glass wrote:
> Hi Michal,
>
...
>> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
>> index e169b774932a..5ea992a3ce65 100644
>> --- a/drivers/mmc/zynq_sdhci.c
>> +++ b/drivers/mmc/zynq_sdhci.c
>> @@ -33,6 +33,23 @@ int zynq_sdhci_init(phys_addr_t regbase)
>> return 0;
>> }
>>
>> +
>> +
>> +static const struct udevice_id arasan_sdhci_ids[] = {
>> + { .compatible = "arasan,sdhci-8.9a" },
>> + { }
>> +};
>> +
>> +U_BOOT_DRIVER(arasan_sdhci_drv) = {
>> + .name = "rockchip_dwmmc",
>> + .id = UCLASS_MMC,
>> + .of_match = rockchip_dwmmc_ids,
>> + .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
>> + .probe = rockchip_dwmmc_probe,
>> + .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
>> +};
>> +
>> +
>
> This seems unrelated / also rockchip stuff.
I reported it in my reply that this was added by accident. As you know I
am playing with SD DM and rockchip was that guy I use for inspiration.
>
>> #if CONFIG_IS_ENABLED(OF_CONTROL)
>> int zynq_sdhci_of_init(const void *blob)
>> {
>> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
>> index 4e93707c7ab1..f2a14938036f 100644
>> --- a/drivers/net/zynq_gem.c
>> +++ b/drivers/net/zynq_gem.c
>> @@ -13,6 +13,7 @@
>> #include
>> #include
>> #include
>> +#include
>
> Can you put up higher so that these are in order?
sure
...
>>
>> - miiphy_register(dev->name, zynq_gem_miiphy_read,
>> zynq_gem_miiphy_write);
>> - priv->bus = miiphy_get_dev_by_name(dev->name);
>> +static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
>> +{
>> + struct eth_pdata *pdata = dev_get_platdata(dev);
>> + struct zynq_gem_priv *priv = dev_get_priv(dev);
>> + int offset = 0;
>>
>> - ret = zynq_phy_init(dev);
>> - if (ret)
>> - return ret;
>> + pdata->iobase = (phys_addr_t)dev_get_addr(dev);
>> + priv->iobase = (struct zynq_gem_regs *)dev_get_addr(dev);
>
> Better to use:
>
> priv->iobase = (struct zynq_gem_regs *)pdata->iobase
>
> I think. But is pdata->iobase ever used?
That was one think I wanted to check. There is eth_pdata structure which
has iobase, enetaddr and phy_interface.
I do fill them here but driver is using iobase saved in private
structure. I do need more information from private structure that's why
I don't need to load it from pdata structure.
I probably also miss to allocate pdata. Is this required?
.platdata_auto_alloc_size = sizeof(struct eth_pdata)
Can you please check logic around pdata if I use it right?
>> + /* Hardcode for now */
>> + priv->emio = 0;
>> +
>> + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
>> + "phy-handle");
>> + if (offset != -1)
>
> I think this should be:
>
> offset > 0
ok. Will fix it.
Thanks,
Michal
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Re: [U-Boot] [PATCH 1/2] altera_qspi: add lock unlock ops
On Sun, 2015-11-29 at 19:38 +0800, Thomas Chou wrote: > Add lock() and unlock() mtd ops to altera_qspi. > > Signed-off-by: Thomas Chou > --- > drivers/mtd/altera_qspi.c | 82 > +++ > 1 file changed, 82 insertions(+) > Acked-by: Chin Liang See As agreed with Marek, it would be great that some of the magic number can be converted as defines. FYI, I am opening both Quad SPI controller spec and EPCQ spec to review this :) Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board
Hi Yuan
On 01/12/15 01:16 AM, Yuantian Tang wrote:
Hi Sinan Akman,
Please see my explanation inline.
-Original Message-
From: Sinan Akman [mailto:si...@writeme.com]
Sent: Tuesday, December 01, 2015 1:28 AM
To: Tang Yuantian-B29983 ; Sun York-R58495
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
ARMv8 board
Hi Yuan
On 30/11/15 02:44 AM, yuantian.t...@freescale.com wrote:
From: Tang Yuantian
Freescale ARM-based Layerscape contains a SATA controller which comply
with the serial ATA 3.0 specification and the AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds
boards.
Signed-off-by: Tang Yuantian
---
v4:
- rebase to lastest git tree
- add another ARMv8 platform which is ls1043aqds
v3:
- rename ls2085a to ls2080a
- rebase to the latest git tree
- replace the magic number with micro variable
v2:
- rebase to the latest git tree
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43
+++
arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++
arch/arm/include/asm/arch-fsl-layerscape/soc.h| 31
include/configs/ls1043aqds.h | 17 +
4 files changed, 109 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8896b70..574ffc4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -6,6 +6,8 @@
#include
#include
+#include
+#include
#include
#include
#include
@@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
}
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+ struct ccsr_ahci __iomem *ccsr_ahci;
+
+ ccsr_ahci = (void *)CONFIG_SYS_SATA2;
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ccsr_ahci = (void *)CONFIG_SYS_SATA1;
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ahci_init((void __iomem *)CONFIG_SYS_SATA1);
+ scsi_scan(0);
+
+ return 0;
+}
+#endif
+
#elif defined(CONFIG_LS1043A)
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+ struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
+
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ahci_init((void __iomem *)CONFIG_SYS_SATA);
+ scsi_scan(0);
+
+ return 0;
+}
+#endif
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400
*)CONFIG_SYS_CCI400_ADDR; @@ -141,6 +180,10 @@ void
fsl_lsch2_early_init_f(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ sata_init();
+#endif
+
return 0;
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b5a2d28..be3acc3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -54,6 +54,24 @@
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR
+ 0x0220)
+#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR
+ 0x0221)
Why do we have CONFIG_SYS_SATA1 and CONFIG_SYS_SATA2 here and
then CONFIG_SYS_SATA in another file (see later below)?
CONFIG_SYS_SATA1 and CONFIG_SYS_SATA seem to have the same macro
value : (CONFIG_SYS_IMMR + 0x0220)
normally we put all those definitions in board specific head file.
but config.h is created for all layerscape ARMv8 board too which include
ls2080a and ls1043a.
So I add those definitions here for ls2080a to avoid defining them in every
ls2080a board head file.
For ls1043a, only ls1043aqds supports SATA, so, I put all those definitions in
board head file which is the normal way.
What is the real reason ls1043aqds is not using that config.h ?
Regards
Sinan Akman
It may lead to a little confusion, but I think it is acceptable.
Regards,
Yuantian
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE
(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+
CONFIG_SYS_SCSI_MAX_LUN)
+
/* Generic Interrupt Controller Definitions */
#define GICD_BASE0x0600
#define GICR_BASE0x061
Re: [U-Boot] [PATCH 1/2] rockchip: add CONFIG_SPL_ROCKCHIP_SERIAL
Hi Simon, On 27/11/15 11:37, Simon Glass wrote: Hi Lin, On 26 November 2015 at 19:35, Simon Glass wrote: Hi Lin, On 19 November 2015 at 22:58, Lin Huang wrote: we can use this config to disable rockchip serial driver in SPL stage, since some rockchip soc sram size is small(rk3036 etc), so we don't want rockchip serial driver build in SPL, but we still want use common debug driver in SPL. Signed-off-by: Lin Huang --- arch/arm/mach-rockchip/Kconfig | 3 +++ drivers/serial/Makefile | 2 +- include/configs/rk3288_common.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index ccff81a..595263c 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -59,6 +59,9 @@ config DM_GPIO config ROCKCHIP_SERIAL default y +config SPL_ROCKCHIP_SERIAL + default n + It will already default to 'n', so this can be omitted. Also you should add this new CONFIG to drivers/serial/Kconfig, below the existing (non-SPL) one. source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 1818c7c..73e30c6 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,7 +41,7 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o -obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o +obj-$(CONFIG_$(SPL_)ROCKCHIP_SERIAL) += serial_rockchip.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 74c7ee1..7f3d1ee 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -30,6 +30,7 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_ROCKCHIP_SERIAL You should add this to the rk3288 defconfig files, instead of here. Kconfig items should not be added to config header files - in fact we plan to eventually remove the config header files. #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SPL_BOARD_INIT -- 1.9.1 Actually, serial_rockchip.c has been removed in mainline. So you may not need this patch, or maybe it can be reduced in size. Please check the current u-boot-rockchip/master. i cherry-pick the [PATCH 2/2] rockchip: rk3036: enable CONFIG_DEBUG_UART, and use ns16550 uart driver in u-boot-rockchip/master branch, build it, but fail, it is will call hang() in arch/arm/lib/div0, so i need to define CONFIG_SPL_LIBGENERIC_SUPPORT, but if i do it, the spl size too big. Regards, Simon -- Lin Huang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board
Hi Sinan Akman,
> -Original Message-
> From: Sinan Akman [mailto:si...@writeme.com]
> Sent: Tuesday, December 01, 2015 2:29 PM
> To: Tang Yuantian-B29983 ; Sun York-R58495
>
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
> ARMv8 board
>
>
>Hi Yuan
>
> On 01/12/15 01:16 AM, Yuantian Tang wrote:
> > Hi Sinan Akman,
> >
> > Please see my explanation inline.
> >
> >> -Original Message-
> >> From: Sinan Akman [mailto:si...@writeme.com]
> >> Sent: Tuesday, December 01, 2015 1:28 AM
> >> To: Tang Yuantian-B29983 ; Sun
> >> York-R58495
> >> Cc: u-boot@lists.denx.de
> >> Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
> >> ARMv8 board
> >>
> >>
> >> Hi Yuan
> >>
> >> On 30/11/15 02:44 AM, yuantian.t...@freescale.com wrote:
> >>> From: Tang Yuantian
> >>>
> >>> Freescale ARM-based Layerscape contains a SATA controller which
> >>> comply with the serial ATA 3.0 specification and the AHCI 1.3
> specification.
> >>> This patch adds SATA feature on ls2080aqds, ls2080ardb and
> >>> ls1043aqds boards.
> >>>
> >>> Signed-off-by: Tang Yuantian
> >>> ---
> >>> v4:
> >>> - rebase to lastest git tree
> >>> - add another ARMv8 platform which is ls1043aqds
> >>> v3:
> >>> - rename ls2085a to ls2080a
> >>> - rebase to the latest git tree
> >>> - replace the magic number with micro variable
> >>> v2:
> >>> - rebase to the latest git tree
> >>>
> >>>arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43
> >> +++
> >>>arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++
> >>>arch/arm/include/asm/arch-fsl-layerscape/soc.h| 31
> >>
> >>>include/configs/ls1043aqds.h | 17 +
> >>>4 files changed, 109 insertions(+)
> >>>
> >>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> index 8896b70..574ffc4 100644
> >>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> @@ -6,6 +6,8 @@
> >>>
> >>>#include
> >>>#include
> >>> +#include
> >>> +#include
> >>>#include
> >>>#include
> >>>#include
> >>> @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
> >>> erratum_a009203();
> >>>}
> >>>
> >>> +#ifdef CONFIG_SCSI_AHCI_PLAT
> >>> +int sata_init(void)
> >>> +{
> >>> + struct ccsr_ahci __iomem *ccsr_ahci;
> >>> +
> >>> + ccsr_ahci = (void *)CONFIG_SYS_SATA2;
> >>> + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> >>> + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
> >>> +
> >>> + ccsr_ahci = (void *)CONFIG_SYS_SATA1;
> >>> + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> >>> + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
> >>> +
> >>> + ahci_init((void __iomem *)CONFIG_SYS_SATA1);
> >>> + scsi_scan(0);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +#endif
> >>> +
> >>>#elif defined(CONFIG_LS1043A)
> >>> +#ifdef CONFIG_SCSI_AHCI_PLAT
> >>> +int sata_init(void)
> >>> +{
> >>> + struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
> >>> +
> >>> + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> >>> + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
> >>> + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
> >>> + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
> >>> +
> >>> + ahci_init((void __iomem *)CONFIG_SYS_SATA);
> >>> + scsi_scan(0);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +#endif
> >>> +
> >>>void fsl_lsch2_early_init_f(void)
> >>>{
> >>> struct ccsr_cci400 *cci = (struct ccsr_cci400
> >>> *)CONFIG_SYS_CCI400_ADDR; @@ -141,6 +180,10 @@ void
> >> fsl_lsch2_early_init_f(void)
> >>>#ifdef CONFIG_BOARD_LATE_INIT
> >>>int board_late_init(void)
> >>>{
> >>> +#ifdef CONFIG_SCSI_AHCI_PLAT
> >>> + sata_init();
> >>> +#endif
> >>> +
> >>> return 0;
> >>>}
> >>>#endif
> >>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>> b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>> index b5a2d28..be3acc3 100644
> >>> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>> @@ -54,6 +54,24 @@
> >>>
> >>>#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
> >>>
> >>> +/* SATA */
> >>> +#define CONFIG_LIBATA
> >>> +#define CONFIG_SCSI_AHCI
> >>> +#define CONFIG_SCSI_AHCI_PLAT
> >>> +#define CONFIG_CMD_SCSI
> >>> +#define CONFIG_CMD_FAT
> >>> +#define CONFIG_CMD_EXT2
> >>> +#define CONFIG_DOS_PARTITION
> >>> +#define CONFIG_BOARD_LATE_INIT
> >>> +
> >>> +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR
> >> + 0x0220)
> >>> +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR
> >> + 0x0221)
> >>
> >> Why do we have CONFIG_SYS_SATA1 and CONFIG_SYS_SATA2 here
> and
> >> then CONFIG_SYS_SATA in another file (see later below)?
> >> CONFIG_SYS_SATA1 and CONFIG_SYS_SATA seem to have the same
> macro
> >> value : (CONFIG_SYS_IMMR
Re: [U-Boot] [PATCH v3 00/16] device model bring-up of ti-qspi on dra72, dra74 and am437x-sk evm
Jagan On Thursday 19 November 2015 12:35 PM, Mugunthan V N wrote: > This patch series enables ti_qspi to adopt driver model. This has > been tested on dra72, dra74 and am437x-sk evms (logs [1]). > Also pushed a branch for testing [2] > > [1]: http://pastebin.ubuntu.com/13341771/ > [2]: git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git qspi-v3 > Gentle ping... Are you Okay with the series to be applied? Regards Mugunthan V N ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] stm32: Convert serial driver to DM
Hi Simon, On Monday, November 30, 2015 04:17:07 PM you wrote: > > + > > + if (((u32)usart & STM32_BUS_MASK) == STM32_APB1PERIPH_BASE) > > + setbits_le32(&STM32_RCC->apb1enr, > > +usart_port_rcc_pairs[usart_port][1]); > > + else if (((u32)usart & STM32_BUS_MASK) == STM32_APB2PERIPH_BASE) > > + setbits_le32(&STM32_RCC->apb2enr, > > +usart_port_rcc_pairs[usart_port][1]); > > Is this some sort of pinmux setting? Shouldn't you add the required > setting to the platdata instead of comparing against a physical > address? > This is the clock gating. The problem is that depending on which bus the peripheral sits on (e.g. APB1, APB2), different register will be used to enable peripheral's clock. I think figuring out the bus within the driver (at least until there is a proper clk driver) is better than relying on board/dt to provide the correct data. At later stage I plan to move clock gating code out of drivers to clk driver, but even there I think this physical address <-> bus lookup could be used. Regarding other points, thanks for the review - I will send v2 shortly. /Kamil ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board
Hi Sinan Akman,
Please see my explanation inline.
> -Original Message-
> From: Sinan Akman [mailto:si...@writeme.com]
> Sent: Tuesday, December 01, 2015 1:28 AM
> To: Tang Yuantian-B29983 ; Sun York-R58495
>
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape
> ARMv8 board
>
>
>Hi Yuan
>
> On 30/11/15 02:44 AM, yuantian.t...@freescale.com wrote:
> > From: Tang Yuantian
> >
> > Freescale ARM-based Layerscape contains a SATA controller which comply
> > with the serial ATA 3.0 specification and the AHCI 1.3 specification.
> > This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds
> > boards.
> >
> > Signed-off-by: Tang Yuantian
> > ---
> > v4:
> > - rebase to lastest git tree
> > - add another ARMv8 platform which is ls1043aqds
> > v3:
> > - rename ls2085a to ls2080a
> > - rebase to the latest git tree
> > - replace the magic number with micro variable
> > v2:
> > - rebase to the latest git tree
> >
> > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43
> +++
> > arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++
> > arch/arm/include/asm/arch-fsl-layerscape/soc.h| 31
>
> > include/configs/ls1043aqds.h | 17 +
> > 4 files changed, 109 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 8896b70..574ffc4 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -6,6 +6,8 @@
> >
> > #include
> > #include
> > +#include
> > +#include
> > #include
> > #include
> > #include
> > @@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
> > erratum_a009203();
> > }
> >
> > +#ifdef CONFIG_SCSI_AHCI_PLAT
> > +int sata_init(void)
> > +{
> > + struct ccsr_ahci __iomem *ccsr_ahci;
> > +
> > + ccsr_ahci = (void *)CONFIG_SYS_SATA2;
> > + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> > + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
> > +
> > + ccsr_ahci = (void *)CONFIG_SYS_SATA1;
> > + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> > + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
> > +
> > + ahci_init((void __iomem *)CONFIG_SYS_SATA1);
> > + scsi_scan(0);
> > +
> > + return 0;
> > +}
> > +#endif
> > +
> > #elif defined(CONFIG_LS1043A)
> > +#ifdef CONFIG_SCSI_AHCI_PLAT
> > +int sata_init(void)
> > +{
> > + struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
> > +
> > + out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
> > + out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
> > + out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
> > + out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
> > +
> > + ahci_init((void __iomem *)CONFIG_SYS_SATA);
> > + scsi_scan(0);
> > +
> > + return 0;
> > +}
> > +#endif
> > +
> > void fsl_lsch2_early_init_f(void)
> > {
> > struct ccsr_cci400 *cci = (struct ccsr_cci400
> > *)CONFIG_SYS_CCI400_ADDR; @@ -141,6 +180,10 @@ void
> fsl_lsch2_early_init_f(void)
> > #ifdef CONFIG_BOARD_LATE_INIT
> > int board_late_init(void)
> > {
> > +#ifdef CONFIG_SCSI_AHCI_PLAT
> > + sata_init();
> > +#endif
> > +
> > return 0;
> > }
> > #endif
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > index b5a2d28..be3acc3 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > @@ -54,6 +54,24 @@
> >
> > #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
> >
> > +/* SATA */
> > +#define CONFIG_LIBATA
> > +#define CONFIG_SCSI_AHCI
> > +#define CONFIG_SCSI_AHCI_PLAT
> > +#define CONFIG_CMD_SCSI
> > +#define CONFIG_CMD_FAT
> > +#define CONFIG_CMD_EXT2
> > +#define CONFIG_DOS_PARTITION
> > +#define CONFIG_BOARD_LATE_INIT
> > +
> > +#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR
> + 0x0220)
> > +#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR
> + 0x0221)
>
>Why do we have CONFIG_SYS_SATA1 and CONFIG_SYS_SATA2 here and
> then CONFIG_SYS_SATA in another file (see later below)?
> CONFIG_SYS_SATA1 and CONFIG_SYS_SATA seem to have the same macro
> value : (CONFIG_SYS_IMMR + 0x0220)
>
normally we put all those definitions in board specific head file.
but config.h is created for all layerscape ARMv8 board too which include
ls2080a and ls1043a.
So I add those definitions here for ls2080a to avoid defining them in every
ls2080a board head file.
For ls1043a, only ls1043aqds supports SATA, so, I put all those definitions in
board head file which is the normal way.
It may lead to a little confusion, but I think it is acceptable.
Regards,
Yuantian
> > +
> > +#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
> > +#define CONFIG_SYS_SCSI_MAX_LUN1
> > +#define CONFIG_SYS_SCSI_MAX_DEVICE
> (CONFI
Re: [U-Boot] [PATCH] dm: core: Add platform specific bus translation function
Hi Simon,
On 01.12.2015 00:17, Simon Glass wrote:
Hi Stefan,
On 29 November 2015 at 23:52, Stefan Roese wrote:
Hi Simon,
On 27.11.2015 19:36, Simon Glass wrote:
On 27 November 2015 at 02:22, Stefan Roese wrote:
This patch adds the additional platform_translate_address() call to
dev_get_addr(). A weak default with a 1-to-1 translation is also
provided. Platforms that need a special address translation can
overwrite this function.
Here the explanation, why this is needed for MVEBU:
When using DM with DT address translation, this does not work
with the standard fdt_translate_address() function on MVEBU
in SPL. Since the DT translates to the 0xf100. base
address for the internal registers. But SPL still has the
registers mapped to the 0xd000. (SOC_REGS_PHY_BASE)
address that is used by the BootROM. This is because SPL
may return to the BootROM for boot continuation (e.g. UART
xmodem boot mode).
Signed-off-by: Stefan Roese
Cc: Simon Glass
Cc: Luka Perkov
Cc: Dirk Eibach
---
drivers/core/device.c | 36 +---
1 file changed, 25 insertions(+), 11 deletions(-)
I wonder if there is a way to handle this with device tree? I would
very much like to avoid adding weak functions and other types of
hooks.
I've thought about this also for quite a bit. But couldn't come
up with a "better", less intrusive implementation for this
problem yet.
Are you saying that there are two values for 'ranges', one in
SPL and one for U-Boot proper?
You can think of it as 2 values for "ranges", yes. Basically
its a difference in the upper 8 bits of all addresses of the
internal registers (e.g. UART, SDRAM controller...).
The BootROM starts with 0xd000. and SPL also needs to
use this value. As SPL returns back into the BootROM in
some cases. And Linux (and other OS'es) expect 0xf100.
as base address. So the main U-Boot reconfigured the base
address to this value quite early.
What actually triggers the change?
This is no change. Its just, that now SPL has added DM and DTS
support. Before this SPL-DM support this was handled by
something like this:
#if defined(CONFIG_SPL_BUILD)
#define SOC_REGS_PHY_BASE 0xd000
#else
#define SOC_REGS_PHY_BASE 0xf100
#endif
#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
#define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
...
And now (nearly) all addresses are taken from the DT. And the
SPL vs. U-Boot proper base address difference needs to get
handled otherwise - here in the DT.
No, I mean what causes the hardware address to move? Is there a
register somewhere that it adjusted to tell the addressing to change?
Yes. U-Boot proper reconfigures this base address. Quite early
in arch_cpu_init(). Note that this change / configuration can't
be detected. So you have to know, where the internal registers
are mapped.
One option would be to have a ranges-spl property, or similar.
Hmmm. you mean to add these "ranges-spl" properties additionally
to the normal "ranges" properties? I would really like to not
change the "ranges" in the dts files. As especially in the
MVEBU cases (Armada XP / 38x etc), the occurrences are very
high. And this would result in quite a big difference to the
"mainline Linux dts" version.
Yes I mean a new property. After all, the existing one is incorrect
for your hardware at least in some configuration.
I could also add this functionality via a new Kconfig option.
Like this:
+ if (CONFIG_IS_ENABLED(PLATFORM_TRANSLATE_ADDRESS)) {
+ addr = platform_translate_address((void *)gd->fdt_blob,
+ dev->of_offset, addr);
+ }
So no weak default would be needed. Just let me know if you
would prefer it this way. And I'll send a v2 using this
approach.
I'd like to exhaust the DT option first, as this adds another level of
complexity...the DT is supposed to describe the hardware.
I understand. But your suggestion of a new "ranges-spl" property
would result in changes to the dts files (for all MVEBU boards)
and additional support for this "ranges-spl" property in the
U-Boot code. This looks more complex than the 2 lines to the
common code I suggested above. And definitely easier to maintain.
As new MVEBU boards would always have to patch their dts files
for U-Boot.
Thanks,
Stefan
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Re: [U-Boot] [PATCH 2/3] mmc: dwmmc: socfpga: Convert to DM
On 30 November 2015 at 11:48, Marek Vasut wrote: > Convert the SoCFPGA shim for registering the DWMMC driver to DM. > > Signed-off-by: Marek Vasut > Cc: Chin Liang See > Cc: Dinh Nguyen > Cc: Pantelis Antoniou > Cc: Simon Glass > Cc: Tom Rini > --- > drivers/mmc/socfpga_dw_mmc.c | 119 --- > 1 file changed, 56 insertions(+), 63 deletions(-) For DM things: Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] arm: socfpga: Enable CONFIG_DM_MMC
On Mon, 2015-11-30 at 20:48 +0100, Marek Vasut wrote: > Enable driver model MMC support on SoCFPGA. > > Signed-off-by: Marek Vasut > Cc: Chin Liang See > Cc: Dinh Nguyen > Cc: Pantelis Antoniou > Cc: Simon Glass > Cc: Tom Rini > --- > configs/socfpga_arria5_defconfig | 1 + > configs/socfpga_cyclone5_defconfig | 1 + > configs/socfpga_de0_nano_soc_defconfig | 1 + > configs/socfpga_mcvevk_defconfig | 1 + > configs/socfpga_sockit_defconfig | 1 + > configs/socfpga_socrates_defconfig | 1 + > 6 files changed, 6 insertions(+) > > Acked-by: Chin Liang See Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] mmc: dwmmc: socfpga: Convert to DM
Hi Marek,
On Mon, 2015-11-30 at 20:48 +0100, Marek Vasut wrote:
> Convert the SoCFPGA shim for registering the DWMMC driver to DM.
>
> Signed-off-by: Marek Vasut
> Cc: Chin Liang See
> Cc: Dinh Nguyen
> Cc: Pantelis Antoniou
> Cc: Simon Glass
> Cc: Tom Rini
> ---
> drivers/mmc/socfpga_dw_mmc.c | 119 -
I cannot applied this successfully to u-boot-socfpga.git. I tried git
am and also patch -1.
> --
> 1 file changed, 56 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/mmc/socfpga_dw_mmc.c
> b/drivers/mmc/socfpga_dw_mmc.c
> index 8076761..dd2b30a 100644
> --- a/drivers/mmc/socfpga_dw_mmc.c
> +++ b/drivers/mmc/socfpga_dw_mmc.c
> @@ -5,20 +5,28 @@
> */
>
> #include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> #include
> +#include
> #include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
>
> static const struct socfpga_clock_manager *clock_manager_base =
> (void *)SOCFPGA_CLKMGR_ADDRESS;
> static const struct socfpga_system_manager *system_manager_base =
> (void *)SOCFPGA_SYSMGR_ADDRESS;
>
> +struct socfpga_dwmmc_priv {
> + struct dwmci_host host;
> +};
> +
There is a new structure added when we add the dts support for drvsel
and smplsel. It's not reflected here.
Thanks
Chin Liang
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Re: [U-Boot] [PATCH 1/3] arm: socfpga: Remove cpu_mmc_init()
On Mon, 2015-11-30 at 20:48 +0100, Marek Vasut wrote: > This function triggers the registration of the dwmmc driver on > SoCFPGA, > but this is not needed in case the driver is correctly probed from > DT. > > Signed-off-by: Marek Vasut > Cc: Chin Liang See > Cc: Dinh Nguyen > Cc: Pantelis Antoniou > Cc: Simon Glass > Cc: Tom Rini > --- > Acked-by: Chin Liang See Thanks Chin Liang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 6/6] dm: x86: Drop the weak cpu_irq_init() function
There are no callers now. Platforms which need to set up interrupts their
own way can implement an interrupt driver. Drop this function.
Signed-off-by: Simon Glass
---
arch/x86/cpu/irq.c | 7 ---
arch/x86/include/asm/irq.h | 10 --
2 files changed, 17 deletions(-)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index e2feba7..324866c 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -83,11 +83,6 @@ static inline void fill_irq_info(struct irq_info *slot, int
bus, int device,
slot->irq[pin - 1].bitmap = irq_router.irq_mask;
}
-__weak void cpu_irq_init(void)
-{
- return;
-}
-
static int create_pirq_routing_table(void)
{
const void *blob = gd->fdt_blob;
@@ -235,8 +230,6 @@ int irq_router_common_init(struct udevice *dev)
{
int ret;
- cpu_irq_init();
-
ret = create_pirq_routing_table();
if (ret) {
debug("Failed to create pirq routing table\n");
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 46e1c31..5b9e673 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -56,16 +56,6 @@ struct pirq_routing {
#define PIRQ_BITMAP0xdef8
/**
- * cpu_irq_init() - Initialize CPU IRQ routing
- *
- * This initializes some platform-specific registers related to IRQ routing,
- * like configuring internal PCI devices to use which PCI interrupt pin,
- * and which PCI interrupt pin is mapped to which PIRQ line. Note on some
- * platforms, such IRQ routing might be hard-coded thus cannot configure.
- */
-void cpu_irq_init(void);
-
-/**
* irq_router_common_init() - Perform common x86 interrupt init
*
* This creates the PIRQ routing table and routes the IRQs
--
2.6.0.rc2.230.g3dd15c0
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[U-Boot] [PATCH 3/6] dm: x86: Add a common PIRQ init function
Most x86 interrupt drivers will want to use the standard PIRQ routing and
table setup. Put this code in a common function so it can be used by those
drivers that want it.
Signed-off-by: Simon Glass
---
arch/x86/cpu/irq.c | 7 ++-
arch/x86/include/asm/irq.h | 7 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 8f59b23..e2feba7 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -231,7 +231,7 @@ static int create_pirq_routing_table(void)
return 0;
}
-int irq_router_probe(struct udevice *dev)
+int irq_router_common_init(struct udevice *dev)
{
int ret;
@@ -249,6 +249,11 @@ int irq_router_probe(struct udevice *dev)
return 0;
}
+int irq_router_probe(struct udevice *dev)
+{
+ return irq_router_common_init(dev);
+}
+
u32 write_pirq_routing_table(u32 addr)
{
if (!pirq_routing_table)
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 74da66e..46e1c31 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -65,4 +65,11 @@ struct pirq_routing {
*/
void cpu_irq_init(void);
+/**
+ * irq_router_common_init() - Perform common x86 interrupt init
+ *
+ * This creates the PIRQ routing table and routes the IRQs
+ */
+int irq_router_common_init(struct udevice *dev);
+
#endif /* _ARCH_IRQ_H_ */
--
2.6.0.rc2.230.g3dd15c0
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[U-Boot] [PATCH 5/6] dm: x86: queensbay: Add an interrupt driver
Add a driver for interrupts on queensbay and move the code currently in
cpu_irq_init() into its probe() method.
Signed-off-by: Simon Glass
---
arch/x86/cpu/queensbay/Makefile | 2 +-
arch/x86/cpu/queensbay/irq.c| 65 +
arch/x86/cpu/queensbay/tnc.c| 37 ---
arch/x86/dts/crownbay.dts | 2 +-
4 files changed, 67 insertions(+), 39 deletions(-)
create mode 100644 arch/x86/cpu/queensbay/irq.c
diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index 660f967..af3ffad 100644
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += fsp_configs.o
+obj-y += fsp_configs.o irq.o
obj-y += tnc.o topcliff.o
diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c
new file mode 100644
index 000..44369f7
--- /dev/null
+++ b/arch/x86/cpu/queensbay/irq.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2014, Bin Meng
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int queensbay_irq_router_probe(struct udevice *dev)
+{
+ struct tnc_rcba *rcba;
+ u32 base;
+
+ base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
+ base &= ~MEM_BAR_EN;
+ rcba = (struct tnc_rcba *)base;
+
+ /* Make sure all internal PCI devices are using INTA */
+ writel(INTA, &rcba->d02ip);
+ writel(INTA, &rcba->d03ip);
+ writel(INTA, &rcba->d27ip);
+ writel(INTA, &rcba->d31ip);
+ writel(INTA, &rcba->d23ip);
+ writel(INTA, &rcba->d24ip);
+ writel(INTA, &rcba->d25ip);
+ writel(INTA, &rcba->d26ip);
+
+ /*
+* Route TunnelCreek PCI device interrupt pin to PIRQ
+*
+* Since PCIe downstream ports received INTx are routed to PIRQ
+* A/B/C/D directly and not configurable, we have to route PCIe
+* root ports' INTx to PIRQ A/B/C/D as well. For other devices
+* on TunneCreek, route them to PIRQ E/F/G/H.
+*/
+ writew(PIRQE, &rcba->d02ir);
+ writew(PIRQF, &rcba->d03ir);
+ writew(PIRQG, &rcba->d27ir);
+ writew(PIRQH, &rcba->d31ir);
+ writew(PIRQA, &rcba->d23ir);
+ writew(PIRQB, &rcba->d24ir);
+ writew(PIRQC, &rcba->d25ir);
+ writew(PIRQD, &rcba->d26ir);
+
+ return irq_router_common_init(dev);
+}
+
+static const struct udevice_id queensbay_irq_router_ids[] = {
+ { .compatible = "intel,queensbay-irq-router" },
+ { }
+};
+
+U_BOOT_DRIVER(queensbay_irq_router_drv) = {
+ .name = "queensbay_intel_irq",
+ .id = UCLASS_IRQ,
+ .of_match = queensbay_irq_router_ids,
+ .probe = queensbay_irq_router_probe,
+};
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index b65906b..75f7adb 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -69,43 +69,6 @@ int arch_early_init_r(void)
return 0;
}
-void cpu_irq_init(void)
-{
- struct tnc_rcba *rcba;
- u32 base;
-
- base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
- base &= ~MEM_BAR_EN;
- rcba = (struct tnc_rcba *)base;
-
- /* Make sure all internal PCI devices are using INTA */
- writel(INTA, &rcba->d02ip);
- writel(INTA, &rcba->d03ip);
- writel(INTA, &rcba->d27ip);
- writel(INTA, &rcba->d31ip);
- writel(INTA, &rcba->d23ip);
- writel(INTA, &rcba->d24ip);
- writel(INTA, &rcba->d25ip);
- writel(INTA, &rcba->d26ip);
-
- /*
-* Route TunnelCreek PCI device interrupt pin to PIRQ
-*
-* Since PCIe downstream ports received INTx are routed to PIRQ
-* A/B/C/D directly and not configurable, we have to route PCIe
-* root ports' INTx to PIRQ A/B/C/D as well. For other devices
-* on TunneCreek, route them to PIRQ E/F/G/H.
-*/
- writew(PIRQE, &rcba->d02ir);
- writew(PIRQF, &rcba->d03ir);
- writew(PIRQG, &rcba->d27ir);
- writew(PIRQH, &rcba->d31ir);
- writew(PIRQA, &rcba->d23ir);
- writew(PIRQB, &rcba->d24ir);
- writew(PIRQC, &rcba->d25ir);
- writew(PIRQD, &rcba->d26ir);
-}
-
int arch_misc_init(void)
{
unprotect_spi_flash();
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 7039332..011f8b5 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -176,7 +176,7 @@
compatible = "intel,pch7";
irq-router {
- compatible = "intel,irq-router";
+ compatible = "intel,queensbay-irq-router";
intel,pirq-config = "pci";
intel,pirq-link = <0x60 8>;
intel,pirq-mask = <0xcee0>;
--
2.6.0.rc
[U-Boot] [PATCH 1/6] dm: x86: Create a driver for x86 interrupts
It seems likely that at some point we will want a generic interrupt uclass.
But this is a big undertaking as it involves unifying code across multiple
architectures.
As a first step, create a simple IRQ uclass and a driver for x86. This can
be generalised later as required.
Adjust pirq_init() to probe this driver, which has the effect of creating
routing tables and setting up the interrupt routing. This is a start
towards making interrupts fit better with driver model.
Signed-off-by: Simon Glass
---
arch/x86/cpu/irq.c | 25 +
include/dm/uclass-id.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 205405b..9b699cf 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -5,6 +5,7 @@
*/
#include
+#include
#include
#include
#include
@@ -232,6 +233,13 @@ static int create_pirq_routing_table(void)
int pirq_init(void)
{
+ struct udevice *dev;
+
+ return uclass_first_device(UCLASS_IRQ, &dev);
+}
+
+int irq_router_probe(struct udevice *dev)
+{
int ret;
cpu_irq_init();
@@ -255,3 +263,20 @@ u32 write_pirq_routing_table(u32 addr)
return copy_pirq_routing_table(addr, pirq_routing_table);
}
+
+static const struct udevice_id irq_router_ids[] = {
+ { .compatible = "intel,irq-router" },
+ { }
+};
+
+U_BOOT_DRIVER(irq_router_drv) = {
+ .name = "intel_irq",
+ .id = UCLASS_IRQ,
+ .of_match = irq_router_ids,
+ .probe = irq_router_probe,
+};
+
+UCLASS_DRIVER(irq) = {
+ .id = UCLASS_IRQ,
+ .name = "irq",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 27fa0b6..ef145af 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -37,6 +37,7 @@ enum uclass_id {
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
UCLASS_I2C_GENERIC, /* Generic I2C device */
UCLASS_I2C_MUX, /* I2C multiplexer */
+ UCLASS_IRQ, /* Interrupt controller */
UCLASS_KEYBOARD,/* Keyboard input device */
UCLASS_LED, /* Light-emitting diode (LED) */
UCLASS_LPC, /* x86 'low pin count' interface */
--
2.6.0.rc2.230.g3dd15c0
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[U-Boot] [PATCH 0/6] dm: x86: Remove pirq_init() and cpu_irq_init()
This series adds an interrupt driver for x86. Since different platforms can implement this in their own way, we no-longer need the platform-specific weak function. We can also dispense with the arch_misc_init() call in some cases. Simon Glass (6): dm: x86: Create a driver for x86 interrupts dm: x86: Set up interrupt routing from interrupt_init() dm: x86: Add a common PIRQ init function dm: x86: quark: Add an interrupt driver dm: x86: queensbay: Add an interrupt driver dm: x86: Drop the weak cpu_irq_init() function arch/x86/cpu/baytrail/valleyview.c | 2 +- arch/x86/cpu/interrupts.c | 9 ++ arch/x86/cpu/irq.c | 32 ++- arch/x86/cpu/qemu/qemu.c | 5 --- arch/x86/cpu/quark/Makefile| 2 +- arch/x86/cpu/quark/irq.c | 49 arch/x86/cpu/quark/quark.c | 27 +--- arch/x86/cpu/queensbay/Makefile| 2 +- arch/x86/cpu/queensbay/irq.c | 65 ++ arch/x86/cpu/queensbay/tnc.c | 39 +-- arch/x86/dts/crownbay.dts | 2 +- arch/x86/dts/galileo.dts | 2 +- arch/x86/include/asm/irq.h | 19 ++- include/configs/qemu-x86.h | 1 - include/dm/uclass-id.h | 1 + 15 files changed, 158 insertions(+), 99 deletions(-) create mode 100644 arch/x86/cpu/quark/irq.c create mode 100644 arch/x86/cpu/queensbay/irq.c -- 2.6.0.rc2.230.g3dd15c0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/6] dm: x86: quark: Add an interrupt driver
Add a driver for interrupts on quark and move the code currently in
cpu_irq_init() into its probe() method.
Signed-off-by: Simon Glass
---
arch/x86/cpu/quark/Makefile | 2 +-
arch/x86/cpu/quark/irq.c| 49 +
arch/x86/cpu/quark/quark.c | 25 ---
arch/x86/dts/galileo.dts| 2 +-
4 files changed, 51 insertions(+), 27 deletions(-)
create mode 100644 arch/x86/cpu/quark/irq.c
diff --git a/arch/x86/cpu/quark/Makefile b/arch/x86/cpu/quark/Makefile
index 8f1d018..6d670d7 100644
--- a/arch/x86/cpu/quark/Makefile
+++ b/arch/x86/cpu/quark/Makefile
@@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += car.o dram.o msg_port.o quark.o
+obj-y += car.o dram.o irq.o msg_port.o quark.o
obj-y += mrc.o mrc_util.o hte.o smc.o
diff --git a/arch/x86/cpu/quark/irq.c b/arch/x86/cpu/quark/irq.c
new file mode 100644
index 000..1f8f909
--- /dev/null
+++ b/arch/x86/cpu/quark/irq.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2015, Bin Meng
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+int quark_irq_router_probe(struct udevice *dev)
+{
+ struct quark_rcba *rcba;
+ u32 base;
+
+ qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
+ base &= ~MEM_BAR_EN;
+ rcba = (struct quark_rcba *)base;
+
+ /*
+* Route Quark PCI device interrupt pin to PIRQ
+*
+* Route device#23's INTA/B/C/D to PIRQA/B/C/D
+* Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
+*/
+ writew(PIRQC, &rcba->rmu_ir);
+ writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
+ &rcba->d23_ir);
+ writew(PIRQD, &rcba->core_ir);
+ writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
+ &rcba->d20d21_ir);
+
+ return irq_router_common_init(dev);
+}
+
+static const struct udevice_id quark_irq_router_ids[] = {
+ { .compatible = "intel,quark-irq-router" },
+ { }
+};
+
+U_BOOT_DRIVER(quark_irq_router_drv) = {
+ .name = "quark_intel_irq",
+ .id = UCLASS_IRQ,
+ .of_match = quark_irq_router_ids,
+ .probe = quark_irq_router_probe,
+};
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index f652d99..3097565 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -7,12 +7,10 @@
#include
#include
#include
-#include
#include
#include
#include
#include
-#include
#include
#include
#include
@@ -341,29 +339,6 @@ int cpu_mmc_init(bd_t *bis)
return pci_mmc_init("Quark SDHCI", mmc_supported);
}
-void cpu_irq_init(void)
-{
- struct quark_rcba *rcba;
- u32 base;
-
- qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
- base &= ~MEM_BAR_EN;
- rcba = (struct quark_rcba *)base;
-
- /*
-* Route Quark PCI device interrupt pin to PIRQ
-*
-* Route device#23's INTA/B/C/D to PIRQA/B/C/D
-* Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
-*/
- writew(PIRQC, &rcba->rmu_ir);
- writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
- &rcba->d23_ir);
- writew(PIRQD, &rcba->core_ir);
- writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
- &rcba->d20d21_ir);
-}
-
int arch_misc_init(void)
{
#ifdef CONFIG_ENABLE_MRC_CACHE
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 3ee9a33..663d03a 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -83,7 +83,7 @@
reg = <0xf800 0 0 0 0>;
irq-router {
- compatible = "intel,irq-router";
+ compatible = "intel,quark-irq-router";
intel,pirq-config = "pci";
intel,pirq-link = <0x60 8>;
intel,pirq-mask = <0xdef8>;
--
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[U-Boot] [PATCH 2/6] dm: x86: Set up interrupt routing from interrupt_init()
At present interrupt routing is set up from arch_misc_init(). We can do it
a little later instead, in interrupt_init().
This removes the manual pirq_init() call. Where the platform does not have
an interrupt router defined in its device tree, no error is generated. Some
platforms do not have this.
Drop pirq_init() since it is no-longer used.
Signed-off-by: Simon Glass
---
arch/x86/cpu/baytrail/valleyview.c | 2 +-
arch/x86/cpu/interrupts.c | 9 +
arch/x86/cpu/irq.c | 7 ---
arch/x86/cpu/qemu/qemu.c | 5 -
arch/x86/cpu/quark/quark.c | 2 +-
arch/x86/cpu/queensbay/tnc.c | 2 +-
arch/x86/include/asm/irq.h | 10 --
include/configs/qemu-x86.h | 1 -
8 files changed, 12 insertions(+), 26 deletions(-)
diff --git a/arch/x86/cpu/baytrail/valleyview.c
b/arch/x86/cpu/baytrail/valleyview.c
index 7299f2c..25382f9 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -50,7 +50,7 @@ int arch_misc_init(void)
mrccache_save();
#endif
- return pirq_init();
+ return 0;
}
int reserve_arch(void)
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index b00ddc0..c40200b 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.c
@@ -12,6 +12,7 @@
*/
#include
+#include
#include
#include
#include
@@ -244,6 +245,14 @@ int disable_interrupts(void)
int interrupt_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ /* Try to set up the interrupt router, but don't require one */
+ ret = uclass_first_device(UCLASS_IRQ, &dev);
+ if (ret && ret != -ENODEV)
+ return ret;
+
/*
* When running as an EFI application we are not in control of
* interrupts and should leave them alone.
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 9b699cf..8f59b23 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -231,13 +231,6 @@ static int create_pirq_routing_table(void)
return 0;
}
-int pirq_init(void)
-{
- struct udevice *dev;
-
- return uclass_first_device(UCLASS_IRQ, &dev);
-}
-
int irq_router_probe(struct udevice *dev)
{
int ret;
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 1f93f72..736d6b1 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -93,11 +93,6 @@ int arch_early_init_r(void)
return 0;
}
-int arch_misc_init(void)
-{
- return pirq_init();
-}
-
#ifdef CONFIG_GENERATE_MP_TABLE
int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
{
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 37ce394..f652d99 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -375,7 +375,7 @@ int arch_misc_init(void)
mrccache_save();
#endif
- return pirq_init();
+ return 0;
}
void board_final_cleanup(void)
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index fb81919..b65906b 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -110,5 +110,5 @@ int arch_misc_init(void)
{
unprotect_spi_flash();
- return pirq_init();
+ return 0;
}
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index 6697da3..74da66e 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -65,14 +65,4 @@ struct pirq_routing {
*/
void cpu_irq_init(void);
-/**
- * pirq_init() - Initialize platform PIRQ routing
- *
- * This initializes the PIRQ routing on the platform and configures all PCI
- * devices' interrupt line register to a working IRQ number on the 8259 PIC.
- *
- * @return 0 if OK, -ve on error
- */
-int pirq_init(void);
-
#endif /* _ARCH_IRQ_H_ */
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index 4258dcb..b0d2ffe 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -14,7 +14,6 @@
#include
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-#define CONFIG_ARCH_MISC_INIT
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_PCI_PNP
--
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Re: [U-Boot] [PATCH v3] arm: ls2080a: Add sata support on qds and rdb board
I have sent the newer version of this patch: http://patchwork.ozlabs.org/patch/549883/ Please have a review. Regards, Yuantian > -Original Message- > From: York Sun [mailto:york...@freescale.com] > Sent: Tuesday, December 01, 2015 3:41 AM > To: Tang Yuantian-B29983 > Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579 > ; Wang Huan-B18965 > > Subject: Re: [PATCH v3] arm: ls2080a: Add sata support on qds and rdb board > > > > On 10/23/2015 12:16 AM, Tang Yuantian wrote: > > Freescale ARM-based Layerscape LS2080A contain a SATA controller which > > comply with the serial ATA 3.0 specification and the AHCI 1.3 > > specification. > > This patch adds SATA feature on ls2080aqds and ls2080ardb boards. > > > > Signed-off-by: Tang Yuantian > > --- > > depends on patches: > > http://patchwork.ozlabs.org/patch/530576/ > > armv8: LS2080A: Rename LS2085A to reflect LS2080A > > http://patchwork.ozlabs.org/patch/530575/ > > armv8: ls2085a: Add support of LS2085A SoC > > v3: > > - rename ls2085a to ls2080a > > - rebase to the latest git tree > > - replace the magic number with micro variable > > v2: > > - rebase to the latest git tree > > > > Yuantian, > > The dependency patches have been updated and merged. Please rebase > your patch and test on the new base git://git.denx.de/u-boot-fsl-qoriq.git > master. > > Thanks. > > York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/7] dm: Expand the uclass for Peripheral Controller Hubs (PCH)
A Peripheral Controller Hub is an Intel concept - it is like the peripherals
on an SoC and is often in a separate chip from the CPU. Even when it is not
it is addressed and used differently. The chip is typically found on the
first PCI device.
We have a very simple uclass to support PCHs. Add a few operations, such as
setting up the devices on the PCH and finding the SPI controller base
address. Also move it into drivers/pch/ since we will be adding a few PCH
drivers.
Signed-off-by: Simon Glass
---
arch/x86/lib/Makefile | 1 -
drivers/Makefile | 1 +
drivers/pch/Makefile | 5 +++
{arch/x86/lib => drivers/pch}/pch-uclass.c | 32 +++
include/pch.h | 66 ++
5 files changed, 104 insertions(+), 1 deletion(-)
create mode 100644 drivers/pch/Makefile
rename {arch/x86/lib => drivers/pch}/pch-uclass.c (53%)
create mode 100644 include/pch.h
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index cd5ecb6..43792bc 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -24,7 +24,6 @@ obj-$(CONFIG_I8254_TIMER) += i8254.o
ifndef CONFIG_DM_PCI
obj-$(CONFIG_PCI) += pci_type1.o
endif
-obj-y += pch-uclass.o
obj-y += pirq_routing.o
obj-y += relocate.o
obj-y += physmem.o
diff --git a/drivers/Makefile b/drivers/Makefile
index c9031f2..acc6af9 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -51,6 +51,7 @@ obj-y += hwmon/
obj-y += misc/
obj-y += pcmcia/
obj-y += dfu/
+obj-$(CONFIG_X86) += pch/
obj-y += rtc/
obj-y += sound/
obj-y += timer/
diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
new file mode 100644
index 000..d69a99c
--- /dev/null
+++ b/drivers/pch/Makefile
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += pch-uclass.o
diff --git a/arch/x86/lib/pch-uclass.c b/drivers/pch/pch-uclass.c
similarity index 53%
rename from arch/x86/lib/pch-uclass.c
rename to drivers/pch/pch-uclass.c
index 20dfa81..09a0107 100644
--- a/arch/x86/lib/pch-uclass.c
+++ b/drivers/pch/pch-uclass.c
@@ -7,10 +7,42 @@
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
+int pch_init(struct udevice *dev)
+{
+ struct pch_ops *ops = pch_get_ops(dev);
+
+ if (!ops->init)
+ return -ENOSYS;
+
+ return ops->init(dev);
+}
+
+int pch_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+ struct pch_ops *ops = pch_get_ops(dev);
+
+ *sbasep = 0;
+ if (!ops->get_sbase)
+ return -ENOSYS;
+
+ return ops->get_sbase(dev, sbasep);
+}
+
+int pch_get_version(struct udevice *dev)
+{
+ struct pch_ops *ops = pch_get_ops(dev);
+
+ if (!ops->get_version)
+ return -ENOSYS;
+
+ return ops->get_version(dev);
+}
+
static int pch_uclass_post_bind(struct udevice *bus)
{
/*
diff --git a/include/pch.h b/include/pch.h
new file mode 100644
index 000..98bb5f2
--- /dev/null
+++ b/include/pch.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __pch_h
+#define __pch_h
+
+struct pch_ops {
+ /**
+* init() - set up the PCH devices
+*
+* This makes sure that all the devices are ready for use. They are
+* not actually started, just set up so that they can be probed.
+*/
+ int (*init)(struct udevice *dev);
+
+ /**
+* get_sbase() - get the address of SBASE
+*
+* @dev:PCH device to check
+* @sbasep: Returns address of SBASE if available, else 0
+* @return 0 if OK, -ve on error (e.g. there is no SBASE)
+*/
+ int (*get_sbase)(struct udevice *dev, ulong *sbasep);
+
+ /**
+* get_version() - get the PCH version (e.g. 7 or 9)
+*
+* @return version, or -1 if unknown
+*/
+ int (*get_version)(struct udevice *dev);
+};
+
+#define pch_get_ops(dev)((struct pch_ops *)(dev)->driver->ops)
+
+/**
+ * pch_init() - init a PCH
+ *
+ * This makes sure that all the devices are ready for use. They are
+ * not actually started, just set up so that they can be probed.
+ *
+ * @dev: PCH device to init
+ * @return 0 if OK, -ve on error
+ */
+int pch_init(struct udevice *dev);
+
+/**
+ * pch_get_sbase() - get the address of SBASE
+ *
+ * @dev: PCH device to check
+ * @sbasep:Returns address of SBASE if available, else 0
+ * @return 0 if OK, -ve on error (e.g. there is no SBASE)
+ */
+int pch_get_sbase(struct udevice *dev, ulong *sbasep);
+
+/**
+ * pch_get_version() - get the PCH version (e.g. 7 or 9)
+ *
+ * @return version, or -ve if unknown/error
+ */
+int pch_get_version(struct udevice *dev);
+
+#endif
--
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[U-Boot] [PATCH 6/7] dm: x86: Add a driver for Intel PCH9
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH9.
Signed-off-by: Simon Glass
---
drivers/pch/Makefile | 1 +
drivers/pch/pch9.c | 41 +
2 files changed, 42 insertions(+)
create mode 100644 drivers/pch/pch9.c
diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
index 33aa727..dde9e86 100644
--- a/drivers/pch/Makefile
+++ b/drivers/pch/Makefile
@@ -4,3 +4,4 @@
obj-y += pch-uclass.o
obj-y += pch7.o
+obj-y += pch9.o
diff --git a/drivers/pch/pch9.c b/drivers/pch/pch9.c
new file mode 100644
index 000..2f40a6b
--- /dev/null
+++ b/drivers/pch/pch9.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+static int baytrail_pch_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+ uint32_t sbase_addr;
+
+ dm_pci_read_config32(dev, 0x54, &sbase_addr);
+ *sbasep = sbase_addr & 0xfe00;
+
+ return 0;
+}
+
+static int baytrail_pch_get_version(struct udevice *dev)
+{
+ return 9;
+}
+
+static const struct pch_ops baytrail_pch_ops = {
+ .get_sbase = baytrail_pch_get_sbase,
+ .get_version= baytrail_pch_get_version,
+};
+
+static const struct udevice_id baytrailpch_ids[] = {
+ { .compatible = "intel,pch9" },
+ { }
+};
+
+U_BOOT_DRIVER(pch9_drv) = {
+ .name = "intel-pch",
+ .id = UCLASS_PCH,
+ .of_match = baytrailpch_ids,
+ .ops= &baytrail_pch_ops,
+};
--
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[U-Boot] [PATCH 7/7] dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.
In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.
While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.
Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.
Signed-off-by: Simon Glass
---
arch/x86/cpu/irq.c | 7 +-
arch/x86/cpu/ivybridge/bd82x6x.c| 11 +++
arch/x86/dts/bayleybay.dts | 160 +++-
arch/x86/dts/broadwell_som-6896.dts | 23 --
arch/x86/dts/chromebook_link.dts| 3 +-
arch/x86/dts/chromebox_panther.dts | 33
arch/x86/dts/crownbay.dts | 150 +
arch/x86/dts/galileo.dts| 98 +++---
arch/x86/dts/minnowmax.dts | 158 ++-
arch/x86/dts/qemu-x86_i440fx.dts| 26 +++---
arch/x86/dts/qemu-x86_q35.dts | 38 +
drivers/spi/ich.c | 115 ++
12 files changed, 409 insertions(+), 413 deletions(-)
diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index 35b29f6..205405b 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -97,6 +97,7 @@ static int create_pirq_routing_table(void)
struct irq_routing_table *rt;
struct irq_info *slot, *slot_base;
int irq_entries = 0;
+ int parent;
int i;
int ret;
@@ -106,7 +107,11 @@ static int create_pirq_routing_table(void)
return -EINVAL;
}
- ret = fdtdec_get_pci_addr(blob, node, FDT_PCI_SPACE_CONFIG,
+ /* TODO(s...@chromium.org): Drop this when PIRQ is a driver */
+ parent = fdt_parent_offset(blob, node);
+ if (parent < 0)
+ return -EINVAL;
+ ret = fdtdec_get_pci_addr(blob, parent, FDT_PCI_SPACE_CONFIG,
"reg", &addr);
if (ret)
return ret;
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 434dfd6..abd59da 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -116,6 +117,15 @@ int bd82x6x_init(void)
return 0;
}
+static int bd82x6x_pch_get_version(struct udevice *dev)
+{
+ return 9;
+}
+
+static const struct pch_ops bd82x6x_pch_ops = {
+ .get_version= bd82x6x_pch_get_version,
+};
+
static const struct udevice_id bd82x6x_ids[] = {
{ .compatible = "intel,bd82x6x" },
{ }
@@ -126,4 +136,5 @@ U_BOOT_DRIVER(bd82x6x_drv) = {
.id = UCLASS_PCH,
.of_match = bd82x6x_ids,
.probe = bd82x6x_probe,
+ .ops= &bd82x6x_pch_ops,
};
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index d3380de..87d809b 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -65,23 +65,6 @@
};
};
- spi {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "intel,ich-spi";
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "winbond,w25q64dw", "spi-flash";
- memory-map = <0xff80 0x0080>;
- rw-mrc-cache {
- label = "rw-mrc-cache";
- reg = <0x006e 0x0001>;
- };
- };
- };
-
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
@@ -133,66 +116,91 @@
0x4200 0x0 0xc000 0xc000 0 0x2000
0x0100 0x0 0x2000 0x2000 0 0xe000>;
- irq-router@1f,0 {
+ pch@1f,0 {
reg = <0xf800 0 0 0 0>;
- compatible = "intel,irq-router";
- intel,pirq-config = "ibase";
- intel,ibase-offset = <0x50>;
- intel,pirq-link = <8 8>;
- intel,pirq-mask = <0xdee0>;
- intel,pirq-routing = <
- /* BayTrail PCI devices */
- PCI_BDF(0, 2, 0) INTA PIRQA
- PCI_BDF(0, 3, 0) INTA PIRQA
- PCI_BDF(0, 16, 0) INTA PIRQA
- PCI_BDF(0, 17, 0) INTA PIRQA
- PCI_BDF(0,
[U-Boot] [PATCH 2/7] dm: pci: Add a function to write a BAR
Add a driver-model version of the pci_write_bar32 function so that this is
supported in the new API.
Signed-off-by: Simon Glass
---
drivers/pci/pci-uclass.c | 8
include/pci.h| 11 +++
2 files changed, 19 insertions(+)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 77d5300..93dcb21 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1053,6 +1053,14 @@ u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
return addr & PCI_BASE_ADDRESS_MEM_MASK;
}
+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr_and_ctrl)
+{
+ int bar;
+
+ bar = PCI_BASE_ADDRESS_0 + barnum * 4;
+ dm_pci_write_config32(dev, bar, addr_and_ctrl);
+}
+
static int _dm_pci_bus_to_phys(struct udevice *ctlr,
pci_addr_t bus_addr, unsigned long flags,
unsigned long skip_mask, phys_addr_t *pa)
diff --git a/include/pci.h b/include/pci.h
index 9e811ca..f04ac99 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1167,6 +1167,17 @@ int pci_get_regions(struct udevice *dev, struct
pci_region **iop,
struct pci_region **memp, struct pci_region **prefp);
/**
+ * dm_pci_write_bar32() - Write the address of a BAR including control bits
+ *
+ * This writes a raw address (with control bits) to a bar
+ *
+ * @dev: PCI device to update
+ * @barnum:BAR number (0-5)
+ * @addr: BAR address with control bits
+ */
+void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr_and_ctrl);
+
+/**
* dm_pci_read_bar32() - read a base address register from a device
*
* @dev: Device to check
--
2.6.0.rc2.230.g3dd15c0
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[U-Boot] [PATCH 5/7] dm: x86: Add a driver for Intel PCH7
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH7.
Signed-off-by: Simon Glass
---
drivers/pch/Makefile | 1 +
drivers/pch/pch7.c | 30 ++
2 files changed, 31 insertions(+)
create mode 100644 drivers/pch/pch7.c
diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile
index d69a99c..33aa727 100644
--- a/drivers/pch/Makefile
+++ b/drivers/pch/Makefile
@@ -3,3 +3,4 @@
#
obj-y += pch-uclass.o
+obj-y += pch7.o
diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c
new file mode 100644
index 000..f1c780c
--- /dev/null
+++ b/drivers/pch/pch7.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+
+static int queensbay_pch_get_version(struct udevice *dev)
+{
+ return 7;
+}
+
+static const struct pch_ops queensbay_pch9_ops = {
+ .get_version= queensbay_pch_get_version,
+};
+
+static const struct udevice_id queensbay_pch_ids[] = {
+ { .compatible = "intel,pch7" },
+ { }
+};
+
+U_BOOT_DRIVER(queensbay_drv) = {
+ .name = "intel-pch",
+ .id = UCLASS_PCH,
+ .of_match = queensbay_pch_ids,
+ .ops= &queensbay_pch9_ops,
+};
--
2.6.0.rc2.230.g3dd15c0
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[U-Boot] [PATCH 3/7] dm: pci: Avoid using pci_bus_to_hose() in the uclass
This function is only available for compatibility with old code. Avoid using it in the uclass. Signed-off-by: Simon Glass --- drivers/pci/pci_auto.c | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 842eafc..c5638e9 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -9,6 +9,7 @@ */ #include +#include #include #include @@ -167,8 +168,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) struct pci_region *pci_prefetch; struct pci_region *pci_io; u16 cmdstat, prefechable_64; - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); pci_mem = ctlr_hose->pci_mem; pci_prefetch = ctlr_hose->pci_prefetch; @@ -248,9 +249,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) struct pci_region *pci_mem; struct pci_region *pci_prefetch; struct pci_region *pci_io; - - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0); + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); pci_mem = ctlr_hose->pci_mem; pci_prefetch = ctlr_hose->pci_prefetch; @@ -311,13 +311,13 @@ int dm_pciauto_config_device(struct udevice *dev) unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev)); unsigned short class; bool enum_only = false; + struct udevice *ctlr = pci_get_controller(dev); + struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); int n; #ifdef CONFIG_PCI_ENUM_ONLY enum_only = true; #endif - /* The root controller has the region information */ - struct pci_controller *ctlr_hose = pci_bus_to_hose(0); pci_mem = ctlr_hose->pci_mem; pci_prefetch = ctlr_hose->pci_prefetch; -- 2.6.0.rc2.230.g3dd15c0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/7] dm: pci: Move pci_bus_to_hose() to compatibility
This function should not be used by driver-model code, so move it to the
compatibility portion.
Signed-off-by: Simon Glass
---
drivers/pci/pci-uclass.c | 16 +---
drivers/pci/pci_compat.c | 15 +++
drivers/pci/pci_internal.h | 11 +++
3 files changed, 27 insertions(+), 15 deletions(-)
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 54b5dbc..77d5300 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -22,7 +22,7 @@
DECLARE_GLOBAL_DATA_PTR;
-static int pci_get_bus(int busnum, struct udevice **busp)
+int pci_get_bus(int busnum, struct udevice **busp)
{
int ret;
@@ -41,20 +41,6 @@ static int pci_get_bus(int busnum, struct udevice **busp)
return ret;
}
-struct pci_controller *pci_bus_to_hose(int busnum)
-{
- struct udevice *bus;
- int ret;
-
- ret = pci_get_bus(busnum, &bus);
- if (ret) {
- debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
- return NULL;
- }
-
- return dev_get_uclass_priv(bus);
-}
-
struct udevice *pci_get_controller(struct udevice *dev)
{
while (device_is_on_pci_bus(dev))
diff --git a/drivers/pci/pci_compat.c b/drivers/pci/pci_compat.c
index dd15eb1..ddaf358 100644
--- a/drivers/pci/pci_compat.c
+++ b/drivers/pci/pci_compat.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include "pci_internal.h"
#define PCI_HOSE_OP(rw, name, size, type) \
int pci_hose_##rw##_config_##name(struct pci_controller *hose, \
@@ -36,3 +37,17 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int
index)
return -1;
return dm_pci_get_bdf(dev);
}
+
+struct pci_controller *pci_bus_to_hose(int busnum)
+{
+ struct udevice *bus;
+ int ret;
+
+ ret = pci_get_bus(busnum, &bus);
+ if (ret) {
+ debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
+ return NULL;
+ }
+
+ return dev_get_uclass_priv(bus);
+}
diff --git a/drivers/pci/pci_internal.h b/drivers/pci/pci_internal.h
index 0867575..c5069f0 100644
--- a/drivers/pci/pci_internal.h
+++ b/drivers/pci/pci_internal.h
@@ -47,4 +47,15 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev,
int sub_bus);
*/
int dm_pciauto_config_device(struct udevice *dev);
+/**
+ * pci_get_bus() - Get a pointer to a bus, given its number
+ *
+ * The bus is probed before use
+ *
+ * @busnum:PCI bus number to look up
+ * @busp: Returns PCI bus on success
+ * @return 0 on success, or -ve error
+ */
+int pci_get_bus(int busnum, struct udevice **busp);
+
#endif
--
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[U-Boot] [PATCH 0/7] dm: x86: Convert ICH driver fully to driver model PCI API
This is a small series to move the ICH driver over to use the driver model
PCI API. It involves creating PCH drivers which the ICH driver can use to
find out its base address.
At present irq-router is the 'PCH' node in most device tree files. This is
not really correct since the router is just one of the functions of the PCH.
Another is the SPI bus. So this series also moves irq-router down a level.
This still works with the same irq-router driver, since it just searches for
the first compatible node it can find.
A driver-model-compatible irq-router driver should be written but that is
left for later.
This series unfortunately needs testing on each board since each has a
separate change. I have tested minnowmax and chromebook_link so far.
Simon Glass (7):
dm: pci: Move pci_bus_to_hose() to compatibility
dm: pci: Add a function to write a BAR
dm: pci: Avoid using pci_bus_to_hose() in the uclass
dm: Expand the uclass for Peripheral Controller Hubs (PCH)
dm: x86: Add a driver for Intel PCH7
dm: x86: Add a driver for Intel PCH9
dm: x86: spi: Convert ICH SPI driver to driver model PCI API
arch/x86/cpu/irq.c | 7 +-
arch/x86/cpu/ivybridge/bd82x6x.c | 11 ++
arch/x86/dts/bayleybay.dts | 160 +++--
arch/x86/dts/broadwell_som-6896.dts| 23 +++--
arch/x86/dts/chromebook_link.dts | 3 +-
arch/x86/dts/chromebox_panther.dts | 33 +++---
arch/x86/dts/crownbay.dts | 150 ++-
arch/x86/dts/galileo.dts | 98 +-
arch/x86/dts/minnowmax.dts | 158 ++--
arch/x86/dts/qemu-x86_i440fx.dts | 26 +++--
arch/x86/dts/qemu-x86_q35.dts | 38 ---
arch/x86/lib/Makefile | 1 -
drivers/Makefile | 1 +
drivers/pch/Makefile | 7 ++
{arch/x86/lib => drivers/pch}/pch-uclass.c | 32 ++
drivers/pch/pch7.c | 30 ++
drivers/pch/pch9.c | 41
drivers/pci/pci-uclass.c | 24 ++---
drivers/pci/pci_auto.c | 14 +--
drivers/pci/pci_compat.c | 15 +++
drivers/pci/pci_internal.h | 11 ++
drivers/spi/ich.c | 115 +
include/pch.h | 66
include/pci.h | 11 ++
24 files changed, 639 insertions(+), 436 deletions(-)
create mode 100644 drivers/pch/Makefile
rename {arch/x86/lib => drivers/pch}/pch-uclass.c (53%)
create mode 100644 drivers/pch/pch7.c
create mode 100644 drivers/pch/pch9.c
create mode 100644 include/pch.h
--
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[U-Boot] [PATCH] drivers: remoteproc: rproc-uclass: Fix check for NULL pointers
Neither uc_pdata->name nor check_name are supposed to be NULL in _rproc_name_is_unique(). if uc_pdata->name is NULL, we are not intialized yet, however if check_data is NULL, we do not have proper data. Further, if either were NULL, strlen will crap out while attempting to derefence NULL. Instead, just check if either of these are NULL and bail out. This should also fix the following coverity scan warnings: *** CID 132281: Null pointer dereferences (FORWARD_NULL) /drivers/remoteproc/rproc-uclass.c: 73 in _rproc_name_is_unique() Reported-by: Tom Rini Signed-off-by: Nishanth Menon --- Test log: http://pastebin.ubuntu.com/13591420/ drivers/remoteproc/rproc-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index a421e12e5d16..200cf61bc948 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -66,7 +66,7 @@ static int _rproc_name_is_unique(struct udevice *dev, const char *check_name = data; /* devices not yet populated with data - so skip them */ - if (!uc_pdata->name && check_name) + if (!uc_pdata->name || !check_name) return 0; /* Return 0 to search further if we dont match */ -- 2.6.2.402.g2635c2b ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] board: atmel: sama5d2_xplained: add SPL support
The sama5d2 Xplained SPL supports the boot medias: spi flash and SD Card. Signed-off-by: Wenyou Yang --- arch/arm/mach-at91/Kconfig |1 + arch/arm/mach-at91/Makefile |1 + arch/arm/mach-at91/include/mach/sama5d2.h | 32 +++ board/atmel/sama5d2_xplained/sama5d2_xplained.c | 103 +++ configs/sama5d2_xplained_mmc_defconfig |1 + configs/sama5d2_xplained_spiflash_defconfig |1 + include/configs/sama5d2_xplained.h | 39 + 7 files changed, 178 insertions(+) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c333647..9426302b 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -74,6 +74,7 @@ config TARGET_AT91SAM9X5EK config TARGET_SAMA5D2_XPLAINED bool "SAMA5D2 Xplained board" select CPU_V7 + select SUPPORT_SPL config TARGET_SAMA5D3_XPLAINED bool "SAMA5D3 Xplained board" diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 5b89617..abd1d13 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o +obj-$(CONFIG_SAMA5D2) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o obj-y += spl.o diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index c85571c..dd5a2a7 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -106,6 +106,7 @@ #define ATMEL_BASE_MPDDRC 0xf000c000 #define ATMEL_BASE_XDMAC0 0xf001 #define ATMEL_BASE_PMC 0xf0014000 +#define ATMEL_BASE_MATRIX0 0xf0018000 #define ATMEL_BASE_QSPI0 0xf002 #define ATMEL_BASE_QSPI1 0xf0024000 #define ATMEL_BASE_SPI00xf800 @@ -117,6 +118,7 @@ #define ATMEL_BASE_UART1 0xf802 #define ATMEL_BASE_UART2 0xf8024000 #define ATMEL_BASE_TWI00xf8028000 +#define ATMEL_BASE_SFR 0xf803 #define ATMEL_BASE_SYSC0xf8048000 #define ATMEL_BASE_SPI10xfc00 #define ATMEL_BASE_UART3 0xfc008000 @@ -125,6 +127,7 @@ #define ATMEL_BASE_UDPHS 0xfc02c000 #define ATMEL_BASE_PIOA0xfc038000 +#define ATMEL_BASE_MATRIX1 0xfc03c000 #define ATMEL_CHIPID_CIDR 0xfc069000 #define ATMEL_CHIPID_EXID 0xfc069004 @@ -171,6 +174,35 @@ #define CPU_HAS_PCR #define CPU_HAS_H32MXDIV +/* AICREDIR Unlock Key */ +#define ATMEL_SFR_AICREDIR_KEY 0xB6D81C4D + +/* MATRIX0(H64MX) slave id definitions */ +#define H64MX_SLAVE_AXIMX_BRIDGE 0 /* Bridge from H64MX to AXIMX */ +#define H64MX_SLAVE_PERIPH_BRIDGE 1 /* H64MX Peripheral Bridge */ +#define H64MX_SLAVE_DDRC_PORT0 2 /* DDR2 Port0-AESOTF */ +#define H64MX_SLAVE_DDRC_PORT1 3 /* DDR2 Port1 */ +#define H64MX_SLAVE_DDRC_PORT2 4 /* DDR2 Port2 */ +#define H64MX_SLAVE_DDRC_PORT3 5 /* DDR2 Port3 */ +#define H64MX_SLAVE_DDRC_PORT4 6 /* DDR2 Port4 */ +#define H64MX_SLAVE_DDRC_PORT5 7 /* DDR2 Port5 */ +#define H64MX_SLAVE_DDRC_PORT6 8 /* DDR2 Port6 */ +#define H64MX_SLAVE_DDRC_PORT7 9 /* DDR2 Port7 */ +#define H64MX_SLAVE_SRAM 10 /* Internal SRAM 128K */ +#define H64MX_SLAVE_CACHE_L2 11 /* Internal SRAM 128K(L2) */ +#define H64MX_SLAVE_QSPI0 12 /* QSPI0 */ +#define H64MX_SLAVE_QSPI1 13 /* QSPI1 */ +#define H64MX_SLAVE_AESB 14 /* AESB */ + +/* MATRIX1(H32MX) slave id definitions */ +#define H32MX_SLAVE_H64MX_BRIDGE 0 /* Bridge from H32MX to H64MX */ +#define H32MX_SLAVE_PERIPH_BRIDGE0 1 /* H32MX Peripheral Bridge 0 */ +#define H32MX_SLAVE_PERIPH_BRIDGE1 2 /* H32MX Peripheral Bridge 1 */ +#define H32MX_SLAVE_EBI3 /* External Bus Interface */ +#define H32MX_SLAVE_NFC_CMD3 /* NFC command Register */ +#define H32MX_SLAVE_NFC_SRAM 4 /* NFC SRAM */ +#define H32MX_SLAVE_USB5 /* USB Device & Host */ + /* SAMA5D2 series chip id definitions */ #define ARCH_ID_SAMA5D20x8a5c08c0 #define ARCH_EXID_SAMA5D21CU 0x005a diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 0b3397f..e0dc9ed 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include
[U-Boot] [PATCH v2 3/3] arm: at91/spl: mpddrc: use IP version to check configuration
To remove the unnecessary #ifdef-endif, use the mpddrc IP version
to check whether or not the interleaved decoding type is supported.
Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
---
Changes in v2:
- add Reviewed-by from Andreas.
arch/arm/mach-at91/mpddrc.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index 2b3a685..3bb5b84 100644
--- a/arch/arm/mach-at91/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -12,6 +12,8 @@
#include
#include
+#define SAMA5D3_MPDDRC_VERSION 0x140
+
static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr,
int mode,
u32 ram_address)
@@ -22,11 +24,13 @@ static inline void atmel_mpddr_op(const struct atmel_mpddr
*mpddr,
static int ddr2_decodtype_is_seq(u32 cr)
{
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
- defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
- if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
+ struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+ u16 version = readl(&mpddr->version) & 0x;
+
+ if ((version >= SAMA5D3_MPDDRC_VERSION) &&
+ (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
return 0;
-#endif
+
return 1;
}
--
1.7.9.5
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[U-Boot] [PATCH v2 2/3] arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization
The DDR3-SDRAM initialization sequence is implemented in
accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section
described in the SAMA5D2 datasheet.
Add registers and definitions of mpddrc controller, which is used
to support DDR3 devices.
Signed-off-by: Wenyou Yang
---
Changes in v2:
- remove comment accordingly after changing struct atmel_mpddr.
- remove some registers which have different definitions on
different SoCs to avoid confusion.
- remove whitespace error.
- rework commit log.
arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 85 ---
arch/arm/mach-at91/mpddrc.c| 88
2 files changed, 165 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
index 47b4cd4..47aae4d 100644
--- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
@@ -2,6 +2,9 @@
* Copyright (C) 2013 Atmel Corporation
* Bo Shen
*
+ * Copyright (C) 2015 Atmel Corporation
+ * Wenyou Yang
+ *
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -23,14 +26,35 @@ struct atmel_mpddrc_config {
* If other register needed, will add them later
*/
struct atmel_mpddr {
- u32 mr;
- u32 rtr;
- u32 cr;
- u32 tpr0;
- u32 tpr1;
- u32 tpr2;
- u32 reserved[2];
- u32 md;
+ u32 mr; /* 0x00: Mode Register */
+ u32 rtr;/* 0x04: Refresh Timer Register */
+ u32 cr; /* 0x08: Configuration Register */
+ u32 tpr0; /* 0x0c: Timing Parameter 0 Register */
+ u32 tpr1; /* 0x10: Timing Parameter 1 Register */
+ u32 tpr2; /* 0x14: Timing Parameter 2 Register */
+ u32 reserved; /* 0x18: Reserved */
+ u32 lpr;/* 0x1c: Low-power Register */
+ u32 md; /* 0x20: Memory Device Register */
+ u32 reserved1; /* 0x24: Reserved */
+ u32 lpddr23_lpr;/* 0x28: LPDDR2-LPDDR3 Low-power Register*/
+ u32 cal_mr4;/* 0x2c: Calibration and MR4 Register */
+ u32 tim_cal;/* 0x30: Timing Calibration Register */
+ u32 io_calibr; /* 0x34: IO Calibration */
+ u32 ocms; /* 0x38: OCMS Register */
+ u32 ocms_key1; /* 0x3c: OCMS KEY1 Register */
+ u32 ocms_key2; /* 0x40: OCMS KEY2 Register */
+ u32 conf_arbiter; /* 0x44: Configuration Arbiter Register */
+ u32 timeout;/* 0x48: Timeout Port 0/1/2/3 Register */
+ u32 req_port0123; /* 0x4c: Request Port 0/1/2/3 Register */
+ u32 req_port4567; /* 0x50: Request Port 4/5/6/7 Register */
+ u32 bdw_port0123; /* 0x54: Bandwidth Port 0/1/2/3 Register */
+ u32 bdw_port4567; /* 0x58: Bandwidth Port 4/5/6/7 Register */
+ u32 rd_data_path; /* 0x5c: Read Datapath Register */
+ u32 reserved2[33];
+ u32 wpmr; /* 0xe4: Write Protection Mode Register */
+ u32 wpsr; /* 0xe8: Write Protection Status Register */
+ u32 reserved3[4];
+ u32 version;/* 0xfc: IP version */
};
@@ -38,6 +62,9 @@ int ddr2_init(const unsigned int base,
const unsigned int ram_address,
const struct atmel_mpddrc_config *mpddr_value);
+int ddr3_init(const unsigned int ram_address,
+ const struct atmel_mpddrc_config *mpddr_value);
+
/* Bit field in mode register */
#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD0x0
#define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1
@@ -120,9 +147,51 @@ int ddr2_init(const unsigned int base,
/* Bit field in Memory Device Register */
#define ATMEL_MPDDRC_MD_LPDDR_SDRAM0x3
+#define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4
+#define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5
#define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6
#define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4)
#define ATMEL_MPDDRC_MD_DBW_32_BITS(0x0 << 4)
#define ATMEL_MPDDRC_MD_DBW_16_BITS(0x1 << 4)
+/* Bit field in I/O Calibration Register */
+#define ATMEL_MPDDRC_IO_CALIBR_RDIV0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_34_3 0x1
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_40 0x2
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48 0x3
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_60 0x4
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_80 0x6
+#define ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_120 0x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_35 0x2
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_43 0x3
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_52 0x4
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_70 0x6
+#define ATMEL_MPDDRC_IO_CALIBR_DDR2_RZQ_1050x7
+
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_37 0x2
+#define ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_44 0x3
+#defi
[U-Boot] [PATCH v2 1/3] arm: at91/spl: mpddrc: add struct atmel_mpddrc_config
Add struct atmel_mpddrc_config to accommodate the mpddrc register
configurations, not using the mpddrc register map structure,
struct atmel_mpddrc, in order to increase readability and reduce
run-time memory use.
Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
---
Changes in v2:
- add Reviewed-by from Andreas.
arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 12 +++-
arch/arm/mach-at91/mpddrc.c |2 +-
board/atmel/sama5d3_xplained/sama5d3_xplained.c |4 ++--
board/atmel/sama5d3xek/sama5d3xek.c |4 ++--
board/atmel/sama5d4_xplained/sama5d4_xplained.c |4 ++--
board/atmel/sama5d4ek/sama5d4ek.c |4 ++--
board/siemens/corvus/board.c|4 ++--
7 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
index c6c8dda..47b4cd4 100644
--- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
+++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
@@ -8,6 +8,16 @@
#ifndef __ATMEL_MPDDRC_H__
#define __ATMEL_MPDDRC_H__
+struct atmel_mpddrc_config {
+ u32 mr;
+ u32 rtr;
+ u32 cr;
+ u32 tpr0;
+ u32 tpr1;
+ u32 tpr2;
+ u32 md;
+};
+
/*
* Only define the needed register in mpddr
* If other register needed, will add them later
@@ -26,7 +36,7 @@ struct atmel_mpddr {
int ddr2_init(const unsigned int base,
const unsigned int ram_address,
- const struct atmel_mpddr *mpddr);
+ const struct atmel_mpddrc_config *mpddr_value);
/* Bit field in mode register */
#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD0x0
diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c
index 47e6e5a..9ba2a00 100644
--- a/arch/arm/mach-at91/mpddrc.c
+++ b/arch/arm/mach-at91/mpddrc.c
@@ -30,7 +30,7 @@ static int ddr2_decodtype_is_seq(u32 cr)
int ddr2_init(const unsigned int base,
const unsigned int ram_address,
- const struct atmel_mpddr *mpddr_value)
+ const struct atmel_mpddrc_config *mpddr_value)
{
const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base;
diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
index 7a01149..7acb8d0 100644
--- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c
+++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c
@@ -143,7 +143,7 @@ void spl_board_init(void)
#endif
}
-static void ddr2_conf(struct atmel_mpddr *ddr2)
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
@@ -185,7 +185,7 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- struct atmel_mpddr ddr2;
+ struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c
b/board/atmel/sama5d3xek/sama5d3xek.c
index 7c95f33..0d824fc 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -402,7 +402,7 @@ void spl_board_init(void)
#endif
}
-static void ddr2_conf(struct atmel_mpddr *ddr2)
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
@@ -444,7 +444,7 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- struct atmel_mpddr ddr2;
+ struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index db45331..e2f33a3 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -346,7 +346,7 @@ void spl_board_init(void)
#endif
}
-static void ddr2_conf(struct atmel_mpddr *ddr2)
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
@@ -384,7 +384,7 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
void mem_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
- struct atmel_mpddr ddr2;
+ struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
diff --git a/board/atmel/sama5d4ek/sama5d4ek.c
b/board/atmel/sama5d4ek/sama5d4ek.c
index 357b223..1799059 100644
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -342,7 +342,7 @@ void spl_board_init(void)
#endif
}
-static void ddr2_conf(struct atmel_mpddr *ddr2)
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
{
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
@@ -380,7 +380,7 @@ static void ddr2_conf(struct atmel_mpddr *ddr2)
void mem_init(void)
{
[U-Boot] [PATCH v2 0/3] arm: at91/spl: add DDR3-SDRAM initialization support
This patch series is to add DDR3-SDRAM initialzation sequence support. The DDR3-SDRAM initialization sequence is implemented in accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section described in the SAMA5D2 datasheet. Changes in v2: - add Reviewed-by from Andreas. - remove comment accordingly after changing struct atmel_mpddr. - remove some registers which have different definitions on different SoCs to avoid confusion. - remove whitespace error. - rework commit log. - add Reviewed-by from Andreas. Wenyou Yang (3): arm: at91/spl: mpddrc: add struct atmel_mpddrc_config arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization arm: at91/spl: mpddrc: use IP version to check configuration arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 93 +++-- arch/arm/mach-at91/mpddrc.c | 102 +-- board/atmel/sama5d3_xplained/sama5d3_xplained.c |4 +- board/atmel/sama5d3xek/sama5d3xek.c |4 +- board/atmel/sama5d4_xplained/sama5d4_xplained.c |4 +- board/atmel/sama5d4ek/sama5d4ek.c |4 +- board/siemens/corvus/board.c|4 +- 7 files changed, 193 insertions(+), 22 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 02/19] dm: timer: uclass: add timer init to add timer device
Hi Mugunthan, On Sun, Nov 29, 2015 at 9:16 PM, Mugunthan V N wrote: > On Saturday 28 November 2015 05:16 PM, Bin Meng wrote: >> Yes, but your patch 01 will break x86. I can prepare a patch for x86 >> if you like > > Can you send the patch so that I can include it on my next series. > Sure, I will prepare a patch for x86 soon. > Regards > Mugunthan V N Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 1/5] arm: at91/spl: matrix: move matrix init to separate file
Dear Andreas, Thank you for your review and apply for series. > -Original Message- > From: Andreas Bießmann [mailto:andreas.de...@googlemail.com] > Sent: 2015年12月1日 5:29 > To: u-boot@lists.denx.de; Yang, Wenyou > Subject: Re: [U-Boot, v2, 1/5] arm: at91/spl: matrix: move matrix init to > separate > file > > Dear Wenyou Yang, > > Wenyou Yang writes: > >To make the matrix initialization code sharing with other SoCs, move it > >from SAMA5D4 particular file, mach-at91/armv7/sama5d4_devices.c to a > >separate file, mach-at91/matrix.c > > > >Signed-off-by: Wenyou Yang > >Reviewed-by: Andreas Bießmann > >--- > > > >Changes in v2: None > > > > arch/arm/mach-at91/Makefile|2 +- > > arch/arm/mach-at91/armv7/sama5d4_devices.c | 42 --- > > arch/arm/mach-at91/matrix.c| 51 > > > 3 files changed, 52 insertions(+), 43 deletions(-) create mode 100644 > > arch/arm/mach-at91/matrix.c > > applied to u-boot-atmel/master, thanks! > > Best regards, > Andreas Bießmann Best Regards Wenyou Yang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] MX6ULEVK does not boot
On Mon, Nov 30, 2015 at 11:34 PM, Peng Fan wrote: > My is revA. I just tried on revB board using one Sandisk 8GB micro SDHC I > card, > it boots ok. > > " > U-Boot SPL 2016.01-rc1-00190-g90447ef (Dec 01 2015 - 09:29:18) > Trying to boot from MMC > > > U-Boot 2016.01-rc1-00190-g90447ef (Dec 01 2015 - 09:29:18 +0800) In my case even mx6qsabresd fails to boot when I use the Sandisk 8GB micro SDHC I card and SPL image. The non-SPL image (u-boot.imx) boots fine though. I haven't had a chance to investigate this yet. Regards, Fabio Estevam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] MX6ULEVK does not boot
Hi Fabio, On Mon, Nov 30, 2015 at 12:54:37PM -0200, Fabio Estevam wrote: >Hi Peng, > >On Mon, Nov 30, 2015 at 5:39 AM, Peng Fan wrote: > >> Sorry for this late reply. I missed you mail. I tried in my side >> with one sandisk 2GB macro sd card and one sandisk SDHC I 8GB card. >> >> Both boots fine. What card are you using? Also which revision board, RevA B >> or C? > >The card I have here that fails to boot is a SanDisk microSD HC I 8GB. > >My mx6ulevk is revB. What about yours? My is revA. I just tried on revB board using one Sandisk 8GB micro SDHC I card, it boots ok. " U-Boot SPL 2016.01-rc1-00190-g90447ef (Dec 01 2015 - 09:29:18) Trying to boot from MMC U-Boot 2016.01-rc1-00190-g90447ef (Dec 01 2015 - 09:29:18 +0800) " Regards, Peng. > >Thanks -- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-fsl-qoriq master
On Mon, Nov 30, 2015 at 11:32:33AM -0800, York Sun wrote: > Tom, > > The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757: > > Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03 > -0500) > > are available in the git repository at: > > > git://git.denx.de/u-boot-fsl-qoriq.git master > > for you to fetch changes up to 3785f57015dbd7582f85fd1c34dcaa26638bf976: > > armv8: fsl-layerscape: Fix early MMU table for nand boot (2015-11-30 > 09:11:13 > -0800) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] u-boot-atmel/master -> u-boot/master
On Mon, Nov 30, 2015 at 10:30:48PM +0100, Andreas Bießmann wrote: > Hi Tom, > > please pull the following changes into u-boot/master > > Andreas > > The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757: > > Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03 > -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-atmel.git master > > for you to fetch changes up to e4677f1ae221ac615f32c993aaf3d2497ad5009d: > > arm: at91/spl: atmel_sfr: move saic redirect to separate file (2015-11-30 > 22:27:55 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initialization
Hi Andreas,
Thank you very much for your review.
> -Original Message-
> From: Andreas Bießmann [mailto:andreas.de...@googlemail.com]
> Sent: 2015年11月28日 5:37
> To: Yang, Wenyou; U-Boot Mailing List
> Subject: Re: [PATCH 2/3] arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM
> initialization
>
> Hi Wenyou,
>
> On 04.11.15 07:32, Wenyou Yang wrote:
> > The implementation conforms to DDR3-SRAM/DDR3L-SDRAM
> typo --^
>
> > initialization section described in the SAMA5D2 datasheet.
> >
> > Add registers and definitions of mpddrc controller, which is used to
> > support DDR3 devices.
> >
> > Signed-off-by: Wenyou Yang
> > ---
> >
> > arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 88
> +---
> > arch/arm/mach-at91/mpddrc.c| 87
> +++
> > 2 files changed, 167 insertions(+), 8 deletions(-)
> >
> > diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
> > b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
> > index 47b4cd4..e777e67 100644
> > --- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
> > +++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h
> > @@ -2,6 +2,9 @@
> > * Copyright (C) 2013 Atmel Corporation
> > * Bo Shen
> > *
> > + * Copyright (C) 2015 Atmel Corporation
> > + * Wenyou Yang
> > + *
> > * SPDX-License-Identifier:GPL-2.0+
> > */
> >
> > @@ -23,14 +26,38 @@ struct atmel_mpddrc_config {
> > * If other register needed, will add them later
>
> This comment should be removed
>
> > */
> > struct atmel_mpddr {
> > - u32 mr;
> > - u32 rtr;
> > - u32 cr;
> > - u32 tpr0;
> > - u32 tpr1;
> > - u32 tpr2;
> > - u32 reserved[2];
> > - u32 md;
> > + u32 mr; /* 0x00: Mode Register */
> > + u32 rtr;/* 0x04: Refresh Timer Register */
> > + u32 cr; /* 0x08: Configuration Register */
> > + u32 tpr0; /* 0x0c: Timing Parameter 0 Register */
> > + u32 tpr1; /* 0x10: Timing Parameter 1 Register */
> > + u32 tpr2; /* 0x14: Timing Parameter 2 Register */
> > + u32 reserved; /* 0x18: Reserved */
> > + u32 lpr;/* 0x1c: Low-power Register */
> > + u32 md; /* 0x20: Memory Device Register */
> > + u32 reserved1; /* 0x24: Reserved */
>
> This is the MPDDRC High Speed Register for sama5d3
>
> > + u32 lpddr23_lpr;/* 0x28: LPDDR2-LPDDR3 Low-power Register*/
> > + u32 cal_mr4;/* 0x2c: LPDDR2 LPDDR3 and DDR3 Calibration
> and MR4 Register */
> > + u32 tim_cal;/* 0x30: LPDDR2 LPDDR3 and DDR3 Timing
> Calibration Register */
> > + u32 io_calibr; /* 0x34: IO Calibration */
> > + u32 ocms; /* 0x38: OCMS Register */
> > + u32 ocms_key1; /* 0x3c: OCMS KEY1 Register */
> > + u32 ocms_key2; /* 0x40: OCMS KEY2 Register */
> > + u32 conf_arbiter; /* 0x44: Configuration Arbiter Register */
> > + u32 timeout;/* 0x48: Timeout Port 0/1/2/3 Register */
> > + u32 req_port0123; /* 0x4c: Request Port 0/1/2/3 Register */
> > + u32 req_port4567; /* 0x50: Request Port 4/5/6/7 Register */
> > + u32 bdw_port0123; /* 0x54: Bandwidth Port 0/1/2/3 Register */
> > + u32 bdw_port4567; /* 0x58: Bandwidth Port 4/5/6/7 Register */
> > + u32 rd_data_path; /* 0x5c: Read Datapath Register */
> > + u32 mcfgr; /* 0x60: Monitor Configuration */
> > + u32 maddr[8]; /* 0x64 ~ 0x80: Monitor Address High/Low
> port0~7 */
> > + u32 minfo[8]; /* 0x84 ~ 0xa0: Monitor Information port0~7 */
>
> ... here it seems the two variants (sama5d3 and sama5d2) are way different
Yes, you are right. I read their datasheets, they have different definitions.
Luckily, these registers (mcfgr, maddr[8], minfo[8]) are not used in the
initialization sequence.
I want to replace them with reserved[17]. Do you agree? Or other advice?
Thanks.
>
> > + u32 reserved2[16];
> > + u32 wpmr; /* 0xe4: Write Protection Mode Register */
> > + u32 wpsr; /* 0xe8: Write Protection Status Register */
> > + u32 reserved3[4];
> > + u32 version;/* 0xfc: IP version */
> > };
> >
> >
> > @@ -38,6 +65,9 @@ int ddr2_init(const unsigned int base,
> > const unsigned int ram_address,
> > const struct atmel_mpddrc_config *mpddr_value);
> >
> > +int ddr3_init(const unsigned int ram_address,
> > + const struct atmel_mpddrc_config *mpddr_value);
> > +
> > /* Bit field in mode register */
> > #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD0x0
> > #define ATMEL_MPDDRC_MR_MODE_NOP_CMD 0x1
> > @@ -120,9 +150,51 @@ int ddr2_init(const unsigned int base,
> >
> > /* Bit field in Memory Device Register */
> > #define ATMEL_MPDDRC_MD_LPDDR_SDRAM0x3
> > +#define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4
> >
Re: [U-Boot] [PATCH] arm, ubifs: fix gcc5.x compiler warning
Hello Heiko,
On 30-11-15 11:03, Heiko Schocher wrote:
Am 30.11.2015 um 10:20 schrieb Jeroen Hofstee:
Hello Heiko,
On 30-11-15 08:47, Heiko Schocher wrote:
compiling U-Boot for openrd_base_defconfig with
gcc 5.x shows the following warning:
CC fs/ubifs/super.o
In file included from fs/ubifs/ubifs.h:35:0,
from fs/ubifs/super.c:37:
fs/ubifs/super.c: In function 'atomic_inc':
./arch/arm/include/asm/atomic.h:55:2: warning: 'flags' is used
uninitialized in this function
[-Wuninitialized]
local_irq_save(flags);
Since flags is an "out" argument, something else must be wrong.
There should be no need to initialize it, since local_irq_save should
do that afaik.
yes, you are right, it should be, but gcc 5.x seems to have problems
with it ... compiled code size for the openrd_base config is same with
my patch ...
Hmm... for the openrd_base compile local_irq_save() is used from:
arch/arm/thumb1/include/asm/proc-armv/system.h
with:
static inline void local_irq_save(
unsigned long flags __attribute__((unused)))
{
__asm__ __volatile__ ("" : : : "memory");
}
flasg marked as unused ... seems correct to me, but I have
no idea, why gcc 5.x prints a warning ... any ideas?
Well, guessing, order of the passes inside the compiler matter, if the
inline is done first, and thereafter the sanity check is done, the latter
can't detect an uninitialized variable is passed, since it has already
been removed. If you do it the other way around, it will warn first
since it won't know the latter pass will remove it. If I have to guess,
I think that is what is happening. [ of course it can be made a bit
smarter, by e.g. looking at the __attribute__((unused)), but more
guessing, I think gcc5 just ignores that one ].
Even more funny is the fact that these functions are not macro's
to _prevent_ compiler warnings ;) So cc-ing Albert since he wrote it.
"
/*
* Redefine all original macros with static inline functions containing
* a simple memory barrier, so that they produce the same instruction
* ordering constraints as their original counterparts.
* We use static inline functions rather than macros so that we can tell
* the compiler to not complain about unused arguments.
*/
"
If we can find a version which doesn't pose other requirements then the
linux versions (like flags must be initialized) _and_ they don't warn
as well, I guess we can agree that would be preferred.
I am not sure to what extend though, some options below to modify
local_irq_save itself to prevent the warning 4 and 5 are warning free,
not sure it is a brilliant thing to do though Albert?
Regards,
Jeroen
// triggers: "is used uninitialized in this function" with gcc5
static inline void my_argument_maybe_unused1(int flags
__attribute__((unused)))
{
}
// triggers -Wunused-variable
#define my_argument_maybe_unused2(flags) do {} while(0)
// triggers set but not used
#define my_argument_maybe_unused3(flags) do { flags = 0; } while(0)
// so, lets use flags instead, but clearly unused so it gets optimized
out later ;)
// no warnings with gcc 5, clang 3.4
#define my_argument_maybe_unused4(flags) do { int dummy
__attribute__((unused)) = sizeof(flags); } while(0)
// combined preprocessor / compiler foodoo
static inline void _my_argument_maybe_unused5(int *flags
__attribute__((unused)))
{
}
#define my_argument_maybe_unused5(flags) do {
_my_argument_maybe_unused5(&flags); } while(0)
int main()
{
int i_am_used_in_linux_not_in_uboot1;
int i_am_used_in_linux_not_in_uboot2;
int i_am_used_in_linux_not_in_uboot3;
int i_am_used_in_linux_not_in_uboot4;
int i_am_used_in_linux_not_in_uboot5;
my_argument_maybe_unused1(i_am_used_in_linux_not_in_uboot1);
my_argument_maybe_unused2(i_am_used_in_linux_not_in_uboot2);
my_argument_maybe_unused3(i_am_used_in_linux_not_in_uboot3);
my_argument_maybe_unused4(i_am_used_in_linux_not_in_uboot4);
my_argument_maybe_unused5(i_am_used_in_linux_not_in_uboot5);
return 0;
}
/*
arm-linux-gnueabihf-gcc (Linaro GCC 5.1-2015.08) 5.1.1 20150608
arm-linux-gnueabihf-gcc -Wall -O2 warnings.c
good, no code generated..
000102c0 :
102c0:2000 movsr0, #0
102c2:4770 bxlr
host, clang... guess this fine too, no idea what the nops are though...
004004f0 :
4004f0:31 c0xor%eax,%eax
4004f2:c3 retq
4004f3:66 2e 0f 1f 84 00 00 nopw %cs:0x0(%rax,%rax,1)
4004fa:00 00 00
4004fd:0f 1f 00 nopl (%rax)
*/
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Re: [U-Boot] [PATCH 3/3] net: mvneta: Convert to driver model
On Fri, Nov 27, 2015 at 4:29 AM, Stefan Roese wrote:
> Update this driver to support driver model. As all MVEBU boards using
> this driver are converted with this patch, the non-driver-model code
> can be removed completely. This is also the reason why this patch
> is quite big and includes a) the driver change and b) the
> platform change. As its not git-bisect save otherwise.
>
> With this conversion, some parameters are now extracted from the
> DT instread of using the config header defines. The supported
> properties right now are:
>
> PHY-mode ("phy-mode") and PHY-address ("reg").
>
> The base addresses for the ethernet controllers can be removed from
> the header files as well.
>
> Please note that this patch also removes the E1000 network driver
> from some MVEBU config headers. This is necessary, as with DM_ETH
> configured and the e1000 driver enabled, the PCI driver also needs
> to support DM. But the MVEBU PCI(e) driver still needs to get
> ported to DM. When this is done, the E1000 driver can be enabled
> again.
>
> Signed-off-by: Stefan Roese
> Cc: Luka Perkov
> Cc: Dirk Eibach
> Cc: Joe Hershberger
> Cc: Simon Glass
Acked-by: Joe Hershberger
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Re: [U-Boot] [PATCH] arm: mx6: Reduce SPL malloc pool size
On Monday, November 30, 2015 at 07:56:55 PM, Tim Harvey wrote: > On Wed, Nov 25, 2015 at 5:32 AM, Marek Vasut wrote: > > On Wednesday, November 25, 2015 at 02:15:13 PM, Przemyslaw Marczak wrote: > >> On 11/25/2015 01:16 PM, Marek Vasut wrote: > >> > On Wednesday, November 25, 2015 at 01:00:41 PM, Przemyslaw Marczak wrote: > >> >> Hello Marek, > >> >> > >> >> On 11/25/2015 11:56 AM, Marek Vasut wrote: > >> >>> On Wednesday, November 25, 2015 at 11:40:36 AM, Przemyslaw Marczak wrote: > >> Hello Tim, Marek > >> > >> On 11/20/2015 10:40 PM, Tim Harvey wrote: > >> > On Fri, Nov 20, 2015 at 12:43 PM, Marek Vasut wrote: > >> >> Using 50 MiB malloc pool in SPL is nonsense. Since the caches are > >> >> not enabled in SPL, it takes 2 seconds to init the pool and has > >> >> no obvious benefit. Reduce the size to 1 MiB. > >> >> > >> >> Signed-off-by: Marek Vasut > >> >> Cc: Stefano Babic > >> >> Cc: Tim Harvey > >> >> --- > >> >> > >> >> include/configs/imx6_spl.h | 6 +++--- > >> >> 1 file changed, 3 insertions(+), 3 deletions(-) > >> >> > >> >> diff --git a/include/configs/imx6_spl.h > >> >> b/include/configs/imx6_spl.h index 1744f2c..43ce7fe 100644 > >> >> --- a/include/configs/imx6_spl.h > >> >> +++ b/include/configs/imx6_spl.h > >> >> @@ -63,15 +63,15 @@ > >> >> > >> >> #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || > >> >> defined(CONFIG_MX6SL) #define CONFIG_SPL_BSS_START_ADDR > >> >> 0x8820 > >> >> > >> >> -#define CONFIG_SPL_BSS_MAX_SIZE0x10/* 1 MB > >> >> */ +#define CONFIG_SPL_BSS_MAX_SIZE0x10 > >> >> /* 1 MB */ > >> >> > >> >> #define CONFIG_SYS_SPL_MALLOC_START0x8830 > >> >> > >> >> -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x320 /* 50 MB > >> >> */ +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10 > >> >> /* 1 MB */ > >> >> > >> >> #define CONFIG_SYS_TEXT_BASE 0x8780 > >> >> #else > >> >> #define CONFIG_SPL_BSS_START_ADDR 0x1820 > >> >> #define CONFIG_SPL_BSS_MAX_SIZE0x10 > >> >> /* 1 MB */ #define CONFIG_SYS_SPL_MALLOC_START0x1830 > >> >> > >> >> -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x320 /* 50 MB > >> >> */ +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10/* 1 > >> >> MB */ > >> >> > >> >> #define CONFIG_SYS_TEXT_BASE 0x1780 > >> >> #endif > >> >> #endif > >> >> > >> >> -- > >> >> 2.1.4 > >> > > >> > Acked-by: Tim Harvey > >> > > >> > thanks for dropping 2 secs off our time to boot! > >> > > >> > Tim > >> > >> The boot time for SPL and U-Boot can be reduced more if > >> CONFIG_SYS_MALLOC_CLEAR_ON_INIT is unset (default is set). > >> >>> > >> >>> This might confuse DM, so I don't want this. DM checks if it's > >> >>> structures were already inited and if we don't clear the malloc > >> >>> area, they would be. > >> >> > >> >> DM is safe - it uses calloc() for it's structures and also driver's > >> >> static structures are zeroed. Only some private data which is not > >> >> allocated by DM can be risky to use. > >> >> > >> >> To be precise - we don't use malloc() to get pointer for zeroed > >> >> memory, this is the job for the calloc(). > >> >> > >> >> So any code with bad use of malloc() should be fixed ASAP. > >> >> > >> >> If you assume that clear the malloc pool at boot is safe to use, then > >> >> I'm asking you, what about the sequence malloc/free/malloc for > >> >> potentially the same area? You can't be sure that the second returned > >> >> pointer after calling free() - points to the initially zeroed pool. > >> >> > >> >> We don't clean the malloc pool for configs that we maintain and we > >> >> didn't noticed any issues related to this. And the boot time is > >> >> reduced significantly. > >> > > >> > Do you use DM in SPL ? > >> > >> No, we don't use the SPL - for the boards which we maintain. > > > > OK > > > >> > I just checked and I see it's probably only the GD which needs to be > >> > cleared out, so we should indeed be safe. In which case, patch is > >> > welcome to enable CONFIG_SYS_MALLOC_CLEAR_ON_INIT . > >> > >> Yes I can see also for the Exynos SPL, that GD is manually cleared. > >> > >> But disabling the default CONFIG_SYS_MALLOC_CLEAR_ON_INIT, will help you > >> in reducing the U-Boot init time. > >> Just try and if you can easy measure the real difference for > >> enable/disable this config - share the results - it can give us an > >> interesting conclusions. > > > > Sure, thanks for the hint, but I still don't see any reason for having 50 > > MiB malloc area in SPL ;-) > > Perhaps the use case for a >1MB malloc area is falcon mode. While a > 1MB area certainly works for l
Re: [U-Boot] [PATCH 3/3] net: mvneta: Convert to driver model
On Mon, Nov 30, 2015 at 4:23 PM, Joe Hershberger
wrote:
> On Fri, Nov 27, 2015 at 4:29 AM, Stefan Roese wrote:
>> Update this driver to support driver model. As all MVEBU boards using
>> this driver are converted with this patch, the non-driver-model code
>> can be removed completely. This is also the reason why this patch
>> is quite big and includes a) the driver change and b) the
>> platform change. As its not git-bisect save otherwise.
>>
>> With this conversion, some parameters are now extracted from the
>> DT instread of using the config header defines. The supported
>> properties right now are:
>>
>> PHY-mode ("phy-mode") and PHY-address ("reg").
>>
>> The base addresses for the ethernet controllers can be removed from
>> the header files as well.
>>
>> Please note that this patch also removes the E1000 network driver
>> from some MVEBU config headers. This is necessary, as with DM_ETH
>> configured and the e1000 driver enabled, the PCI driver also needs
>> to support DM. But the MVEBU PCI(e) driver still needs to get
>> ported to DM. When this is done, the E1000 driver can be enabled
>> again.
>>
>> Signed-off-by: Stefan Roese
>> Cc: Luka Perkov
>> Cc: Dirk Eibach
>> Cc: Joe Hershberger
>> Cc: Simon Glass
>> ---
>> arch/arm/Kconfig| 1 +
>> arch/arm/mach-mvebu/cpu.c | 24 ---
>> arch/arm/mach-mvebu/include/mach/soc.h | 4 -
>> board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 32 ++--
>> board/maxbcm/maxbcm.c | 20 ++-
>> drivers/net/mvneta.c| 230
>>
>> include/configs/db-88f6820-gp.h | 3 -
>> include/configs/db-mv784mp-gp.h | 4 -
>> include/configs/maxbcm.h| 3 -
>> 9 files changed, 154 insertions(+), 167 deletions(-)
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index 2e20212..0c4794b 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -117,6 +117,7 @@ config ARCH_MVEBU
>> select OF_CONTROL
>> select OF_SEPARATE
>> select DM
>> + select DM_ETH
>
> All ARM boards? Am I missing something? Seems a bit broad for the
> scope of this patch.
Nevermind. Didn't notice the scoping of "config ARCH_MVEBU".
>
>> select DM_SERIAL
>> select DM_SPI
>> select DM_SPI_FLASH
>
> Otherwise, looks good.
>
> -Joe
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Re: [U-Boot] [PATCH 18/25] dm: net: Convert rtl8169 to use DM PCI API
Hi Joe,
On 23 November 2015 at 16:32, Joe Hershberger wrote:
> Hi Simon,
>
> On Mon, Nov 16, 2015 at 9:53 PM, Simon Glass wrote:
>> Update this driver to use the proper driver-model PCI API functions.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> drivers/net/rtl8169.c | 88
>> ---
>> 1 file changed, 70 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
>> index 19422c4..0a93668 100644
>> --- a/drivers/net/rtl8169.c
>> +++ b/drivers/net/rtl8169.c
>> @@ -513,8 +513,13 @@ static void rtl_flush_buffer(void *buf, size_t size)
>> /**
>> RECV - Receive a frame
>> ***/
>> -static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase,
>> +#ifdef CONFIG_DM_ETH
>> +static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
>> + uchar **packetp)
>> +#else
>> +static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
>>uchar **packetp)
>> +#endif
>> {
>> /* return true if there's an ethernet packet ready to read */
>> /* nic->packet should contain data on return */
>> @@ -545,9 +550,16 @@ static int rtl_recv_common(pci_dev_t bdf, unsigned long
>> dev_iobase,
>> else
>> tpc->RxDescArray[cur_rx].status =
>> cpu_to_le32(OWNbit + RX_BUF_SIZE);
>> +#ifdef CONFIG_DM_ETH
>> tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
>> - pci_mem_to_phys(bdf, (pci_addr_t)(unsigned
>> long)
>> + dm_pci_mem_to_phys(dev,
>> + (pci_addr_t)(unsigned long)
>> + tpc->RxBufferRing[cur_rx]));
>> +#else
>> + tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
>> + pci_mem_to_phys(dev, (pci_addr_t)(unsigned
>> long)
>> tpc->RxBufferRing[cur_rx]));
>> +#endif
>> rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
>> #ifdef CONFIG_DM_ETH
>> *packetp = rxdata;
>> @@ -576,7 +588,7 @@ int rtl8169_eth_recv(struct udevice *dev, int flags,
>> uchar **packetp)
>> {
>> struct rtl8169_private *priv = dev_get_priv(dev);
>>
>> - return rtl_recv_common(pci_get_bdf(dev), priv->iobase, packetp);
>> + return rtl_recv_common(dev, priv->iobase, packetp);
>> }
>> #else
>> static int rtl_recv(struct eth_device *dev)
>> @@ -590,8 +602,13 @@ static int rtl_recv(struct eth_device *dev)
>> /**
>> SEND - Transmit a frame
>> ***/
>> -static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase,
>> +#ifdef CONFIG_DM_ETH
>> +static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
>>void *packet, int length)
>> +#else
>> +static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
>> + void *packet, int length)
>> +#endif
>> {
>> /* send the packet to destination */
>>
>> @@ -618,8 +635,13 @@ static int rtl_send_common(pci_dev_t bdf, unsigned long
>> dev_iobase,
>> ptxb[len++] = '\0';
>>
>> tpc->TxDescArray[entry].buf_Haddr = 0;
>> +#ifdef CONFIG_DM_ETH
>> + tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
>> + dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
>> +#else
>> tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
>> - pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb));
>> + pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
>> +#endif
>> if (entry != (NUM_TX_DESC - 1)) {
>> tpc->TxDescArray[entry].status =
>> cpu_to_le32((OWNbit | FSbit | LSbit) |
>> @@ -661,7 +683,7 @@ int rtl8169_eth_send(struct udevice *dev, void *packet,
>> int length)
>> {
>> struct rtl8169_private *priv = dev_get_priv(dev);
>>
>> - return rtl_send_common(pci_get_bdf(dev), priv->iobase, packet,
>> length);
>> + return rtl_send_common(dev, priv->iobase, packet, length);
>> }
>>
>> #else
>> @@ -695,7 +717,11 @@ static void rtl8169_set_rx_mode(void)
>> RTL_W32(MAR0 + 4, mc_filter[1]);
>> }
>>
>> -static void rtl8169_hw_start(pci_dev_t bdf)
>> +#ifdef CONFIG_DM_ETH
>> +static void rtl8169_hw_start(struct udevice *dev)
>> +#else
>> +static void rtl8169_hw_start(pci_dev_t dev)
>> +#endif
>> {
>> u32 i;
>>
>> @@ -740,11 +766,21 @@ static void rtl8169_hw_start(pci_dev_t bdf)
>>
>> tpc->cur_rx = 0;
>>
>> - RTL_W32(TxDescStartAddrLow
Re: [U-Boot] [PATCH 10/14] net: gem: Remove zynq_gem_of_init()
On 30 November 2015 at 08:05, Michal Simek wrote: > This function was used for OF init before DM. > Remove this function as the part of move to DM. > > Signed-off-by: Michal Simek > --- > > drivers/net/zynq_gem.c | 42 -- > include/netdev.h | 1 - > 2 files changed, 43 deletions(-) Reviewed-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 12/14] net: gem: Move driver to DM
Hi Michal,
On 30 November 2015 at 08:05, Michal Simek wrote:
> - Enable DM_ETH by default for Zynq and ZynqMP
> - Remove board_eth_init code
> - Change miiphy_read function to return value instead of error code
> based on DM requirement
> - Do not enable EMIO DT support by default
>
> Signed-off-by: Michal Simek
> ---
>
> arch/arm/Kconfig | 2 +
> board/xilinx/zynq/board.c | 13
> board/xilinx/zynqmp/zynqmp.c | 25 ---
> drivers/mmc/zynq_sdhci.c | 17 +
> drivers/net/zynq_gem.c| 166
> --
> include/configs/zynq-common.h | 6 --
> include/netdev.h | 2 -
> 7 files changed, 116 insertions(+), 115 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 6542c38304a5..f989ab521469 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -551,6 +551,7 @@ config ARCH_ZYNQ
> select OF_CONTROL
> select SPL_OF_CONTROL
> select DM
> + select DM_ETH
> select SPL_DM
> select DM_SPI
> select DM_SERIAL
> @@ -562,6 +563,7 @@ config ARCH_ZYNQMP
> select ARM64
> select DM
> select OF_CONTROL
> + select DM_ETH
> select DM_SERIAL
>
> config TEGRA
> diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
> index 237f2c2a2bf6..572b1468bf51 100644
> --- a/board/xilinx/zynq/board.c
> +++ b/board/xilinx/zynq/board.c
> @@ -119,19 +119,6 @@ int board_eth_init(bd_t *bis)
> ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
> txpp, rxpp);
> #endif
> -
> -#if defined(CONFIG_ZYNQ_GEM)
> -# if defined(CONFIG_ZYNQ_GEM0)
> - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
> - CONFIG_ZYNQ_GEM_PHY_ADDR0,
> - CONFIG_ZYNQ_GEM_EMIO0);
> -# endif
> -# if defined(CONFIG_ZYNQ_GEM1)
> - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
> - CONFIG_ZYNQ_GEM_PHY_ADDR1,
> - CONFIG_ZYNQ_GEM_EMIO1);
> -# endif
> -#endif
> return ret;
> }
>
> diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
> index d105bb4de32f..51dc30f90d7e 100644
> --- a/board/xilinx/zynqmp/zynqmp.c
> +++ b/board/xilinx/zynqmp/zynqmp.c
> @@ -65,31 +65,6 @@ void scsi_init(void)
> }
> #endif
>
> -int board_eth_init(bd_t *bis)
> -{
> - u32 ret = 0;
> -
> -#if defined(CONFIG_ZYNQ_GEM)
> -# if defined(CONFIG_ZYNQ_GEM0)
> - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
> - CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
> -# endif
> -# if defined(CONFIG_ZYNQ_GEM1)
> - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
> - CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
> -# endif
> -# if defined(CONFIG_ZYNQ_GEM2)
> - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2,
> - CONFIG_ZYNQ_GEM_PHY_ADDR2, 0);
> -# endif
> -# if defined(CONFIG_ZYNQ_GEM3)
> - ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3,
> - CONFIG_ZYNQ_GEM_PHY_ADDR3, 0);
> -# endif
> -#endif
> - return ret;
> -}
> -
> #ifdef CONFIG_CMD_MMC
> int board_mmc_init(bd_t *bd)
> {
> diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> index e169b774932a..5ea992a3ce65 100644
> --- a/drivers/mmc/zynq_sdhci.c
> +++ b/drivers/mmc/zynq_sdhci.c
> @@ -33,6 +33,23 @@ int zynq_sdhci_init(phys_addr_t regbase)
> return 0;
> }
>
> +
> +
> +static const struct udevice_id arasan_sdhci_ids[] = {
> + { .compatible = "arasan,sdhci-8.9a" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(arasan_sdhci_drv) = {
> + .name = "rockchip_dwmmc",
> + .id = UCLASS_MMC,
> + .of_match = rockchip_dwmmc_ids,
> + .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
> + .probe = rockchip_dwmmc_probe,
> + .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
> +};
> +
> +
This seems unrelated / also rockchip stuff.
> #if CONFIG_IS_ENABLED(OF_CONTROL)
> int zynq_sdhci_of_init(const void *blob)
> {
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
> index 4e93707c7ab1..f2a14938036f 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -13,6 +13,7 @@
> #include
> #include
> #include
> +#include
Can you put up higher so that these are in order?
> #include
> #include
> #include
> @@ -23,6 +24,8 @@
> #include
> #include
>
> +DECLARE_GLOBAL_DATA_PTR;
> +
> #if !defined(CONFIG_PHYLIB)
> # error XILINX_GEM_ETHERNET requires PHYLIB
> #endif
> @@ -241,7 +244,7 @@ static u32 phywrite(struct zynq_gem_priv *priv, u32
> phy_addr,
> ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
> }
>
> -static int phy_detection(struct eth_device *dev)
> +static
Re: [U-Boot] [PATCH v7 00/34] sf: MTD support
Hi Jagan,
On 27 November 2015 at 02:21, Jagan Teki wrote:
> Hi Bin,
>
> On 27 November 2015 at 07:55, Bin Meng wrote:
>> Hi Jagan,
>>
>> On Fri, Nov 27, 2015 at 2:54 AM, Jagan Teki wrote:
>>> Hi Simon,
>>>
>>> Some how I'm unclear about your comments in previous series probably I
>>> my misunderstanding or something. let me explain about my plan on
>>> spi-nor development.
>>>
>>> The entire spi-flash code is generic for all means there is no
>>> separate code for any platform or device. So I call it as spi-flash
>>> core. spi-flash core having functionaries like read_jedec, flash
>>> read/write/erase all these were calling from cmd_sf using dm and
>>> non-dm version, here I'm replacing this MTD since it is core interface
>>> it doesn't handle any specific device or uclass and mtd operations are
>>> being used directly without any dm except the probe.
>>>
>>> So spi-flash shouldn't need dm and the respective probe sf_probe will
>>> follow dm as it allocates spi_flash and by taking spi_slave{} setup
>>> spi-uclass. spi-flash operation are common and there is no different
>>> ops for different drivers or devices or something and mtd_ops are
>>> manged directly from cmd_sf like nand and spi-nor in Linux.
>>>
>>> And once core sits stable spi-flash will implemented as spi-nor core
>>> and the bellowed drivers becomes spi-nor drivers like spi-nor to spi
>>> driver interface and spi-nor controller drivers these are dm-driven
>>> it's having dm ops similar to spi-flash ops and spi-flash no where
>>> required.
>>
>> My understanding is that when we introduce a new driver feature, it
>> should target driver model by default. This is to encourage boards to
>> take advantage of driver model, and all these *new* features. This is
>> what Simon asked for. As Simon mentioned, probably we should make the
>> SPI flash DM conversion complete now instead of adding any new feature
>> on top of it.
>
> I'm not introduced any new driver feature here, instead I re-used the
> existing mtd core features and functionalities.
>
> The current code looks as below:
>
> sf_probe.c:
> 1) having both non-dm and dm spi-flash and calls to
> 2) spi_flash_probe_slave for spi_flash detection and setting up hooks
> (spi_flash ops)
>
> sf_ops.c:
> 1) having all spi_flash ops definitions.
>
> These are the changes I did
> a) Moved spi_flash probing like definition of spi_flash_probe_slave
> from sf_probe.c to sf_ops.c so sf_ops.c having all core spi-flash code
> like flash detection, setting up hooks (spi_flash ops) and spi_flash
> ops definitions.
> b) from above point a) sf_probe.c having both dm and non-dm interface
> with a common call to sf_ops.c for spi-flash core functionalities
> using spi_flash_scan.
> c) Replaced existing spi_flash_mtd_register (sf_mtd.c) registration
> with generic mtd core using add_mtd_device in sf_probe.c for both dm
> and non-dm interfaces.
> d) In sf_ops.c Updated all mtd_info structure filling and replaced
> spi_flash ops hooks with mtd_info hooks - where dm_spi_flash_ops got
> dropped.
> e) Called mtd core operations from spi_flash.h like
> mtd_erase|write|read instead of direct calls to sf_ops.c with
> spi_flash operation as they are not needed, so mtd core calls will in
> turn call mtd hooks on spi-flash like nand, cfi and spi-nor in Linux.
>
> The code after these changes:
>
> sf_probe.c:
> 1) having both non-dm and dm spi-flash and calls to
> 2) spi_flash_scan for spi-flash core functionalities and register with core
> mtd.
>
> sf_ops.c:
> 1) core spi-flash operations => spi_flash detection + setting up hooks
> (mtd ops) + having all mtd_info ops definitions.
>
> I couldn't understand what's wrong with this approach, because I have
> not added any new feature instead I reused it existing MTD core. I
> agree that the dm_spi_flash_ops are removed as mtd_info ops are used
> instead and sf_probe.c is still with dm.
>
> Please let me know your inputs.
Conceptually this seems problematic.
SPI flash is a uclass and supports driver model. It has operations,
etc. Your patches remove the operations in favour of calling MTD. But
MTD does not support driver model. This is getting really messy.
Before going any further we need to at least figure out the end goal.
To repeat my question from the previous email:
Is it intended that SPI flash should be a driver for the MTD uclass?
Others would be NAND and CFI. From what I can tell MTD has the same
operations as SPI flash (erase, read, write) and adds a lot more.
Or is SPI flash really a separate uclass from MTD, with SPI flash
being at a higher level?
>
>>
>>>
>>> cmd_sf
>>> ===
>>> MTD
>>> ===
>>> spi-nor or spi-flash
>>> ===
>>> "spi-nor to spi drivers" and spi-nor controller driver
>>> ===
>
> thanks!
> --
> Jagan | openedev.
> ___
> U-Boot mailing list
> U-Boot@lists.denx.de
Re: [U-Boot] [PATCH] dm: core: Add platform specific bus translation function
Hi Stefan,
On 29 November 2015 at 23:52, Stefan Roese wrote:
> Hi Simon,
>
> On 27.11.2015 19:36, Simon Glass wrote:
>> On 27 November 2015 at 02:22, Stefan Roese wrote:
>>> This patch adds the additional platform_translate_address() call to
>>> dev_get_addr(). A weak default with a 1-to-1 translation is also
>>> provided. Platforms that need a special address translation can
>>> overwrite this function.
>>>
>>> Here the explanation, why this is needed for MVEBU:
>>>
>>> When using DM with DT address translation, this does not work
>>> with the standard fdt_translate_address() function on MVEBU
>>> in SPL. Since the DT translates to the 0xf100. base
>>> address for the internal registers. But SPL still has the
>>> registers mapped to the 0xd000. (SOC_REGS_PHY_BASE)
>>> address that is used by the BootROM. This is because SPL
>>> may return to the BootROM for boot continuation (e.g. UART
>>> xmodem boot mode).
>>>
>>> Signed-off-by: Stefan Roese
>>> Cc: Simon Glass
>>> Cc: Luka Perkov
>>> Cc: Dirk Eibach
>>> ---
>>> drivers/core/device.c | 36 +---
>>> 1 file changed, 25 insertions(+), 11 deletions(-)
>>
>> I wonder if there is a way to handle this with device tree? I would
>> very much like to avoid adding weak functions and other types of
>> hooks.
>
> I've thought about this also for quite a bit. But couldn't come
> up with a "better", less intrusive implementation for this
> problem yet.
>
>> Are you saying that there are two values for 'ranges', one in
>> SPL and one for U-Boot proper?
>
> You can think of it as 2 values for "ranges", yes. Basically
> its a difference in the upper 8 bits of all addresses of the
> internal registers (e.g. UART, SDRAM controller...).
>
> The BootROM starts with 0xd000. and SPL also needs to
> use this value. As SPL returns back into the BootROM in
> some cases. And Linux (and other OS'es) expect 0xf100.
> as base address. So the main U-Boot reconfigured the base
> address to this value quite early.
>
>> What actually triggers the change?
>
> This is no change. Its just, that now SPL has added DM and DTS
> support. Before this SPL-DM support this was handled by
> something like this:
>
> #if defined(CONFIG_SPL_BUILD)
> #define SOC_REGS_PHY_BASE 0xd000
> #else
> #define SOC_REGS_PHY_BASE 0xf100
> #endif
> #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
> #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
> #define MVEBU_L2_CACHE_BASE (MVEBU_REGISTER(0x08000))
> ...
>
> And now (nearly) all addresses are taken from the DT. And the
> SPL vs. U-Boot proper base address difference needs to get
> handled otherwise - here in the DT.
No, I mean what causes the hardware address to move? Is there a
register somewhere that it adjusted to tell the addressing to change?
>
>> One option would be to have a ranges-spl property, or similar.
>
> Hmmm. you mean to add these "ranges-spl" properties additionally
> to the normal "ranges" properties? I would really like to not
> change the "ranges" in the dts files. As especially in the
> MVEBU cases (Armada XP / 38x etc), the occurrences are very
> high. And this would result in quite a big difference to the
> "mainline Linux dts" version.
Yes I mean a new property. After all, the existing one is incorrect
for your hardware at least in some configuration.
>
> I could also add this functionality via a new Kconfig option.
> Like this:
>
> + if (CONFIG_IS_ENABLED(PLATFORM_TRANSLATE_ADDRESS)) {
> + addr = platform_translate_address((void *)gd->fdt_blob,
> + dev->of_offset, addr);
> + }
>
> So no weak default would be needed. Just let me know if you
> would prefer it this way. And I'll send a v2 using this
> approach.
I'd like to exhaust the DT option first, as this adds another level of
complexity...the DT is supposed to describe the hardware.
Regards,
Simon
___
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Re: [U-Boot] [PATCH v5 00/21] Bring up rk3036 uboot
Hi Sjeord, On 30 November 2015 at 01:12, Sjoerd Simons wrote: > On Fri, 2015-11-27 at 16:21 -0800, Simon Glass wrote: >> +a few others who have submitted patches > > I suspect this is unrelated to the 3036 bringup, but at the moment i > can't build the 3288 firefly SPL smaller then 32k :( (iotw small enoug > to be used as an SD card image). The image ends up being about 250 > bytes too big.. > > Playing silly games with nm, it seems the big items are the sdram > bringup-code, mmc core/drivers and ofcourse (vs)printf related > functions (followed by a long tail of smaller things). > > Seems like a bit of dieting is required ;) Yes. Maybe some #ifdefs for each subsystem in rk3288_pinctrl_request() would help. But in general it is too close to the limit. With the bug-fixed gcc it is fine, but we are stuck with the bug for a while. Would be great if we could move to tiny printf(). Adding sprintf() requires refactoring but should be doable. Regards, Simon > >> Hi, >> >> On 15 November 2015 at 16:58, hl wrote: >> > Hi Simon, >> > >> > >> > On 14/11/15 02:14, Simon Glass wrote: >> > > >> > > Hi Lin, >> > > >> > > On 10 November 2015 at 03:24, Lin Huang >> > > wrote: >> > > > >> > > > This series patch bring up rk3036 uboot, since rk3036 only 4K >> > > > size >> > > > SRAM for SPL, so in SPL stage only support timer, uart, sdram >> > > > driver, >> > > > and back to bootrom when finish ddr initial, and boot up second >> > > > stage >> > > > from bootrom.You can boot to command line(mmc info etc) for now >> > > > use >> > > > this patchset. >> > > > >> > > > Jeffy Chen (2): >> > > >rockchip: Add max init size & chip tag configs >> > > >rockchip: Add support for rk's second level loader >> > > > >> > > > Lin Huang (19): >> > > >rockchip: add timer driver >> > > >rockchip: move SYS_MALLOC_F_LEN to rk3288 own Kconfig >> > > >rockchip: rename board-spl.c to rk3288-board-spl.c >> > > >rockchip: add config decide whether to build common.c >> > > >dm: core: Add SPL Kconfig for REGMAP and SYSCON >> > > >rockchip: serial driver support rk3036 >> > > >rockchip: Bring in RK3036 device tree file includes and >> > > > bindings >> > > >rockchip: rk3036: Add clock driver >> > > >rockchip: rk3036: Add header files for GRF >> > > >rockchip: rk3036: Add Soc reset driver >> > > >rockchip: rk3036: Add a simple syscon driver >> > > >rockchip: rk3036: Add pinctrl driver >> > > >mmc: dw_mmc: support fifo mode in dwc mmc driver >> > > >rockchip: mmc: get the fifo mode and fifo depth property >> > > > from dts >> > > >rockchip: add early uart driver >> > > >rockchip: add rk3036 sdram driver >> > > >rockchip: rk3036: Add core Soc start-up code >> > > >rockchip: Add basic support for evb-rk3036 board >> > > >rockchip: doc: show packet rk3036 uboot image >> > > > >> > > > arch/arm/dts/Makefile | 3 +- >> > > > arch/arm/dts/rk3036-sdk.dts | 46 ++ >> > > > arch/arm/dts/rk3036.dtsi | 428 >> > > > >> > > > arch/arm/include/asm/arch-rockchip/cru_rk3036.h | 168 + >> > > > arch/arm/include/asm/arch-rockchip/grf_rk3036.h | 493 >> > > > ++ >> > > > arch/arm/include/asm/arch-rockchip/sdram_rk3036.h | 341 >> > > > ++ >> > > > arch/arm/include/asm/arch-rockchip/timer.h| 22 + >> > > > arch/arm/include/asm/arch-rockchip/uart.h | 44 ++ >> > > > arch/arm/mach-rockchip/Kconfig| 24 +- >> > > > arch/arm/mach-rockchip/Makefile | 10 +- >> > > > arch/arm/mach-rockchip/board-spl.c| 294 --- >> > > > -- >> > > > arch/arm/mach-rockchip/board.c| 1 + >> > > > arch/arm/mach-rockchip/rk3036-board-spl.c | 53 ++ >> > > > arch/arm/mach-rockchip/rk3036/Kconfig | 23 + >> > > > arch/arm/mach-rockchip/rk3036/Makefile| 13 + >> > > > arch/arm/mach-rockchip/rk3036/reset_rk3036.c | 45 ++ >> > > > arch/arm/mach-rockchip/rk3036/save_boot_param.S | 34 + >> > > > arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 766 >> > > > ++ >> > > > arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 21 + >> > > > arch/arm/mach-rockchip/rk3288-board-spl.c | 277 >> > > > >> > > > arch/arm/mach-rockchip/rk3288/Kconfig | 9 + >> > > > arch/arm/mach-rockchip/rk_early_print.c | 56 ++ >> > > > arch/arm/mach-rockchip/rk_timer.c | 48 ++ >> > > > board/evb_rk3036/evb_rk3036/Kconfig | 15 + >> > > > board/evb_rk3036/evb_rk3036/MAINTAINERS | 0 >> > > > board/evb_rk3036/evb_rk3036/Makefile | 7 + >> > > > board/evb_rk3036/evb_rk3036/evb_rk3036.c | 48 ++ >> > > > configs/chromebook_jerry_defconfig| 2 + >> > > > configs/evb-rk3036_defconfig
Re: [U-Boot] [PATCH] ns16550: change reg-shift property default to zero
On 29 November 2015 at 23:07, Mugunthan V N wrote: > On Sunday 29 November 2015 11:31 AM, Thomas Chou wrote: >> Change reg-shift property default to zero. When the integer property >> is missing, it should be taken as zero. This is consistent to Linux >> drivers/tty/serial/of_serial.c. >> >> The x86 and most powerpc use reg-shift of 0. Most others use reg-shift >> of 2. While reg-shift of 1 is rarely used. >> >> Signed-off-by: Thomas Chou > > Reviewed-by: Mugunthan V N Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] stm32: Convert serial driver to DM
Hi Kamil,
On 29 November 2015 at 03:38, Kamil Lulko wrote:
> Signed-off-by: Kamil Lulko
> ---
> arch/arm/Kconfig | 2 +
> arch/arm/include/asm/arch-stm32f4/stm32.h | 10 +-
> board/st/stm32f429-discovery/stm32f429-discovery.c | 13 +-
> doc/driver-model/serial-howto.txt | 1 -
> drivers/serial/serial_stm32.c | 201
> ++---
> include/configs/stm32f429-discovery.h | 10 +-
> include/dm/platform_data/serial_stm32.h| 16 ++
> 7 files changed, 135 insertions(+), 118 deletions(-)
> create mode 100644 include/dm/platform_data/serial_stm32.h
Looks good, a few nits below.
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 6542c38..a611ad9 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -674,6 +674,8 @@ config ARCH_UNIPHIER
> config TARGET_STM32F429_DISCOVERY
> bool "Support STM32F429 Discovery"
> select CPU_V7M
> + select DM
> + select DM_SERIAL
>
> config ARCH_ROCKCHIP
> bool "Support Rockchip SoCs"
> diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h
> b/arch/arm/include/asm/arch-stm32f4/stm32.h
> index 7ca6dc3..6b64d03 100644
> --- a/arch/arm/include/asm/arch-stm32f4/stm32.h
> +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
> @@ -3,7 +3,7 @@
> * Yuri Tikhonov, Emcraft Systems, y...@emcraft.com
> *
> * (C) Copyright 2015
> - * Kamil Lulko,
> + * Kamil Lulko,
> *
> * SPDX-License-Identifier:GPL-2.0+
> */
> @@ -106,6 +106,14 @@ struct stm32_flash_regs {
> #define STM32_FLASH_CR_SNB_OFFSET 3
> #define STM32_FLASH_CR_SNB_MASK(15 <<
> STM32_FLASH_CR_SNB_OFFSET)
>
> +/*
> + * Peripheral base addresses
> + */
> +#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000)
> +#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400)
> +#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800)
> +#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400)
> +
> enum clock {
> CLOCK_CORE,
> CLOCK_AHB,
> diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c
> b/board/st/stm32f429-discovery/stm32f429-discovery.c
> index f418186..8bc2d9e 100644
> --- a/board/st/stm32f429-discovery/stm32f429-discovery.c
> +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c
> @@ -6,7 +6,7 @@
> * Pavel Boldin, Emcraft Systems, pabol...@emcraft.com
> *
> * (C) Copyright 2015
> - * Kamil Lulko,
> + * Kamil Lulko,
> *
> * SPDX-License-Identifier:GPL-2.0+
> */
> @@ -17,6 +17,8 @@
> #include
> #include
> #include
> +#include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -263,6 +265,15 @@ int dram_init(void)
> return rv;
> }
>
> +static const struct stm32_serial_platdata serial_platdata = {
> + .base = (struct stm32_usart *)STM32_USART1_BASE,
> +};
> +
> +U_BOOT_DEVICE(stm32_serials) = {
> + .name = "serial_stm32",
> + .platdata = &serial_platdata,
> +};
> +
> u32 get_board_rev(void)
> {
> return 0;
> diff --git a/doc/driver-model/serial-howto.txt
> b/doc/driver-model/serial-howto.txt
> index 60483a4..76ad629 100644
> --- a/doc/driver-model/serial-howto.txt
> +++ b/doc/driver-model/serial-howto.txt
> @@ -18,7 +18,6 @@ is time for maintainers to start converting over the
> remaining serial drivers:
> serial_pxa.c
> serial_s3c24x0.c
> serial_sa1100.c
> - serial_stm32.c
> serial_xuartlite.c
> usbtty.c
>
> diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c
> index 8b2830b..df2258e 100644
> --- a/drivers/serial/serial_stm32.c
> +++ b/drivers/serial/serial_stm32.c
> @@ -1,45 +1,18 @@
> /*
> * (C) Copyright 2015
> - * Kamil Lulko,
> + * Kamil Lulko,
> *
> * SPDX-License-Identifier:GPL-2.0+
> */
>
> #include
> +#include
> #include
> #include
> #include
> +#include
>
> -/*
> - * Set up the usart port
> - */
> -#if (CONFIG_STM32_USART >= 1) && (CONFIG_STM32_USART <= 6)
> -#define USART_PORT (CONFIG_STM32_USART - 1)
> -#else
> -#define USART_PORT 0
> -#endif
> -/*
> - * Set up the usart base address
> - *
> - * --STM32_USARTD_BASE means default setting
> - */
> -#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000)
> -#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400)
> -#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800)
> -#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400)
> -#define STM32_USARTD_BASE STM32_USART1_BASE
> -/*
> - * RCC USART specific definitions
> - *
> - * --RCC_ENR_USARTDEN means default setting
> - */
> -#define RCC_ENR_USART1EN (1 << 4)
> -#define RCC_ENR_USART2EN (1 << 17)
> -#define RCC_ENR_USART3EN (1 << 18)
> -#define RCC_ENR_USART6EN (1 << 5)
> -#define RCC_ENR_USARTDEN RCC_ENR_USART1EN
> -
> -struct stm32_serial {
> +struct stm32_usart {
> u32 sr;
> u32 dr;
> u32 brr;
> @@ -49,120 +22,136 @@
Re: [U-Boot] [PATCH v2] common: board_f: Dont relocate FDT incase of CONFIG_OF_EMBED
Hi Michal,
On 27 November 2015 at 00:28, Michal Simek wrote:
> From: Siva Durga Prasad Paladugu
>
> Don't relocate fdt in case of CONFIG_OF EMBED as the fdt is
> already embedded with u-boot image. Also update the fdt_blob
> correctly in this case
>
> Signed-off-by: Siva Durga Prasad Paladugu
> Signed-off-by: Michal Simek
> Reviewed-by: Alexey Brodkin
> ---
>
> Changes in v2:
> - Fix commit message reported by Alexey
>
> common/board_f.c | 11 +--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/common/board_f.c b/common/board_f.c
> index b035c90ff3b7..91bf8beea1c6 100644
> --- a/common/board_f.c
> +++ b/common/board_f.c
> @@ -508,7 +508,7 @@ static int reserve_global_data(void)
> return 0;
> }
>
> -static int reserve_fdt(void)
> +static int __maybe_unused reserve_fdt(void)
> {
> /*
> * If the device tree is sitting immediately above our image then we
> @@ -658,7 +658,7 @@ static int setup_dram_config(void)
> return 0;
> }
>
> -static int reloc_fdt(void)
> +static int __maybe_unused reloc_fdt(void)
> {
> if (gd->flags & GD_FLG_SKIP_RELOC)
> return 0;
> @@ -687,6 +687,9 @@ static int setup_reloc(void)
> gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
> #endif
> #endif
> +#ifdef CONFIG_OF_EMBED
> + gd->fdt_blob += gd->reloc_off;
> +#endif
> memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
>
> debug("Relocation Offset is: %08lx\n", gd->reloc_off);
> @@ -938,7 +941,9 @@ static init_fnc_t init_sequence_f[] = {
> #endif
> setup_machine,
> reserve_global_data,
> +#ifndef CONFIG_OF_EMBED
> reserve_fdt,
> +#endif
Can you please put the #ifdef in the function? At some point we are
hoping to get rid of all these #ifdefs.
> reserve_arch,
> reserve_stacks,
> setup_dram_config,
> @@ -955,7 +960,9 @@ static init_fnc_t init_sequence_f[] = {
> setup_board_extra,
> #endif
> INIT_FUNC_WATCHDOG_RESET
> +#ifndef CONFIG_OF_EMBED
> reloc_fdt,
> +#endif
> setup_reloc,
> #if defined(CONFIG_X86) || defined(CONFIG_ARC)
> copy_uboot_to_ram,
> --
> 1.9.1
>
Regards,
Simon
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Re: [U-Boot] [PATCH v2 16/26] dm: tegra: net: Convert tegra boards to driver model for Ethernet
On Sun, Nov 29, 2015 at 2:18 PM, Simon Glass wrote: > Adjust all Tegra boards to use driver model for Ethernet, now that the > required drivers are converted. > > Signed-off-by: Simon Glass > Reviewed-by: Bin Meng Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 19/26] dm: net: Convert rtl8169 to use DM PCI API
Hi Simon,
On Sun, Nov 29, 2015 at 2:18 PM, Simon Glass wrote:
> Update this driver to use the proper driver-model PCI API functions.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v2:
> - Drop unnecessary and confusing '#ifdef CONFIG_DM_ETH' in rtl8169_eth_probe()
>
> drivers/net/rtl8169.c | 85
> +++
> 1 file changed, 66 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
> index f210005..9e60adf 100644
> --- a/drivers/net/rtl8169.c
> +++ b/drivers/net/rtl8169.c
> @@ -513,8 +513,13 @@ static void rtl_flush_buffer(void *buf, size_t size)
> /**
> RECV - Receive a frame
> ***/
> -static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase,
> +#ifdef CONFIG_DM_ETH
> +static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
> + uchar **packetp)
> +#else
> +static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
>uchar **packetp)
> +#endif
> {
> /* return true if there's an ethernet packet ready to read */
> /* nic->packet should contain data on return */
> @@ -545,9 +550,16 @@ static int rtl_recv_common(pci_dev_t bdf, unsigned long
> dev_iobase,
> else
> tpc->RxDescArray[cur_rx].status =
> cpu_to_le32(OWNbit + RX_BUF_SIZE);
> +#ifdef CONFIG_DM_ETH
> tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
> - pci_mem_to_phys(bdf, (pci_addr_t)(unsigned
> long)
> + dm_pci_mem_to_phys(dev,
> + (pci_addr_t)(unsigned long)
> + tpc->RxBufferRing[cur_rx]));
> +#else
> + tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
> + pci_mem_to_phys(dev, (pci_addr_t)(unsigned
> long)
> tpc->RxBufferRing[cur_rx]));
> +#endif
> rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
> #ifdef CONFIG_DM_ETH
> *packetp = rxdata;
> @@ -576,7 +588,7 @@ int rtl8169_eth_recv(struct udevice *dev, int flags,
> uchar **packetp)
> {
> struct rtl8169_private *priv = dev_get_priv(dev);
>
> - return rtl_recv_common(dm_pci_get_bdf(dev), priv->iobase, packetp);
> + return rtl_recv_common(dev, priv->iobase, packetp);
> }
> #else
> static int rtl_recv(struct eth_device *dev)
> @@ -590,8 +602,13 @@ static int rtl_recv(struct eth_device *dev)
> /**
> SEND - Transmit a frame
> ***/
> -static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase,
> +#ifdef CONFIG_DM_ETH
> +static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
>void *packet, int length)
> +#else
> +static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
> + void *packet, int length)
> +#endif
> {
> /* send the packet to destination */
>
> @@ -618,8 +635,13 @@ static int rtl_send_common(pci_dev_t bdf, unsigned long
> dev_iobase,
> ptxb[len++] = '\0';
>
> tpc->TxDescArray[entry].buf_Haddr = 0;
> +#ifdef CONFIG_DM_ETH
> tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
> - pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb));
> + dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
> +#else
> + tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
> + pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
> +#endif
> if (entry != (NUM_TX_DESC - 1)) {
> tpc->TxDescArray[entry].status =
> cpu_to_le32((OWNbit | FSbit | LSbit) |
> @@ -661,8 +683,7 @@ int rtl8169_eth_send(struct udevice *dev, void *packet,
> int length)
> {
> struct rtl8169_private *priv = dev_get_priv(dev);
>
> - return rtl_send_common(dm_pci_get_bdf(dev), priv->iobase, packet,
> - length);
> + return rtl_send_common(dev, priv->iobase, packet, length);
> }
>
> #else
> @@ -696,7 +717,11 @@ static void rtl8169_set_rx_mode(void)
> RTL_W32(MAR0 + 4, mc_filter[1]);
> }
>
> -static void rtl8169_hw_start(pci_dev_t bdf)
> +#ifdef CONFIG_DM_ETH
> +static void rtl8169_hw_start(struct udevice *dev)
> +#else
> +static void rtl8169_hw_start(pci_dev_t dev)
> +#endif
> {
> u32 i;
>
> @@ -741,11 +766,21 @@ static void rtl8169_hw_start(pci_dev_t bdf)
>
> tpc->cur_rx = 0;
>
> - RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf,
> +
Re: [U-Boot] [PATCH 3/3] net: mvneta: Convert to driver model
On Fri, Nov 27, 2015 at 4:29 AM, Stefan Roese wrote:
> Update this driver to support driver model. As all MVEBU boards using
> this driver are converted with this patch, the non-driver-model code
> can be removed completely. This is also the reason why this patch
> is quite big and includes a) the driver change and b) the
> platform change. As its not git-bisect save otherwise.
>
> With this conversion, some parameters are now extracted from the
> DT instread of using the config header defines. The supported
> properties right now are:
>
> PHY-mode ("phy-mode") and PHY-address ("reg").
>
> The base addresses for the ethernet controllers can be removed from
> the header files as well.
>
> Please note that this patch also removes the E1000 network driver
> from some MVEBU config headers. This is necessary, as with DM_ETH
> configured and the e1000 driver enabled, the PCI driver also needs
> to support DM. But the MVEBU PCI(e) driver still needs to get
> ported to DM. When this is done, the E1000 driver can be enabled
> again.
>
> Signed-off-by: Stefan Roese
> Cc: Luka Perkov
> Cc: Dirk Eibach
> Cc: Joe Hershberger
> Cc: Simon Glass
> ---
> arch/arm/Kconfig| 1 +
> arch/arm/mach-mvebu/cpu.c | 24 ---
> arch/arm/mach-mvebu/include/mach/soc.h | 4 -
> board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 32 ++--
> board/maxbcm/maxbcm.c | 20 ++-
> drivers/net/mvneta.c| 230
>
> include/configs/db-88f6820-gp.h | 3 -
> include/configs/db-mv784mp-gp.h | 4 -
> include/configs/maxbcm.h| 3 -
> 9 files changed, 154 insertions(+), 167 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 2e20212..0c4794b 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -117,6 +117,7 @@ config ARCH_MVEBU
> select OF_CONTROL
> select OF_SEPARATE
> select DM
> + select DM_ETH
All ARM boards? Am I missing something? Seems a bit broad for the
scope of this patch.
> select DM_SERIAL
> select DM_SPI
> select DM_SPI_FLASH
Otherwise, looks good.
-Joe
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Re: [U-Boot] [PATCH 1/4] eth-raw-os.c: Add cast to bind(2) call
On Sat, Nov 28, 2015 at 7:04 AM, Tom Rini wrote: > With more recent gcc versions we otherwise get an error like: > note: expected 'const struct sockaddr *' but argument is of type > 'struct sockaddr_in *' > > and the common solution here is to cast, rather than re-work the code. > > Cc: Joe Hershberger > Cc: Simon Glass > Signed-off-by: Tom Rini Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] usb: eth: add Realtek RTL8152B/RTL8153 driver
Hi Ted, On Tue, Nov 24, 2015 at 11:30 PM, Ted Chen wrote: > From: Ted Chen > > This patch adds driver support for the Realtek RTL8152B/RTL8153 USB > network adapters. > > Signed-off-by: Ted Chen > [swarren, fixed a few compiler warnings] > [swarren, with permission, converted license header to SPDX] > [swarren, removed printf() spew during probe()] > Signed-off-by: Stephen Warren > > Changes for v2: Modified by Marek's comments. > - Remove pattern informations. > - Don't allocate & free when read/write register. > - relpace udelay to mdelay. > - pull firmware into global variable. > - code review. > > Signed-off-by: Ted Chen > --- > drivers/usb/eth/Makefile|1 + > drivers/usb/eth/r8152.c | 3099 > +++ > drivers/usb/eth/usb_ether.c |8 + > include/usb_ether.h |6 + > 4 files changed, 3114 insertions(+) > create mode 100644 drivers/usb/eth/r8152.c > > diff --git a/drivers/usb/eth/Makefile b/drivers/usb/eth/Makefile > index c92d2b0..74f5f87 100644 > --- a/drivers/usb/eth/Makefile > +++ b/drivers/usb/eth/Makefile > @@ -9,3 +9,4 @@ obj-$(CONFIG_USB_ETHER_ASIX) += asix.o > obj-$(CONFIG_USB_ETHER_ASIX88179) += asix88179.o > obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o > obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o > +obj-$(CONFIG_USB_ETHER_RTL8152) += r8152.o > diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c > new file mode 100644 > index 000..345f2c3 > --- /dev/null > +++ b/drivers/usb/eth/r8152.c > @@ -0,0 +1,3099 @@ > +/* > + * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved. > + * > + * SPDX-License-Identifier:GPL-2.0 > + * > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "usb_ether.h" > + > +#define DRIVER_VERSION "v1.0 (2015/11/24)" If this is somehow useful to link back to a Realtek release or something, then in belongs in the commit log, not in the code. > + > +#define R8152_PHY_ID 32 > + 8< snip >8 > + > +/* The forced speed, 10Mb, 100Mb, gigabit, [2.5|5|10|20|25|40|50|56|100]GbE. > */ > +#define SPEED_1010 > +#define SPEED_100 100 > +#define SPEED_1000 1000 > +#define SPEED_2500 2500 > +#define SPEED_5000 5000 > +#define SPEED_1 1 > +#define SPEED_2 2 > +#define SPEED_25000 25000 > +#define SPEED_4 4 > +#define SPEED_5 5 > +#define SPEED_56000 56000 > +#define SPEED_1010 Are all the speeds really relevant to define? They aren't used. Maybe lose all the unused ones. > +#define SPEED_UNKNOWN -1 > + > +/* Duplex, half or full. */ > +#define DUPLEX_HALF 0x00 > +#define DUPLEX_FULL 0x01 > +#define DUPLEX_UNKNOWN 0xff > + > +/* Enable or disable autonegotiation. */ > +#define AUTONEG_DISABLE 0x00 > +#define AUTONEG_ENABLE 0x01 > + > + > +/* Generic MII registers. */ > +#define MII_BMCR0x00/* Basic mode control register */ > +#define MII_BMSR0x01/* Basic mode status register */ > +#define MII_PHYSID1 0x02/* PHYS ID 1 */ > +#define MII_PHYSID2 0x03/* PHYS ID 2 */ > +#define MII_ADVERTISE 0x04/* Advertisement control reg */ > +#define MII_LPA 0x05/* Link partner ability reg*/ > +#define MII_EXPANSION 0x06/* Expansion register */ > +#define MII_CTRL10000x09/* 1000BASE-T control */ > +#define MII_STAT10000x0a/* 1000BASE-T status */ > +#define MII_MMD_CTRL0x0d/* MMD Access Control Register */ > +#define MII_MMD_DATA0x0e/* MMD Access Data Register */ > +#define MII_ESTATUS 0x0f/* Extended Status */ > +#define MII_DCOUNTER0x12/* Disconnect counter */ > +#define MII_FCSCOUNTER 0x13/* False carrier counter */ > +#define MII_NWAYTEST0x14/* N-way auto-neg test reg */ > +#define MII_RERRCOUNTER 0x15/* Receive error counter */ > +#define MII_SREVISION 0x16/* Silicon revision*/ > +#define MII_RESV1 0x17/* Reserved... */ > +#define MII_LBRERROR0x18/* Lpback, rx, bypass error*/ > +#define MII_PHYADDR 0x19/* PHY address */ > +#define MII_RESV2 0x1a/* Reserved... */ > +#define MII_TPISTATUS 0x1b/* TPI status for 10mbps */ > +#define MII_NCONFIG 0x1c/* Network interface config*/ > + > +#define agg_buf_sz 2048 > + > +/* local vars */ > +static int curr_eth_dev; /* index for name of next device detec
[U-Boot] [PULL] u-boot-atmel/master -> u-boot/master
Hi Tom, please pull the following changes into u-boot/master Andreas The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757: Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03 -0500) are available in the git repository at: git://git.denx.de/u-boot-atmel.git master for you to fetch changes up to e4677f1ae221ac615f32c993aaf3d2497ad5009d: arm: at91/spl: atmel_sfr: move saic redirect to separate file (2015-11-30 22:27:55 +0100) Wenyou Yang (7): gpio: atmel: Add the PIO4 driver support arm: atmel: Add SAMA5D2 Xplained board arm: at91/spl: matrix: move matrix init to separate file arm: at91/spl: matrix: remove matrix write protection code arm: at91/spl: matrix: remove security peripheral select code arm: at91/spl: matrix: use matrix slave id macros arm: at91/spl: atmel_sfr: move saic redirect to separate file arch/arm/mach-at91/Kconfig | 5 + arch/arm/mach-at91/Makefile | 2 +- arch/arm/mach-at91/armv7/Makefile| 1 + arch/arm/mach-at91/armv7/sama5d2_devices.c | 57 + arch/arm/mach-at91/armv7/sama5d4_devices.c | 55 - arch/arm/mach-at91/atmel_sfr.c | 21 ++ arch/arm/mach-at91/include/mach/at91_pmc.h | 9 +- arch/arm/mach-at91/include/mach/atmel_pio4.h | 48 arch/arm/mach-at91/include/mach/atmel_usba_udc.h | 3 +- arch/arm/mach-at91/include/mach/hardware.h | 2 + arch/arm/mach-at91/include/mach/sama5_sfr.h | 1 - arch/arm/mach-at91/include/mach/sama5d2.h| 203 arch/arm/mach-at91/include/mach/sama5d4.h| 28 +++ arch/arm/mach-at91/matrix.c | 34 +++ board/atmel/sama5d2_xplained/Kconfig | 15 ++ board/atmel/sama5d2_xplained/MAINTAINERS | 7 + board/atmel/sama5d2_xplained/Makefile| 8 + board/atmel/sama5d2_xplained/sama5d2_xplained.c | 283 ++ configs/sama5d2_xplained_mmc_defconfig | 11 + configs/sama5d2_xplained_spiflash_defconfig | 11 + drivers/gpio/Kconfig | 11 + drivers/gpio/Makefile| 1 + drivers/gpio/atmel_pio4.c| 296 +++ include/configs/sama5d2_xplained.h | 122 ++ 24 files changed, 1171 insertions(+), 63 deletions(-) create mode 100644 arch/arm/mach-at91/armv7/sama5d2_devices.c create mode 100644 arch/arm/mach-at91/atmel_sfr.c create mode 100644 arch/arm/mach-at91/include/mach/atmel_pio4.h create mode 100644 arch/arm/mach-at91/include/mach/sama5d2.h create mode 100644 arch/arm/mach-at91/matrix.c create mode 100644 board/atmel/sama5d2_xplained/Kconfig create mode 100644 board/atmel/sama5d2_xplained/MAINTAINERS create mode 100644 board/atmel/sama5d2_xplained/Makefile create mode 100644 board/atmel/sama5d2_xplained/sama5d2_xplained.c create mode 100644 configs/sama5d2_xplained_mmc_defconfig create mode 100644 configs/sama5d2_xplained_spiflash_defconfig create mode 100644 drivers/gpio/atmel_pio4.c create mode 100644 include/configs/sama5d2_xplained.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 5/5] arm: at91/spl: atmel_sfr: move saic redirect to separate file
Dear Wenyou Yang, Wenyou Yang writes: >To make saic redirect code sharing with other SoCs, move the >saic redirect code from SAMA5D4 particular file, >mach-at91/armv7/sama5d4_devices.c to a separate file, >mach-at91/atmel_sfr.c > >Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each >SoC has its own value. > >Signed-off-by: Wenyou Yang >Reviewed-by: Andreas Bießmann >--- > >Changes in v2: > 1./ split the version 1 [PATCH 2/3] into three patches for > more legible. > > arch/arm/mach-at91/Makefile |2 +- > arch/arm/mach-at91/armv7/sama5d4_devices.c | 13 - > arch/arm/mach-at91/atmel_sfr.c | 21 + > arch/arm/mach-at91/include/mach/sama5_sfr.h |1 - > arch/arm/mach-at91/include/mach/sama5d4.h |3 +++ > 5 files changed, 25 insertions(+), 15 deletions(-) > create mode 100644 arch/arm/mach-at91/atmel_sfr.c applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 4/5] arm: at91/spl: matrix: use matrix slave id macros
Dear Wenyou Yang, Wenyou Yang writes: >To make matrix initialization code sharing with others, >use the matrix slave id macros, instead of hard-coding. > >Signed-off-by: Wenyou Yang >Reviewed-by: Andreas Bießmann >--- > >Changes in v2: None > > arch/arm/mach-at91/include/mach/sama5d4.h | 25 + > arch/arm/mach-at91/matrix.c | 18 +- > 2 files changed, 34 insertions(+), 9 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 3/5] arm: at91/spl: matrix: remove security peripheral select code
Dear Wenyou Yang, Wenyou Yang writes: >Remove the security peripheral select code, keep the default value >in these registers, that is, the peripheral address space is >configured as "Secured" access, it is suitable for SPL. > >Signed-off-by: Wenyou Yang >Reviewed-by: Andreas Bießmann >--- > >Changes in v2: None > > arch/arm/mach-at91/matrix.c |9 - > 1 file changed, 9 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 2/5] arm: at91/spl: matrix: remove matrix write protection code
Dear Wenyou Yang, Wenyou Yang writes: >On processor reset, the matrix write protection is disabled, >so no need to disable/enable write protection when writing >the matrix registers. > >Signed-off-by: Wenyou Yang >Reviewed-by: Andreas Bießmann >--- > >Changes in v2: None > > arch/arm/mach-at91/matrix.c |8 > 1 file changed, 8 deletions(-) applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot, v2, 1/5] arm: at91/spl: matrix: move matrix init to separate file
Dear Wenyou Yang, Wenyou Yang writes: >To make the matrix initialization code sharing with other SoCs, >move it from SAMA5D4 particular file, >mach-at91/armv7/sama5d4_devices.c to a separate file, >mach-at91/matrix.c > >Signed-off-by: Wenyou Yang >Reviewed-by: Andreas Bießmann >--- > >Changes in v2: None > > arch/arm/mach-at91/Makefile|2 +- > arch/arm/mach-at91/armv7/sama5d4_devices.c | 42 --- > arch/arm/mach-at91/matrix.c| 51 > 3 files changed, 52 insertions(+), 43 deletions(-) > create mode 100644 arch/arm/mach-at91/matrix.c applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,v6] arm: atmel: Add SAMA5D2 Xplained board
Dear Wenyou Yang, Wenyou Yang writes: >The board supports following features: > - Boot media support: SD card/e.MMC/SPI flash, > - Support LCD display (optional, disabled by default), > - Support ethernet, > - Support USB mass storage. > >Signed-off-by: Wenyou Yang >[fix checkpatch warnings] >Signed-off-by: Andreas Bießmann >--- >The patch is based on the following patches sent in mailing list. > [PATCH] gpio: atmel: Add the PIO4 driver support > [PATCH] arm: at91: Change the Chip ID registers' addresses > [PATCH v4] mmc: atmel: Add atmel sdhci support > [PATCH v3] arm: at91: clock: Add the generated clock support > >Changes in v6: > 1./ change function invocation due to its declaration change, > at91_enable_periph_generated_clk(). > >Changes in v5: > 1./ remove wrong pin config for USB hw init. > >Changes in v4: > 1./ remove __weak attribute for has_lcdc() added in v3. > 2./ remove unused goto err_exit. > >Changes in v3: > 1./ change defines-->definitions for more clearly in asm/arch/sama5d2.h. > 2./ remove unused cpu_is_sama5d2x() macros. > 3./ fix spelling error "adress". > 4./ add __weak attribute for has_lcdc(). > 5./ remove SPL configs. > >Changes in v2: > 1./ re-order SAMA5D2 statements alphabetically. > 2./ remove redundant "Unknown CPU type". > 3./ rework sama5d2's macros. > 4./ remove some #ifdef before functions. > 5./ move CONFIG_CMD_SF to Kconfig. > 6./ remove NAND macros from config file. > 7./ CONFIG_BOOTCOMMAND for sf uses defines in at91-sama5_common.h. > > arch/arm/mach-at91/Kconfig |5 + > arch/arm/mach-at91/armv7/Makefile|1 + > arch/arm/mach-at91/armv7/sama5d2_devices.c | 59 + > arch/arm/mach-at91/include/mach/at91_pmc.h |9 +- > arch/arm/mach-at91/include/mach/atmel_usba_udc.h |3 +- > arch/arm/mach-at91/include/mach/hardware.h |2 + > arch/arm/mach-at91/include/mach/sama5d2.h| 203 > board/atmel/sama5d2_xplained/Kconfig | 15 ++ > board/atmel/sama5d2_xplained/MAINTAINERS |7 + > board/atmel/sama5d2_xplained/Makefile|8 + > board/atmel/sama5d2_xplained/sama5d2_xplained.c | 284 ++ > configs/sama5d2_xplained_mmc_defconfig | 11 + > configs/sama5d2_xplained_spiflash_defconfig | 11 + > include/configs/sama5d2_xplained.h | 122 ++ > 14 files changed, 734 insertions(+), 6 deletions(-) > create mode 100644 arch/arm/mach-at91/armv7/sama5d2_devices.c > create mode 100644 arch/arm/mach-at91/include/mach/sama5d2.h > create mode 100644 board/atmel/sama5d2_xplained/Kconfig > create mode 100644 board/atmel/sama5d2_xplained/MAINTAINERS > create mode 100644 board/atmel/sama5d2_xplained/Makefile > create mode 100644 board/atmel/sama5d2_xplained/sama5d2_xplained.c > create mode 100644 configs/sama5d2_xplained_mmc_defconfig > create mode 100644 configs/sama5d2_xplained_spiflash_defconfig > create mode 100644 include/configs/sama5d2_xplained.h applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot,v3] gpio: atmel: Add the PIO4 driver support
Dear Wenyou Yang, Wenyou Yang writes: >The PIO4 is introduced from SAMA5D2, as a new version >for Atmel PIO controller. > >Signed-off-by: Wenyou Yang >--- > >Changes in v3: > 1./ add return to atmel_pio4_set_pio_output() to avoid compilation > warning. > >Changes in v2: > 1./ update the macro definitions according to the latest datasheet. > 2./ change the return value to -ENODEV. > 3./ add check to port_base, pin and return -ENODEV. > 4./ change the return value for set/get_pio_output/input function. > > arch/arm/mach-at91/include/mach/atmel_pio4.h | 48 + > drivers/gpio/Kconfig | 11 + > drivers/gpio/Makefile|1 + > drivers/gpio/atmel_pio4.c| 296 ++ > 4 files changed, 356 insertions(+) > create mode 100644 arch/arm/mach-at91/include/mach/atmel_pio4.h > create mode 100644 drivers/gpio/atmel_pio4.c applied to u-boot-atmel/master, thanks! Best regards, Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net: gem: Enable CTRL+C in wait_for_bit
Hi Michal,
On Thu, Nov 26, 2015 at 3:46 AM, Michal Simek wrote:
> Enable to break waiting loop at any time.
>
> Signed-off-by: Michal Simek
> ---
>
> drivers/net/zynq_gem.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
> index 858093f0d7e2..ee4169107e5b 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -447,6 +447,11 @@ static int wait_for_bit(const char *func, u32 *reg,
> const u32 mask,
> if (get_timer(start) > timeout)
> break;
>
> + if (ctrlc()) {
> + puts("Abort\n");
> + return -1;
Maybe this should return -EINTR?
> + }
> +
> udelay(1);
> }
>
> --
> 1.9.1
>
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Re: [U-Boot] [PATCH] common: miiphyutil: avoid memory leak
Hi Peng On Wed, Nov 25, 2015 at 8:26 PM, Peng Fan wrote: > The following code will alloc memory for new_dev and ldev: > " > new_dev = mdio_alloc(); > ldev = malloc(sizeof(*ldev)); > " > Either new_dev or ldev is NULL, directly return, but this may leak memory. > So before return, using free(ldev) and mdio_free(new_dev) to avoid > leaking memory, also free can handle NULL pointer. > > Signed-off-by: Peng Fan > Cc: Joe Hershberger > Cc: Simon Glass > Cc: Bin Meng Acked-by: Joe Hershberger ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-cfi-flash/master
On Mon, Nov 30, 2015 at 01:02:56PM +0100, Stefan Roese wrote: > Hi Tom, > > please pull this small CFI patch: > > The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757: > > Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03 > -0500) > > are available in the git repository at: > > git://www.denx.de/git/u-boot-cfi-flash.git > > for you to fetch changes up to 5aeeabf43c27b1bf4b3bb86e2b713dd98801df63: > > cfi_flash: give default CONFIG_SYS_MAX_FLASH_SECT in flash.h (2015-11-30 > 13:00:00 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-ppc4xx/master
On Mon, Nov 30, 2015 at 12:56:45PM +0100, Stefan Roese wrote: > Hi Tom, > > please pull those 2 pending patches: > > The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757: > > Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03 > -0500) > > are available in the git repository at: > > git://www.denx.de/git/u-boot-ppc4xx.git > > for you to fetch changes up to 6623aee5b6aba2f8efe9b7d2417f090f9c2b3cd3: > > PPC4xx: Create "liebherr" vendor directory (2015-11-30 12:50:29 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PULL] u-boot-socfpga/master
On Mon, Nov 30, 2015 at 01:31:12PM +0100, Marek Vasut wrote: > The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757: > > Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03 > -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-socfpga.git > > for you to fetch changes up to 486f4fa98c65baa6d70008ceb2d93ac0f8f7bd96: > > arm: socfpga: Remove fsloadcmd from environment (2015-11-30 13:30:19 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] please pull u-boot-samsung master
On Mon, Nov 30, 2015 at 05:33:14PM +0900, Minkyu Kang wrote: > Dear Tom, > > The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757: > > Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03 > -0500) > > are available in the git repository at: > > > http://git.denx.de/u-boot-samsung > > for you to fetch changes up to 225f5eeccd6c0d376a20c15897edd8c69500d8cc: > > arm: s5pc1xx: move SoC to mach-s5pc1xx (2015-11-30 17:17:01 +0900) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-video/master
On Mon, Nov 30, 2015 at 09:28:03AM +0100, Anatolij Gustschin wrote: > Hello Tom, > > The following changes since commit 736d1746fb7b8f7cd70657a4a72db2b6bd8de40e: > > itest: add missing break statements to evalexp() (2015-11-18 15:29:00 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-video.git master > > for you to fetch changes up to 3dbdb4dd4f8e5847b8f7d6dbd849e0b9a0907a5b: > > video: ipu: fix out of bounds access (2015-11-30 09:18:36 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Please pull u-boot-marvell master
On Sun, Nov 29, 2015 at 09:20:05PM +, Luka Perkov wrote: > Hi Tom, > > please pull the queued changes below from Marvell tree. Additional work from > Stefan will be sent later on. > > The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757: > > Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03 > -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-marvell.git > > for you to fetch changes up to f1df81c4008c8e0edbc1a2738cf2490b2f7be661: > > arm: kirkwood: add ZyXEL NSA310S device (2015-11-29 22:16:14 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Enable console log from earlyconsole in Linux bootargs
On 10/31/2015 03:20 AM, Pratiyush Mohan Srivastava wrote: > Remove 115200 from "earlycon" to avoid loss of initial > log messages during linux kernel 4.1 bootup > > Signed-off-by: Pratiyush Mohan Srivastava > --- > include/configs/ls2080a_common.h | 2 +- > include/configs/ls2080ardb.h | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/include/configs/ls2080a_common.h > b/include/configs/ls2080a_common.h > index 31f6441..c39e294 100644 > --- a/include/configs/ls2080a_common.h > +++ b/include/configs/ls2080a_common.h > @@ -263,7 +263,7 @@ unsigned long long get_qixis_addr(void); > "console=ttyAMA0,38400n8\0" > > #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ > - "earlycon=uart8250,mmio,0x21c0500,115200 " \ > + "earlycon=uart8250,mmio,0x21c0500" \ > "ramdisk_size=0x200 default_hugepagesz=2m" \ > " hugepagesz=2m hugepages=16" > #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ > diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h > index 69bac8b..23d121a 100644 > --- a/include/configs/ls2080ardb.h > +++ b/include/configs/ls2080ardb.h > @@ -314,7 +314,7 @@ unsigned long get_board_sys_clk(void); > > #undef CONFIG_BOOTARGS > #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ > - "earlycon=uart8250,mmio,0x21c0600,115200 " \ > + "earlycon=uart8250,mmio,0x21c0600" \ > "ramdisk_size=0x200 default_hugepagesz=2m" \ > " hugepagesz=2m hugepages=16" > > This has no negative effect on 4.0 and 3.x kernel, does it? I didn't notice the message difference for 4.0.4. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] arm: socfpga: Remove cpu_mmc_init()
This function triggers the registration of the dwmmc driver on SoCFPGA,
but this is not needed in case the driver is correctly probed from DT.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Pantelis Antoniou
Cc: Simon Glass
Cc: Tom Rini
---
arch/arm/mach-socfpga/misc.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index bbd31ef..b110f5b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -130,17 +130,6 @@ int cpu_eth_init(bd_t *bis)
}
#endif
-#ifdef CONFIG_DWMMC
-/*
- * Initializes MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(bd_t *bis)
-{
- return socfpga_dwmmc_init(gd->fdt_blob);
-}
-#endif
-
struct {
const char *mode;
const char *name;
--
2.1.4
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[U-Boot] [PATCH 3/3] arm: socfpga: Enable CONFIG_DM_MMC
Enable driver model MMC support on SoCFPGA. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen Cc: Pantelis Antoniou Cc: Simon Glass Cc: Tom Rini --- configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + 6 files changed, 6 insertions(+) diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index b4c23d9..f59bc00 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -20,3 +20,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index ac7bd0b..c0d6913 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -20,3 +20,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index d21029f..a4f75e6 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -18,3 +18,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 97f6c5d..382db65 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -18,3 +18,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index d3b9c89..03f8eff 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -22,3 +22,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 462b2fd..ad8ed6d 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -20,3 +20,4 @@ CONFIG_ETH_DESIGNWARE=y CONFIG_SYS_NS16550=y CONFIG_CADENCE_QSPI=y CONFIG_DESIGNWARE_SPI=y +CONFIG_DM_MMC=y -- 2.1.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] mmc: dwmmc: socfpga: Convert to DM
Convert the SoCFPGA shim for registering the DWMMC driver to DM.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Pantelis Antoniou
Cc: Simon Glass
Cc: Tom Rini
---
drivers/mmc/socfpga_dw_mmc.c | 119 ---
1 file changed, 56 insertions(+), 63 deletions(-)
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 8076761..dd2b30a 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -5,20 +5,28 @@
*/
#include
-#include
-#include
-#include
-#include
-#include
-#include
#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_clock_manager *clock_manager_base =
(void *)SOCFPGA_CLKMGR_ADDRESS;
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
+struct socfpga_dwmmc_priv {
+ struct dwmci_host host;
+};
+
static void socfpga_dwmci_clksel(struct dwmci_host *host)
{
unsigned int drvsel;
@@ -44,87 +52,72 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
}
-static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
+static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
{
/* FIXME: probe from DT eventually too/ */
const unsigned long clk = cm_get_mmc_controller_clk_hz();
- struct dwmci_host *host;
- fdt_addr_t reg_base;
- int bus_width, fifo_depth;
+ struct socfpga_dwmmc_priv *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+ int fifo_depth;
if (clk == 0) {
- printf("DWMMC%d: MMC clock is zero!", idx);
+ printf("DWMMC: MMC clock is zero!");
return -EINVAL;
}
- /* Get the register address from the device node */
- reg_base = fdtdec_get_addr(blob, node, "reg");
- if (!reg_base) {
- printf("DWMMC%d: Can't get base address\n", idx);
- return -EINVAL;
- }
-
- /* Get the bus width from the device node */
- bus_width = fdtdec_get_int(blob, node, "bus-width", 0);
- if (bus_width <= 0) {
- printf("DWMMC%d: Can't get bus-width\n", idx);
- return -EINVAL;
- }
-
- fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
+ fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "fifo-depth", 0);
if (fifo_depth < 0) {
- printf("DWMMC%d: Can't get FIFO depth\n", idx);
+ printf("DWMMC: Can't get FIFO depth\n");
return -EINVAL;
}
- /* Allocate the host */
- host = calloc(1, sizeof(*host));
- if (!host)
- return -ENOMEM;
-
- host->name = "SOCFPGA DWMMC";
- host->ioaddr = (void *)reg_base;
- host->buswidth = bus_width;
+ host->name = dev->name;
+ host->ioaddr = (void *)dev_get_addr(dev);
+ host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "bus-width", 4);
host->clksel = socfpga_dwmci_clksel;
- host->dev_index = idx;
+
+ /*
+* TODO(s...@chromium.org): Remove the need for this hack.
+* We only have one dwmmc block on gen5 SoCFPGA.
+*/
+ host->dev_index = 0;
/* Fixed clock divide by 4 which due to the SDMMC wrapper */
host->bus_hz = clk;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
- return add_dwmci(host, host->bus_hz, 40);
-}
-
-static int socfpga_dwmci_process_node(const void *blob, int nodes[],
- int count)
-{
- int i, node, ret;
-
- for (i = 0; i < count; i++) {
- node = nodes[i];
- if (node <= 0)
- continue;
-
- ret = socfpga_dwmci_of_probe(blob, node, i);
- if (ret) {
- printf("%s: failed to decode dev %d\n", __func__, i);
- return ret;
- }
- }
return 0;
}
-int socfpga_dwmmc_init(const void *blob)
+static int socfpga_dwmmc_probe(struct udevice *dev)
{
- int nodes[2]; /* Max. two controllers. */
- int ret, count;
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct socfpga_dwmmc_priv *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+ int ret;
- count = fdtdec_find_aliases_for_id(blob, "mmc",
- COMPAT_ALTERA_SOCFPGA_DWMMC,
- nodes, ARRAY_SIZE(nodes));
+ ret = add_dwmci(host, host->bus_hz, 40);
+ if (ret)
+ retu
Re: [U-Boot] [PATCH v3] arm: ls2080a: Add sata support on qds and rdb board
On 10/23/2015 12:16 AM, Tang Yuantian wrote: > Freescale ARM-based Layerscape LS2080A contain a SATA controller > which comply with the serial ATA 3.0 specification and the > AHCI 1.3 specification. > This patch adds SATA feature on ls2080aqds and ls2080ardb boards. > > Signed-off-by: Tang Yuantian > --- > depends on patches: > http://patchwork.ozlabs.org/patch/530576/ > armv8: LS2080A: Rename LS2085A to reflect LS2080A > http://patchwork.ozlabs.org/patch/530575/ > armv8: ls2085a: Add support of LS2085A SoC > v3: > - rename ls2085a to ls2080a > - rebase to the latest git tree > - replace the magic number with micro variable > v2: > - rebase to the latest git tree > Yuantian, The dependency patches have been updated and merged. Please rebase your patch and test on the new base git://git.denx.de/u-boot-fsl-qoriq.git master. Thanks. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Please pull u-boot-fsl-qoriq master
Tom,
The following changes since commit fa8883a1e39a20e72aaa5093af0c80062cb95757:
Merge branch 'master' of git://git.denx.de/u-boot-i2c (2015-11-27 08:41:03
-0500)
are available in the git repository at:
git://git.denx.de/u-boot-fsl-qoriq.git master
for you to fetch changes up to 3785f57015dbd7582f85fd1c34dcaa26638bf976:
armv8: fsl-layerscape: Fix early MMU table for nand boot (2015-11-30 09:11:13
-0800)
Alison Wang (5):
arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit
arm: ls1021a: Ensure Generic Timer disabled before jumping into the OS
armv8/layerscape: Update MMU table with execute-never bits
arm: ls102xa: Update fdt_high and initrd_high for LS1021AQDS board
armv8: ls2080a: Define CONFIG_ENV_OVERWRITE to overwrite serial and
ethaddr
Gong Qianyu (5):
armv8/fsl-layerscape: Remove reference to gdata
armv8/ls1043ardb: dts: add dtb support
armv8/ls1043aqds: dts: add dtb support
armv8/ls1043ardb: add DSPI support
armv8/ls1043ardb: add USB support
Mingkai Hu (1):
pci/layerscape: add support for LS1043A PCIe LUT register access
Prabhakar Kushwaha (15):
armv8: lsch3: Fix lane protocol parsing logic
driver: net: fsl-mc: Add create, destroy APIs in flibs
driver: net: fsl-mc: Add APIs for DPMAC objects in FLIB
armv8: ls2085aqds: Print function name during SerDes error
driver: ldpaa: Add api to return linked PHY ID of DPMAC
driver: net: fsl-mc: Increase MC command timeout
driver: net: fsl-mc: Add DPAA2 commands to manage MC
driver: net: fsl-mc: Create DPAA2 object at run-time
driver: net: ldpaa: Use DPMAC as net device
driver: net: ldpaa: Add debug information
driver: net: ldpaa: Fix Rx buffer alignment
armv8: LS2080A: Rename LS2085A to reflect LS2080A
armv8: ls2085a: Add support of LS2085A SoC
board/ls2080qds: Fix typo in README for QSGMII riser card
armv8: ls2085a: Add workaround of errata A009635
Shaohui Xie (2):
armv8/ls1043aqds: add LS1043AQDS board support
net: phy: added aquantia PHY AQR405 support
York Sun (4):
drivers/ddr/fsl: Enable detection of one DDR controller operation for
LSCH3
drivers/ddr/fsl: Fix typo in BIST test for DDR4
armv8: fsl-layerscape: Fix "cpu release" command
armv8: fsl-layerscape: Fix early MMU table for nand boot
README |3 +
arch/arm/Kconfig | 53 +-
arch/arm/cpu/armv7/ls102xa/cpu.c | 10 +
arch/arm/cpu/armv7/ls102xa/timer.c |3 +-
arch/arm/cpu/armv8/cache_v8.c |4 +-
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 10 +-
arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 | 85 ++-
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 10 +-
arch/arm/cpu/armv8/fsl-layerscape/fdt.c|2 +-
.../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 25 +-
.../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 11 +
.../{ls2085a_serdes.c => ls2080a_serdes.c} |5 +
arch/arm/cpu/armv8/fsl-layerscape/mp.c |6 +
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 45 +-
arch/arm/cpu/armv8/fsl-layerscape/spl.c|6 +-
arch/arm/dts/Makefile |6 +-
arch/arm/dts/fsl-ls1043a-qds.dts | 124 +++
arch/arm/dts/fsl-ls1043a-rdb.dts | 103 +++
arch/arm/dts/fsl-ls1043a.dtsi | 186 +
.../{fsl-ls2085a-qds.dts => fsl-ls2080a-qds.dts} |8 +-
.../{fsl-ls2085a-rdb.dts => fsl-ls2080a-rdb.dts} |8 +-
.../arm/dts/{fsl-ls2085a.dtsi => fsl-ls2080a.dtsi} |4 +-
arch/arm/include/asm/arch-fsl-layerscape/config.h | 26 +-
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 87 ++-
arch/arm/include/asm/arch-fsl-layerscape/fdt.h |1 +
.../include/asm/arch-fsl-layerscape/fsl_serdes.h |2 +-
.../include/asm/arch-fsl-layerscape/immap_lsch2.h | 10 +-
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 10 +-
.../{ls2085a_stream_id.h => ls2080a_stream_id.h} |4 +-
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 11 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |2 +-
arch/arm/include/asm/armv8/mmu.h |2 +-
arch/arm/include/asm/global_data.h |2 +-
board/freescale/common/vid.c | 22 +
board/freescale/ls1043aqds/Kconfig | 15 +
board/freescale/ls1043aqds/MAINTAINERS |9 +
board/freescale/ls1043aqds/Makefile|9 +
board/freescale/ls1043aqds/README | 96 +++
board/freescale/ls1043aqds/ddr.c | 131
board/freescale/ls1043aqds/ddr.h | 60 ++
board/freescale/ls1043aqds/eth.c
Re: [U-Boot] [PATCH v2] armv8: fsl-layerscape: Fix early MMU table for nand boot
On 11/25/2015 08:41 PM, York Sun wrote: > The early MMU table doesn't enable all addresses. Unused addresses > are marked as invalid, as introduced by commit 9979922. An entry > was missing for NAND flash space, causing nand boot failure. > > Signed-off-by: York Sun > CC: Alison Wang > CC: Prabhakar Kushwaha > > --- > > Changes in v2: > Reduce the IFC mapped for early MMU, up to NOR flash base to > avoid conflict > Tested on LS2085AQDS > > arch/arm/include/asm/arch-fsl-layerscape/cpu.h |4 > 1 file changed, 4 insertions(+) Applied to fsl-qoriq master. York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: mx6: Reduce SPL malloc pool size
On Wed, Nov 25, 2015 at 5:32 AM, Marek Vasut wrote: > On Wednesday, November 25, 2015 at 02:15:13 PM, Przemyslaw Marczak wrote: >> On 11/25/2015 01:16 PM, Marek Vasut wrote: >> > On Wednesday, November 25, 2015 at 01:00:41 PM, Przemyslaw Marczak wrote: >> >> Hello Marek, >> >> >> >> On 11/25/2015 11:56 AM, Marek Vasut wrote: >> >>> On Wednesday, November 25, 2015 at 11:40:36 AM, Przemyslaw Marczak wrote: >> Hello Tim, Marek >> >> On 11/20/2015 10:40 PM, Tim Harvey wrote: >> > On Fri, Nov 20, 2015 at 12:43 PM, Marek Vasut wrote: >> >> Using 50 MiB malloc pool in SPL is nonsense. Since the caches are >> >> not enabled in SPL, it takes 2 seconds to init the pool and has no >> >> obvious benefit. Reduce the size to 1 MiB. >> >> >> >> Signed-off-by: Marek Vasut >> >> Cc: Stefano Babic >> >> Cc: Tim Harvey >> >> --- >> >> >> >> include/configs/imx6_spl.h | 6 +++--- >> >> 1 file changed, 3 insertions(+), 3 deletions(-) >> >> >> >> diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h >> >> index 1744f2c..43ce7fe 100644 >> >> --- a/include/configs/imx6_spl.h >> >> +++ b/include/configs/imx6_spl.h >> >> @@ -63,15 +63,15 @@ >> >> >> >> #if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || >> >> defined(CONFIG_MX6SL) #define CONFIG_SPL_BSS_START_ADDR >> >> 0x8820 >> >> >> >> -#define CONFIG_SPL_BSS_MAX_SIZE0x10/* 1 MB */ >> >> +#define CONFIG_SPL_BSS_MAX_SIZE0x10/* 1 >> >> MB */ >> >> >> >> #define CONFIG_SYS_SPL_MALLOC_START0x8830 >> >> >> >> -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x320 /* 50 MB */ >> >> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10/* 1 >> >> MB */ >> >> >> >> #define CONFIG_SYS_TEXT_BASE 0x8780 >> >> #else >> >> #define CONFIG_SPL_BSS_START_ADDR 0x1820 >> >> #define CONFIG_SPL_BSS_MAX_SIZE0x10 >> >> /* 1 MB */ #define CONFIG_SYS_SPL_MALLOC_START0x1830 >> >> >> >> -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x320 /* 50 MB */ >> >> +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10/* 1 MB */ >> >> >> >> #define CONFIG_SYS_TEXT_BASE 0x1780 >> >> #endif >> >> #endif >> >> >> >> -- >> >> 2.1.4 >> > >> > Acked-by: Tim Harvey >> > >> > thanks for dropping 2 secs off our time to boot! >> > >> > Tim >> >> The boot time for SPL and U-Boot can be reduced more if >> CONFIG_SYS_MALLOC_CLEAR_ON_INIT is unset (default is set). >> >>> >> >>> This might confuse DM, so I don't want this. DM checks if it's >> >>> structures were already inited and if we don't clear the malloc area, >> >>> they would be. >> >> >> >> DM is safe - it uses calloc() for it's structures and also driver's >> >> static structures are zeroed. Only some private data which is not >> >> allocated by DM can be risky to use. >> >> >> >> To be precise - we don't use malloc() to get pointer for zeroed memory, >> >> this is the job for the calloc(). >> >> >> >> So any code with bad use of malloc() should be fixed ASAP. >> >> >> >> If you assume that clear the malloc pool at boot is safe to use, then >> >> I'm asking you, what about the sequence malloc/free/malloc for >> >> potentially the same area? You can't be sure that the second returned >> >> pointer after calling free() - points to the initially zeroed pool. >> >> >> >> We don't clean the malloc pool for configs that we maintain and we >> >> didn't noticed any issues related to this. And the boot time is reduced >> >> significantly. >> > >> > Do you use DM in SPL ? >> >> No, we don't use the SPL - for the boards which we maintain. > > OK > >> > I just checked and I see it's probably only the GD which needs to be >> > cleared out, so we should indeed be safe. In which case, patch is >> > welcome to enable CONFIG_SYS_MALLOC_CLEAR_ON_INIT . >> >> Yes I can see also for the Exynos SPL, that GD is manually cleared. >> >> But disabling the default CONFIG_SYS_MALLOC_CLEAR_ON_INIT, will help you >> in reducing the U-Boot init time. >> Just try and if you can easy measure the real difference for >> enable/disable this config - share the results - it can give us an >> interesting conclusions. > > Sure, thanks for the hint, but I still don't see any reason for having 50 MiB > malloc area in SPL ;-) Perhaps the use case for a >1MB malloc area is falcon mode. While a 1MB area certainly works for loading and bootstrapping to u-boot.img I have used anywhere from 1MB to 8MB images for falcon mode. Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] usb: add support for generic EHCI devices
On Monday, November 30, 2015 at 07:13:30 PM, Alexey Brodkin wrote:
> Hi Marek,
Hi!
> On Mon, 2015-11-30 at 19:05 +0100, Marek Vasut wrote:
> > On Monday, November 30, 2015 at 06:47:45 PM, Alexey Brodkin wrote:
> > > From: Alexey Brodkin
> > >
> > > +config USB_EHCI_GENERIC
> > > + bool "Support for generic EHCI USB controller"
> > > + depends on OF_CONTROL
> > > + default n
> > > + ---help---
> > > + Enables support for generic EHCI controller.
> >
> > This should depend on EHCI_HCD somehow, no (since it's using
> > ehci_deregister and friends) ?
>
> This symbol is in "if USB_EHCI_HCD" so if USB_EHCI_HCD is not enabled
> EHCI_GENERIC won't be visible and hence USB_EHCI_HCD in defconfig.
>
> Otherwise we'll need to add USB_EHCI_HCD dependency for other EHCI drivers
> such as USB_EHCI_MARVELL, USB_EHCI_MX6 and USB_EHCI_UNIPHIER.
> Do we want to do it? :)
>
> Please check drivers/usb/host/Kconfig.
The order there seems correct. But how is it possible that your driver
triggered the build error on the ph1_sld8,ph1_sld3,ph1_ld4 boards ? I
suspect because it was enabled by default, but didn't "select" the
EHCI_HCD ?
> > [...]
> >
> > > +static const struct udevice_id ehci_usb_ids[] = {
> > > + { .compatible = "generic-ehci" },
> > > + { }
> > > +};
> > > +
> > > +U_BOOT_DRIVER(usb_ehci) = {
> >
> > The driver name should be ehci_generic, not usb_ehci, otherwise this will
> > collide with other drivers who do the same mistake.
>
> Ok but then some other drivers should be fixed as well, right?
Yes.
> See:
> --->8
> git grep U_BOOT_DRIVER drivers/usb/host/
> drivers/usb/host/dwc2.c:U_BOOT_DRIVER(usb_dwc2) = {
> drivers/usb/host/ehci-exynos.c:U_BOOT_DRIVER(usb_ehci) = {
CCing Lukasz
> drivers/usb/host/ehci-generic.c:U_BOOT_DRIVER(usb_ehci) = {
> drivers/usb/host/ehci-marvell.c:U_BOOT_DRIVER(ehci_mvebu) = {
> drivers/usb/host/ehci-pci.c:U_BOOT_DRIVER(ehci_pci) = {
> drivers/usb/host/ehci-sunxi.c:U_BOOT_DRIVER(usb_ehci) = {
This was fixed by a patch I posted just a while ago.
> drivers/usb/host/ehci-tegra.c:U_BOOT_DRIVER(usb_ehci) = {
> drivers/usb/host/ohci-sunxi.c:U_BOOT_DRIVER(usb_ohci) = {
CCing Hans.
> drivers/usb/host/usb-sandbox.c:U_BOOT_DRIVER(usb_sandbox) = {
> drivers/usb/host/usb-uclass.c:U_BOOT_DRIVER(usb_dev_generic_drv) = {
> drivers/usb/host/xhci-exynos5.c:U_BOOT_DRIVER(usb_xhci) = {
> --->8
>
> I believe it all works because we don't enable 2 drivers at a time
> [usually] :)
Correct. I trapped this on sunxi just today. Propagation of this error
must be stopped.
> And in that light I don't see a point in having different names here.
> Or you think there's a chance to have more than one USB controller enabled
> simultaneously [and if it is possible at all with current implementation]?
I can have ehci-pci and ehci-somethingelse enabled, so yes, the possibility
is here and since Tom triggered it on sunxi, it already happens.
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v3] usb: add support for generic EHCI devices
Hi Marek,
On Mon, 2015-11-30 at 19:05 +0100, Marek Vasut wrote:
> On Monday, November 30, 2015 at 06:47:45 PM, Alexey Brodkin wrote:
> > From: Alexey Brodkin
> > +config USB_EHCI_GENERIC
> > + bool "Support for generic EHCI USB controller"
> > + depends on OF_CONTROL
> > + default n
> > + ---help---
> > + Enables support for generic EHCI controller.
>
> This should depend on EHCI_HCD somehow, no (since it's using ehci_deregister
> and
> friends) ?
This symbol is in "if USB_EHCI_HCD" so if USB_EHCI_HCD is not enabled
EHCI_GENERIC won't be visible and hence USB_EHCI_HCD in defconfig.
Otherwise we'll need to add USB_EHCI_HCD dependency for other EHCI drivers
such as USB_EHCI_MARVELL, USB_EHCI_MX6 and USB_EHCI_UNIPHIER.
Do we want to do it? :)
Please check drivers/usb/host/Kconfig.
> [...]
>
> > +static const struct udevice_id ehci_usb_ids[] = {
> > + { .compatible = "generic-ehci" },
> > + { }
> > +};
> > +
> > +U_BOOT_DRIVER(usb_ehci) = {
>
> The driver name should be ehci_generic, not usb_ehci, otherwise this will
> collide with other drivers who do the same mistake.
Ok but then some other drivers should be fixed as well, right?
See:
--->8
git grep U_BOOT_DRIVER drivers/usb/host/
drivers/usb/host/dwc2.c:U_BOOT_DRIVER(usb_dwc2) = {
drivers/usb/host/ehci-exynos.c:U_BOOT_DRIVER(usb_ehci) = {
drivers/usb/host/ehci-generic.c:U_BOOT_DRIVER(usb_ehci) = {
drivers/usb/host/ehci-marvell.c:U_BOOT_DRIVER(ehci_mvebu) = {
drivers/usb/host/ehci-pci.c:U_BOOT_DRIVER(ehci_pci) = {
drivers/usb/host/ehci-sunxi.c:U_BOOT_DRIVER(usb_ehci) = {
drivers/usb/host/ehci-tegra.c:U_BOOT_DRIVER(usb_ehci) = {
drivers/usb/host/ohci-sunxi.c:U_BOOT_DRIVER(usb_ohci) = {
drivers/usb/host/usb-sandbox.c:U_BOOT_DRIVER(usb_sandbox) = {
drivers/usb/host/usb-uclass.c:U_BOOT_DRIVER(usb_dev_generic_drv) = {
drivers/usb/host/xhci-exynos5.c:U_BOOT_DRIVER(usb_xhci) = {
--->8
I believe it all works because we don't enable 2 drivers at a time
[usually] :)
And in that light I don't see a point in having different names here.
Or you think there's a chance to have more than one USB controller enabled
simultaneously [and if it is possible at all with current implementation]?
-Alexey
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Re: [U-Boot] [PATCH v2] axs10x: add support of generic ECHI USB 2.0 controller
On Monday, November 30, 2015 at 06:53:25 PM, Alexey Brodkin wrote: > This commit adds support of USB 2.0 storage media on AXS10x boards. > > Signed-off-by: Alexey Brodkin > Cc: Marek Vasut > Cc: Simon Glass > --- Ad subject -- It's EHCI, not ECHI ;-) [...] > diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig > index 52d5e2f..a541d9d 100644 > --- a/configs/axs101_defconfig > +++ b/configs/axs101_defconfig > @@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x" > CONFIG_SYS_PROMPT="AXS# " > # CONFIG_CMD_IMLS is not set > # CONFIG_CMD_FLASH is not set > +CONFIG_CMD_USB=y > # CONFIG_CMD_SETEXPR is not set > CONFIG_CMD_DHCP=y > CONFIG_CMD_PING=y > @@ -19,4 +20,9 @@ CONFIG_CLK=y > CONFIG_DM_ETH=y > CONFIG_ETH_DESIGNWARE=y > CONFIG_SYS_NS16550=y > +CONFIG_USB=y > +CONFIG_DM_USB=y > +CONFIG_USB_EHCI_HCD=y You don't need EHCI_HCD in defconfig in case EHCI_GENERIC depends on it I think. > +CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_STORAGE=y > CONFIG_USE_PRIVATE_LIBGCC=y > diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig > index a7f3c38..3c65c83 100644 > --- a/configs/axs103_defconfig > +++ b/configs/axs103_defconfig > @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x" > CONFIG_SYS_PROMPT="AXS# " > # CONFIG_CMD_IMLS is not set > # CONFIG_CMD_FLASH is not set > +CONFIG_CMD_USB=y > # CONFIG_CMD_SETEXPR is not set > CONFIG_CMD_DHCP=y > CONFIG_CMD_PING=y > @@ -18,4 +19,9 @@ CONFIG_CLK=y > CONFIG_DM_ETH=y > CONFIG_ETH_DESIGNWARE=y > CONFIG_SYS_NS16550=y > +CONFIG_USB=y > +CONFIG_DM_USB=y > +CONFIG_USB_EHCI_HCD=y DTTO > +CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_STORAGE=y > CONFIG_USE_PRIVATE_LIBGCC=y ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] usb: add support for generic EHCI devices
On Monday, November 30, 2015 at 06:47:45 PM, Alexey Brodkin wrote:
> From: Alexey Brodkin
>
> This driver is meant to be used with any EHCI-compatible host
> controller in case if there's no need for platform-specific
> glue such as setup of controller or PHY's power mode via
> GPIOs etc.
>
> Signed-off-by: Alexey Brodkin
> Reviewed-by: Simon Glass
> Reviewed-by: Marek Vasut
> Cc: Stephen Warren
> ---
>
> Changes compared to v2:
> * Driver is disabled by default now
> * Use uintptr_t instead of uint32_t for "struct ehci_hcor"
>address calculation
>
> Changes compared to v1:
> * Updated commit message with removal of Synopsys board mention
> * Cleaned-up ehci_usb_remove()
>
> drivers/usb/host/Kconfig| 7 ++
> drivers/usb/host/Makefile | 1 +
> drivers/usb/host/ehci-generic.c | 51
> + 3 files changed, 59
> insertions(+)
> create mode 100644 drivers/usb/host/ehci-generic.c
>
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index 2a2bffe..6bb9caa 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -73,4 +73,11 @@ config USB_EHCI_UNIPHIER
> ---help---
> Enables support for the on-chip EHCI controller on UniPhier SoCs.
>
> +config USB_EHCI_GENERIC
> + bool "Support for generic EHCI USB controller"
> + depends on OF_CONTROL
> + default n
> + ---help---
> + Enables support for generic EHCI controller.
This should depend on EHCI_HCD somehow, no (since it's using ehci_deregister
and
friends) ?
[...]
> +static const struct udevice_id ehci_usb_ids[] = {
> + { .compatible = "generic-ehci" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(usb_ehci) = {
The driver name should be ehci_generic, not usb_ehci, otherwise this will
collide with other drivers who do the same mistake.
> + .name = "ehci_generic",
> + .id = UCLASS_USB,
> + .of_match = ehci_usb_ids,
> + .probe = ehci_usb_probe,
> + .remove = ehci_usb_remove,
> + .ops= &ehci_usb_ops,
> + .priv_auto_alloc_size = sizeof(struct generic_ehci),
> + .flags = DM_FLAG_ALLOC_PRIV_DMA,
> +};
> +
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v4] arm: Add sata support on Layerscape ARMv8 board
Hi Yuan
On 30/11/15 02:44 AM, yuantian.t...@freescale.com wrote:
From: Tang Yuantian
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: Tang Yuantian
---
v4:
- rebase to lastest git tree
- add another ARMv8 platform which is ls1043aqds
v3:
- rename ls2085a to ls2080a
- rebase to the latest git tree
- replace the magic number with micro variable
v2:
- rebase to the latest git tree
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 43 +++
arch/arm/include/asm/arch-fsl-layerscape/config.h | 18 ++
arch/arm/include/asm/arch-fsl-layerscape/soc.h| 31
include/configs/ls1043aqds.h | 17 +
4 files changed, 109 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8896b70..574ffc4 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -6,6 +6,8 @@
#include
#include
+#include
+#include
#include
#include
#include
@@ -120,7 +122,44 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
}
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+ struct ccsr_ahci __iomem *ccsr_ahci;
+
+ ccsr_ahci = (void *)CONFIG_SYS_SATA2;
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ccsr_ahci = (void *)CONFIG_SYS_SATA1;
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ahci_init((void __iomem *)CONFIG_SYS_SATA1);
+ scsi_scan(0);
+
+ return 0;
+}
+#endif
+
#elif defined(CONFIG_LS1043A)
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int sata_init(void)
+{
+ struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
+
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ahci_init((void __iomem *)CONFIG_SYS_SATA);
+ scsi_scan(0);
+
+ return 0;
+}
+#endif
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -141,6 +180,10 @@ void fsl_lsch2_early_init_f(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
+#ifdef CONFIG_SCSI_AHCI_PLAT
+ sata_init();
+#endif
+
return 0;
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b5a2d28..be3acc3 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -54,6 +54,24 @@
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+/* SATA */
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + 0x0220)
+#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + 0x0221)
Why do we have CONFIG_SYS_SATA1 and CONFIG_SYS_SATA2
here and then CONFIG_SYS_SATA in another file (see later
below)? CONFIG_SYS_SATA1 and CONFIG_SYS_SATA seem to
have the same macro value : (CONFIG_SYS_IMMR + 0x0220)
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID1
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x0600
#define GICR_BASE 0x0610
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 504c1f9..83186d6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -51,6 +51,37 @@ struct cpu_type {
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
+/* ahci port register default value */
+#define AHCI_PORT_PHY_1_CFG0xa003fffe
+#define AHCI_PORT_PHY_2_CFG0x28184d1f
+#define AHCI_PORT_PHY_3_CFG0x0e081509
+#define AHCI_PORT_TRANS_CFG0x0825
+
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+ u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
+ u32 pcfg; /* port config */
+ u32 ppcfg; /* port phy1 config */
+ u32 pp2c; /* port phy2 config */
+ u32 pp3c; /* port phy3 config */
+ u32 pp4c; /* port p
[U-Boot] [PATCH v2] axs10x: add support of generic ECHI USB 2.0 controller
This commit adds support of USB 2.0 storage media on AXS10x boards.
Signed-off-by: Alexey Brodkin
Cc: Marek Vasut
Cc: Simon Glass
---
Changes compared to v1:
* Explicitly enable CONFIG_USB_EHCI_GENERIC
arch/arc/dts/axs10x.dts | 6 ++
configs/axs101_defconfig | 6 ++
configs/axs103_defconfig | 6 ++
3 files changed, 18 insertions(+)
diff --git a/arch/arc/dts/axs10x.dts b/arch/arc/dts/axs10x.dts
index 8fe1837..80e6d6b 100644
--- a/arch/arc/dts/axs10x.dts
+++ b/arch/arc/dts/axs10x.dts
@@ -42,4 +42,10 @@
clock-names = "stmmaceth";
max-speed = <100>;
};
+
+ ehci@0xe004 {
+ compatible = "generic-ehci";
+ reg = < 0xe004 0x100 >;
+ interrupts = < 8 >;
+ };
};
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index 52d5e2f..a541d9d 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -8,6 +8,7 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x"
CONFIG_SYS_PROMPT="AXS# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
@@ -19,4 +20,9 @@ CONFIG_CLK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index a7f3c38..3c65c83 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="axs10x"
CONFIG_SYS_PROMPT="AXS# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
@@ -18,4 +19,9 @@ CONFIG_CLK=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
CONFIG_USE_PRIVATE_LIBGCC=y
--
2.5.0
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Re: [U-Boot] [PATCH v3] usb: add support for generic EHCI devices
Hi Marek, On Mon, 2015-11-30 at 20:47 +0300, Alexey Brodkin wrote: > From: Alexey Brodkin > > This driver is meant to be used with any EHCI-compatible host > controller in case if there's no need for platform-specific > glue such as setup of controller or PHY's power mode via > GPIOs etc. > > Signed-off-by: Alexey Brodkin > Reviewed-by: Simon Glass > Reviewed-by: Marek Vasut > Cc: Stephen Warren > --- > > Changes compared to v2: > * Driver is disabled by default now > * Use uintptr_t instead of uint32_t for "struct ehci_hcor" >address calculation > > Changes compared to v1: > * Updated commit message with removal of Synopsys board mention > * Cleaned-up ehci_usb_remove() git doesn't Cc people from "Reviewed-by" tags, so adding you and Simon here. Sorry for that noise. -Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] usb: add support for generic EHCI devices
From: Alexey Brodkin
This driver is meant to be used with any EHCI-compatible host
controller in case if there's no need for platform-specific
glue such as setup of controller or PHY's power mode via
GPIOs etc.
Signed-off-by: Alexey Brodkin
Reviewed-by: Simon Glass
Reviewed-by: Marek Vasut
Cc: Stephen Warren
---
Changes compared to v2:
* Driver is disabled by default now
* Use uintptr_t instead of uint32_t for "struct ehci_hcor"
address calculation
Changes compared to v1:
* Updated commit message with removal of Synopsys board mention
* Cleaned-up ehci_usb_remove()
drivers/usb/host/Kconfig| 7 ++
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ehci-generic.c | 51 +
3 files changed, 59 insertions(+)
create mode 100644 drivers/usb/host/ehci-generic.c
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 2a2bffe..6bb9caa 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -73,4 +73,11 @@ config USB_EHCI_UNIPHIER
---help---
Enables support for the on-chip EHCI controller on UniPhier SoCs.
+config USB_EHCI_GENERIC
+ bool "Support for generic EHCI USB controller"
+ depends on OF_CONTROL
+ default n
+ ---help---
+ Enables support for generic EHCI controller.
+
endif
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index f70f38c..b9b4471 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -32,6 +32,7 @@ else
obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
endif
obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o
+obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o
obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
diff --git a/drivers/usb/host/ehci-generic.c b/drivers/usb/host/ehci-generic.c
new file mode 100644
index 000..22e1ad0
--- /dev/null
+++ b/drivers/usb/host/ehci-generic.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2015 Alexey Brodkin
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include "ehci.h"
+
+/*
+ * Even though here we don't explicitly use "struct ehci_ctrl"
+ * ehci_register() expects it to be the first thing that resides in
+ * device's private data.
+ */
+struct generic_ehci {
+ struct ehci_ctrl ctrl;
+};
+
+static int ehci_usb_probe(struct udevice *dev)
+{
+ struct ehci_hccr *hccr = (struct ehci_hccr *)dev_get_addr(dev);
+ struct ehci_hcor *hcor;
+
+ hcor = (struct ehci_hcor *)((uintptr_t)hccr +
+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
+}
+
+static int ehci_usb_remove(struct udevice *dev)
+{
+ return ehci_deregister(dev);
+}
+
+static const struct udevice_id ehci_usb_ids[] = {
+ { .compatible = "generic-ehci" },
+ { }
+};
+
+U_BOOT_DRIVER(usb_ehci) = {
+ .name = "ehci_generic",
+ .id = UCLASS_USB,
+ .of_match = ehci_usb_ids,
+ .probe = ehci_usb_probe,
+ .remove = ehci_usb_remove,
+ .ops= &ehci_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct generic_ehci),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+
--
2.5.0
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