[U-Boot] [PATCH] Improve Power Management in SMC911X driver.

2011-11-15 Thread Bertrand Cachet
From datasheet, when READY bit is set inside PM_CTRL register, it means that
device is already in *normal* (D0) mode = it doesn't need to be wake-up.

With this patch, we only wake-up (writing on TEST_BYTE register) if PM_MODE
bits of PM_CTRL register is in sleep (D1/D2) mode.

Improve code styling by grouping two narrow comments.

Signed-off-by: Bertrand Cachet bertrand.cac...@heig-vd.ch
---
 drivers/net/smc911x.h |7 +--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 8ce08a9..7f4156e 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -471,8 +471,11 @@ static void smc911x_reset(struct eth_device *dev)
 {
int timeout;
 
-   /* Take out of PM setting first */
-   if (smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) {
+   /*
+*  Take out of PM setting first
+*  Device is already wake up if PMT_CTRL_READY bit is set
+*/
+   if ((smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) == 0) {
/* Write to the bytetest will take out of powerdown */
smc911x_reg_write(dev, BYTE_TEST, 0x0);
 
-- 
1.7.5.4

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[U-Boot] [PATCH v3] Improve Power Management in SMC911X driver.

2011-11-15 Thread Bertrand Cachet
From datasheet, when READY bit is set inside PM_CTRL register, it means that
device is already in *normal* (D0) mode = it doesn't need to be wake-up.

With this patch, we only wake-up (writing on TEST_BYTE register) if PM_MODE
bits of PM_CTRL register is in sleep (D1/D2) mode.

Signed-off-by: Bertrand Cachet bertrand.cac...@heig-vd.ch
---
 v2: Improve code styling by grouping two narrow comments.
 v3: Place versions information under scissors line.

 drivers/net/smc911x.h |7 +--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 8ce08a9..00e5b2e 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -471,8 +471,11 @@ static void smc911x_reset(struct eth_device *dev)
 {
int timeout;
 
-   /* Take out of PM setting first */
-   if (smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) {
+ /*
+  *  Take out of PM setting first
+  *  Device is already wake up if PMT_CTRL_READY bit is set
+  */
+   if ((smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) == 0) {
/* Write to the bytetest will take out of powerdown */
smc911x_reg_write(dev, BYTE_TEST, 0x0);
 
-- 
1.7.5.4

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[U-Boot] [PATCH v4] Improve Power Management in SMC911X driver.

2011-11-15 Thread Bertrand Cachet
From datasheet, when READY bit is set inside PM_CTRL register, it means that
device is already in *normal* (D0) mode = it doesn't need to be wake-up.

With this patch, we only wake-up (writing on TEST_BYTE register) if PM_MODE
bits of PM_CTRL register is in sleep (D1/D2) mode.

Signed-off-by: Bertrand Cachet bertrand.cac...@heig-vd.ch
---
 v2: Improve code styling by grouping two narrow comments.
 v3: Place versions information under scissors line.
 v4: Use tabs instead of spaces (vimrc problem)

 drivers/net/smc911x.h |7 +--
 1 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 8ce08a9..a290073 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -471,8 +471,11 @@ static void smc911x_reset(struct eth_device *dev)
 {
int timeout;
 
-   /* Take out of PM setting first */
-   if (smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) {
+   /*
+*  Take out of PM setting first
+*  Device is already wake up if PMT_CTRL_READY bit is set
+*/
+   if ((smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) == 0) {
/* Write to the bytetest will take out of powerdown */
smc911x_reg_write(dev, BYTE_TEST, 0x0);
 
-- 
1.7.5.4

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[U-Boot] Patch: Power Mangement with smc911x driver

2011-11-14 Thread bertrand . cachet

Hello,

In a previous email I sent a patch without following u-boot gitflow.
So I send my patch again following informations provided by Mike Frysinger.

I hope that I have done everything correctly now.

Sincerely

Bertrand Cachet
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[U-Boot] [PATCH] Improve Power Management in SMC911X driver.

2011-11-14 Thread bertrand . cachet
From: Bertrand Cachet bertrand.cac...@heig-vd.ch

From datasheet, when READY bit is set inside PM_CTRL register, it means that
device is already in *normal* (D0) mode = it doesn't need to be wake-up.

With this patch, we only wake-up (writing on TEST_BYTE register) if PM_MODE
bits of PM_CTRL register is in D1/D2 mode.

Signed-off-by: Bertrand Cachet bertrand.cac...@heig-vd.ch
---
 drivers/net/smc911x.h |6 --
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 8ce08a9..258b9b6 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -471,8 +471,10 @@ static void smc911x_reset(struct eth_device *dev)
 {
int timeout;
 
-   /* Take out of PM setting first */
-   if (smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) {
+   /*  Take out of PM setting first */
+  /*  If PMT_CTRL_READY bit is set to 1b = power management is 
+  already ready */
+   if ((smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) == 0) {
/* Write to the bytetest will take out of powerdown */
smc911x_reg_write(dev, BYTE_TEST, 0x0);
 
-- 
1.7.5.4

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[U-Boot] [PATCH] Improve Power Management in SMC911X driver.

2011-11-14 Thread Bertrand Cachet
From datasheet, when READY bit is set inside PM_CTRL register, it means that
device is already in *normal* (D0) mode = it doesn't need to be wake-up.

With this patch, we only wake-up (writing on TEST_BYTE register) if PM_MODE
bits of PM_CTRL register is in D1/D2 mode.

Signed-off-by: Bertrand Cachet bertrand.cac...@heig-vd.ch
---
 drivers/net/smc911x.h |6 --
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 8ce08a9..258b9b6 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -471,8 +471,10 @@ static void smc911x_reset(struct eth_device *dev)
 {
int timeout;
 
-   /* Take out of PM setting first */
-   if (smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) {
+   /*  Take out of PM setting first */
+  /*  If PMT_CTRL_READY bit is set to 1b = power management is 
+  already ready */
+   if ((smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) == 0) {
/* Write to the bytetest will take out of powerdown */
smc911x_reg_write(dev, BYTE_TEST, 0x0);
 
-- 
1.7.5.4

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[U-Boot] [PATCH] Improve Power Management in SMC911X driver.

2011-11-14 Thread Bertrand Cachet
From datasheet, when READY bit is set inside PM_CTRL register, it means that
device is already in *normal* (D0) mode = it doesn't need to be wake-up.

With this patch, we only wake-up (writing on TEST_BYTE register) if PM_MODE
bits of PM_CTRL register is in D1/D2 mode.

Signed-off-by: Bertrand Cachet bertrand.cac...@heig-vd.ch
---
 drivers/net/smc911x.h |8 ++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 8ce08a9..61f7669 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -471,8 +471,12 @@ static void smc911x_reset(struct eth_device *dev)
 {
int timeout;
 
-   /* Take out of PM setting first */
-   if (smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) {
+   /*  Take out of PM setting first */
+   /*
+*  If PMT_CTRL_READY bit is set to 1b = power management is 
+*  already ready 
+*/
+   if ((smc911x_reg_read(dev, PMT_CTRL)  PMT_CTRL_READY) == 0) {
/* Write to the bytetest will take out of powerdown */
smc911x_reg_write(dev, BYTE_TEST, 0x0);
 
-- 
1.7.5.4

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