[PATCH v4 4/4] rockchip: Add support to generate LZMA compressed U-boot binary
Add support for generating a LZMA-compressed U-boot binary with the
help of binman, if CONFIG_SPL_LZMA is selected.
Signed-off-by: Manoj Sai
Reviewed-by: Simon Glass
Reviewed-by: Kever Yang
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- New patch for v2
arch/arm/dts/rockchip-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index 8f248f941f..c8c928c7e5 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -58,6 +58,8 @@
#endif
#if defined(CONFIG_SPL_GZIP)
compression = "gzip";
+#elif defined(CONFIG_SPL_LZMA)
+ compression = "lzma";
#else
compression = "none";
#endif
@@ -66,6 +68,8 @@
u-boot-nodtb {
#if defined(CONFIG_SPL_GZIP)
compress = "gzip";
+#elif defined(CONFIG_SPL_LZMA)
+ compress = "lzma";
#endif
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
--
2.25.1
[PATCH v4 3/4] rockchip: Add support to generate GZIP compressed U-boot binary
Add support for generating a GZIP-compressed U-boot binary with the
help of binman, if CONFIG_SPL_GZIP is selected.
Signed-off-by: Manoj Sai
Reviewed-by: Simon Glass
Reviewed-by: Kever Yang
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- New patch for v2
arch/arm/dts/rockchip-u-boot.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index be2658e8ef..8f248f941f 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -56,10 +56,17 @@
#else
arch = "arm";
#endif
+#if defined(CONFIG_SPL_GZIP)
+ compression = "gzip";
+#else
compression = "none";
+#endif
load = ;
entry = ;
u-boot-nodtb {
+#if defined(CONFIG_SPL_GZIP)
+ compress = "gzip";
+#endif
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
--
2.25.1
[PATCH v4 2/4] spl: fit: support for booting a LZMA-compressed U-boot binary
If LZMA Compression support is enabled, LZMA compressed U-Boot
binary will be placed at a specified RAM location which is
defined at CONFIG_SYS_LOAD_ADDR and will be assigned as the
source address.
image_decomp() function, will decompress the LZMA compressed
U-Boot binary which is placed at source address(CONFIG_SYS_LOAD_ADDR)
to the default CONFIG_SYS_TEXT_BASE location.
spl_load_fit_image function will load the decompressed U-Boot
binary, which is placed at the CONFIG_SYS_TEXT_BASE location.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
Reviewed-by: Simon Glass
Reviewed-by: Kever Yang
---
Changes in v4:
- None
Changes in v3:
- added IS_ENABLED(CONFIG_SPL_LZMA) to spl_decompression_enabled() function.
- Removed extra parentheses.
Changes in v2:
- New patch for v2
common/spl/spl_fit.c | 13 -
include/spl.h| 2 +-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index eb97259f57..75895ef15c 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -281,7 +281,8 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return 0;
}
- if (spl_decompression_enabled() && image_comp == IH_COMP_GZIP)
+ if (spl_decompression_enabled() &&
+ (image_comp == IH_COMP_GZIP || image_comp == IH_COMP_LZMA))
src_ptr = map_sysmem(ALIGN(CONFIG_SYS_LOAD_ADDR,
ARCH_DMA_MINALIGN), len);
else
src_ptr = map_sysmem(ALIGN(load_addr,
ARCH_DMA_MINALIGN), len);
@@ -329,6 +330,16 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return -EIO;
}
length = size;
+ } else if (IS_ENABLED(CONFIG_SPL_LZMA) && image_comp == IH_COMP_LZMA) {
+ size = CONFIG_SYS_BOOTM_LEN;
+ ulong loadEnd;
+
+ if (image_decomp(IH_COMP_LZMA, CONFIG_SYS_LOAD_ADDR, 0, 0,
+load_ptr, src, length, size, &loadEnd)) {
+ puts("Uncompressing error\n");
+ return -EIO;
+ }
+ length = loadEnd - CONFIG_SYS_LOAD_ADDR;
} else {
memcpy(load_ptr, src, length);
}
diff --git a/include/spl.h b/include/spl.h
index 3a7e448cc7..9de93a34cd 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -905,6 +905,6 @@ void spl_save_restore_data(void);
*/
static inline bool spl_decompression_enabled(void)
{
- return IS_ENABLED(CONFIG_SPL_GZIP);
+ return IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA);
}
#endif
--
2.25.1
[PATCH v4 1/4] spl: fit: support for booting a GZIP-compressed U-boot binary
If GZIP Compression support is enabled, GZIP compressed U-Boot binary
will be at a specified RAM location which is defined at
CONFIG_SYS_LOAD_ADDR and will be assign it as the source address.
gunzip function in spl_load_fit_image ,will decompress the GZIP
compressed U-Boot binary which is placed at
source address(CONFIG_SYS_LOAD_ADDR) to the default
CONFIG_SYS_TEXT_BASE location.
spl_load_fit_image function will load the decompressed U-Boot
binary, which is placed at the CONFIG_SYS_TEXT_BASE location.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
Reviewed-by: Kever Yang
Reviewed-by: Simon Glass
---
Changes in v4:
- None
Changes in v3:
- Replaced spl_decompression_enabled() function instead of
checking IS_ENABLED(CONFIG_SPL_GZIP).
- Removed checking IS_ENABLED(CONFIG_SPL_LZMA) in spl_decompression_enabled()
function.
Changes in v2:
- New patch for v2
common/spl/spl_fit.c | 9 ++---
include/spl.h| 10 ++
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 730639f756..eb97259f57 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -239,14 +239,14 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
bool external_data = false;
if (IS_ENABLED(CONFIG_SPL_FPGA) ||
- (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP))) {
+ (IS_ENABLED(CONFIG_SPL_OS_BOOT) && spl_decompression_enabled())) {
if (fit_image_get_type(fit, node, &type))
puts("Cannot get image type.\n");
else
debug("%s ", genimg_get_type_name(type));
}
- if (IS_ENABLED(CONFIG_SPL_GZIP)) {
+ if (spl_decompression_enabled()) {
fit_image_get_comp(fit, node, &image_comp);
debug("%s ", genimg_get_comp_name(image_comp));
}
@@ -281,7 +281,10 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return 0;
}
- src_ptr = map_sysmem(ALIGN(load_addr, ARCH_DMA_MINALIGN), len);
+ if (spl_decompression_enabled() && image_comp == IH_COMP_GZIP)
+ src_ptr = map_sysmem(ALIGN(CONFIG_SYS_LOAD_ADDR,
ARCH_DMA_MINALIGN), len);
+ else
+ src_ptr = map_sysmem(ALIGN(load_addr,
ARCH_DMA_MINALIGN), len);
length = len;
overhead = get_aligned_image_overhead(info, offset);
diff --git a/include/spl.h b/include/spl.h
index 93e906431e..3a7e448cc7 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -897,4 +897,14 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset,
size_t size);
void board_boot_order(u32 *spl_boot_list);
void spl_save_restore_data(void);
+
+/*
+ * spl_decompression_enabled() - check decompression support is enabled for
SPL build
+ *
+ * Returns true if decompression support is enabled, else False
+ */
+static inline bool spl_decompression_enabled(void)
+{
+ return IS_ENABLED(CONFIG_SPL_GZIP);
+}
#endif
--
2.25.1
[PATCH v4 0/4] support for booting the compressed U-boot binary on Rockchip based ARM64 SOC's
This patchset adds the support on Rockchip based ARM64 SOC's that compress the U-BOOT proper along with dtb and ATF in FIT image format.Second stage bootloader(SPL) loads the compressed binaries, uncompress them and handover control to the next stage. Changes for V3 :- 1. Replaced spl_decompression_enabled() function instead of checking IS_ENABLED(CONFIG_SPL_GZIP) and IS_ENABLED(CONFIG_SPL_LZMA) in spl_fit.c. 2. Removed extra wrapping parentheses in spl_decompression_enabled(). Changes for V4 :- 1. As per the suggestion from Mr.Jonas Karlman (jo...@kwiboo.se) from PATCH v2 and v3 ,check boot time with the following RFC patch with CONFIG_SPL_FIT_SIGNATURE enabled that might impact boot time and As seen there is an improvement in boot time with both compress enabled and disabled , I have added the logs of it below. [RFC] rockchip: spl: Enable caches to speed up checksum validation https://patchwork.ozlabs.org/project/uboot/patch/20230702110055.3686457-1-jo...@kwiboo.se/ Size Comparision between compressed and uncompressed binaries :- size of uncompressed binary:- 9.0M (94,21,824 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 9421824 Sep 10 22:22 u-boot-rockchip.bin size of GZIP compressed binary :- 8.6M (89,85,088 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 8985088 Jul 25 07:42 u-boot-rockchip.bin size of LZMA compressed binary :- 8.6 M (90,06,592 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 9006592 Jul 25 07:47 u-boot-rockchip.bin Test results of Booting time using bootstage command in Uboot command prompt on roc-rk3399-pc board :- 1) Uncompressed U-BOOT : Total boot time = 12.063971 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 1,833,884 1,833,884 board_init_f 2,959,528 1,125,644 board_init_r 5,224,521 2,264,993 eth_common_init 5,523,428298,907 eth_initialize 5,523,606178 main_loop 5,523,764158 usb_start 12,063,971 6,540,207 cli_loop 2) GZIP Compressed U-BOOT : Total time = 12.824968 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 2,594,709 2,594,709 board_init_f 3,719,969 1,125,260 board_init_r 5,985,450 2,265,481 eth_common_init 6,284,371298,921 eth_initialize 6,284,549178 main_loop 6,284,708159 usb_start 12,824,968 6,540,260 cli_loop 3) LZMA Compressed U-BOOT : Total time = 17.025004 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 6,852,254 6,852,254 board_init_f 7,940,143 1,087,889 board_init_r 10,190,458 2,250,315 eth_common_init 10,487,254296,796 eth_initialize 10,487,432178 main_loop 10,487,590158 usb_start 17,025,004 6,537,414 cli_loop Test results of booting time using RFC patch from Mr.Jonas Karlman(jo...@kwiboo.se) with CONFIG_SPL_FIT_SIGNATURE enabled on roc-rk3399-pc board :- 1. Uncompressed U-BOOT : Total boot time = 10.728 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 477,024477,024 board_init_f 1,623,670 1,146,646 board_init_r 3,889,493 2,265,823 eth_common_init 4,188,402298,909 eth_initialize 4,188,579177 main_loop 4,188,738159 usb_start 10,728,000 6,539,262 cli_loop 2. GZIP Compressed U-BOOT : Total time = 10.708 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 457,663457,663 board_init_f 1,604,222 1,146,559 board_init_r 3,869,505 2,265,283 eth_common_init 4,168,410298,905 eth_initialize 4,168,587177 main_loop 4,168,745158 usb_start 10,707,997 6,539,252 cli_loop 3. LZMA Compressed U-BOOT : Total time = 10.86 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 612,427612,427 board_init_f 1,756,176 1,143,749 board_init_r 4,021,522 2,265,346 eth_common_init 4,320,433298,911 eth_initialize 4,320,610177 main_loop 4,320,768158 usb_start 10,860,001 6,539,233 cli_loop As I can seen there is an improvement in boot time with Enable caches in SPL to speed up FIT checksum validation, with the following RFC patch from Mr.Jonas. [RFC] rockchip: spl: Enable caches to speed up checksum validation https://patchwork.ozlabs.org/project/uboot/patch/20230702110055.3686457-1-jo...@kwiboo.se/ Manoj Sai (4): spl: fit: support for booting a GZIP-compressed U-boot binary spl: fit: support for boot
[PATCH v3 4/4] rockchip: Add support to generate LZMA compressed U-boot binary
Add support for generating a LZMA-compressed U-boot binary with the
help of binman, if CONFIG_SPL_LZMA is selected.
Signed-off-by: Manoj Sai
Reviewed-by: Simon Glass
Reviewed-by: Kever Yang
---
Changes in v3:
- None
Changes in v2:
- New patch for v2
arch/arm/dts/rockchip-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index 8f248f941f..c8c928c7e5 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -58,6 +58,8 @@
#endif
#if defined(CONFIG_SPL_GZIP)
compression = "gzip";
+#elif defined(CONFIG_SPL_LZMA)
+ compression = "lzma";
#else
compression = "none";
#endif
@@ -66,6 +68,8 @@
u-boot-nodtb {
#if defined(CONFIG_SPL_GZIP)
compress = "gzip";
+#elif defined(CONFIG_SPL_LZMA)
+ compress = "lzma";
#endif
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
--
2.25.1
[PATCH v3 3/4] rockchip: Add support to generate GZIP compressed U-boot binary
Add support for generating a GZIP-compressed U-boot binary with the
help of binman, if CONFIG_SPL_GZIP is selected.
Signed-off-by: Manoj Sai
Reviewed-by: Simon Glass
Reviewed-by: Kever Yang
---
Changes in v3:
- None
Changes in v2:
- New patch for v2
arch/arm/dts/rockchip-u-boot.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index be2658e8ef..8f248f941f 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -56,10 +56,17 @@
#else
arch = "arm";
#endif
+#if defined(CONFIG_SPL_GZIP)
+ compression = "gzip";
+#else
compression = "none";
+#endif
load = ;
entry = ;
u-boot-nodtb {
+#if defined(CONFIG_SPL_GZIP)
+ compress = "gzip";
+#endif
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
--
2.25.1
[PATCH v3 2/4] spl: fit: support for booting a LZMA-compressed U-boot binary
If LZMA Compression support is enabled, LZMA compressed U-Boot
binary will be placed at a specified RAM location which is
defined at CONFIG_SYS_LOAD_ADDR and will be assigned as the
source address.
image_decomp() function, will decompress the LZMA compressed
U-Boot binary which is placed at source address(CONFIG_SYS_LOAD_ADDR)
to the default CONFIG_SYS_TEXT_BASE location.
spl_load_fit_image function will load the decompressed U-Boot
binary, which is placed at the CONFIG_SYS_TEXT_BASE location.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
Reviewed-by: Simon Glass
Reviewed-by: Kever Yang
---
Changes in v3:
- added IS_ENABLED(CONFIG_SPL_LZMA) to spl_decompression_enabled() function.
- Removed extra parentheses.
Changes in v2:
- New patch for v2
common/spl/spl_fit.c | 13 -
include/spl.h| 2 +-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index eb97259f57..75895ef15c 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -281,7 +281,8 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return 0;
}
- if (spl_decompression_enabled() && image_comp == IH_COMP_GZIP)
+ if (spl_decompression_enabled() &&
+ (image_comp == IH_COMP_GZIP || image_comp == IH_COMP_LZMA))
src_ptr = map_sysmem(ALIGN(CONFIG_SYS_LOAD_ADDR,
ARCH_DMA_MINALIGN), len);
else
src_ptr = map_sysmem(ALIGN(load_addr,
ARCH_DMA_MINALIGN), len);
@@ -329,6 +330,16 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return -EIO;
}
length = size;
+ } else if (IS_ENABLED(CONFIG_SPL_LZMA) && image_comp == IH_COMP_LZMA) {
+ size = CONFIG_SYS_BOOTM_LEN;
+ ulong loadEnd;
+
+ if (image_decomp(IH_COMP_LZMA, CONFIG_SYS_LOAD_ADDR, 0, 0,
+load_ptr, src, length, size, &loadEnd)) {
+ puts("Uncompressing error\n");
+ return -EIO;
+ }
+ length = loadEnd - CONFIG_SYS_LOAD_ADDR;
} else {
memcpy(load_ptr, src, length);
}
diff --git a/include/spl.h b/include/spl.h
index 3a7e448cc7..9de93a34cd 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -905,6 +905,6 @@ void spl_save_restore_data(void);
*/
static inline bool spl_decompression_enabled(void)
{
- return IS_ENABLED(CONFIG_SPL_GZIP);
+ return IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA);
}
#endif
--
2.25.1
[PATCH v3 1/4] spl: fit: support for booting a GZIP-compressed U-boot binary
If GZIP Compression support is enabled, GZIP compressed U-Boot binary
will be at a specified RAM location which is defined at
CONFIG_SYS_LOAD_ADDR and will be assign it as the source address.
gunzip function in spl_load_fit_image ,will decompress the GZIP
compressed U-Boot binary which is placed at
source address(CONFIG_SYS_LOAD_ADDR) to the default
CONFIG_SYS_TEXT_BASE location.
spl_load_fit_image function will load the decompressed U-Boot
binary, which is placed at the CONFIG_SYS_TEXT_BASE location.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
Reviewed-by: Kever Yang
Reviewed-by: Simon Glass
---
Changes in v3:
- Replaced spl_decompression_enabled() function instead of
checking IS_ENABLED(CONFIG_SPL_GZIP).
- Removed checking IS_ENABLED(CONFIG_SPL_LZMA) in spl_decompression_enabled()
function.
Changes in v2:
- New patch for v2
common/spl/spl_fit.c | 9 ++---
include/spl.h| 10 ++
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 730639f756..eb97259f57 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -239,14 +239,14 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
bool external_data = false;
if (IS_ENABLED(CONFIG_SPL_FPGA) ||
- (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP))) {
+ (IS_ENABLED(CONFIG_SPL_OS_BOOT) && spl_decompression_enabled())) {
if (fit_image_get_type(fit, node, &type))
puts("Cannot get image type.\n");
else
debug("%s ", genimg_get_type_name(type));
}
- if (IS_ENABLED(CONFIG_SPL_GZIP)) {
+ if (spl_decompression_enabled()) {
fit_image_get_comp(fit, node, &image_comp);
debug("%s ", genimg_get_comp_name(image_comp));
}
@@ -281,7 +281,10 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return 0;
}
- src_ptr = map_sysmem(ALIGN(load_addr, ARCH_DMA_MINALIGN), len);
+ if (spl_decompression_enabled() && image_comp == IH_COMP_GZIP)
+ src_ptr = map_sysmem(ALIGN(CONFIG_SYS_LOAD_ADDR,
ARCH_DMA_MINALIGN), len);
+ else
+ src_ptr = map_sysmem(ALIGN(load_addr,
ARCH_DMA_MINALIGN), len);
length = len;
overhead = get_aligned_image_overhead(info, offset);
diff --git a/include/spl.h b/include/spl.h
index 93e906431e..3a7e448cc7 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -897,4 +897,14 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset,
size_t size);
void board_boot_order(u32 *spl_boot_list);
void spl_save_restore_data(void);
+
+/*
+ * spl_decompression_enabled() - check decompression support is enabled for
SPL build
+ *
+ * Returns true if decompression support is enabled, else False
+ */
+static inline bool spl_decompression_enabled(void)
+{
+ return IS_ENABLED(CONFIG_SPL_GZIP);
+}
#endif
--
2.25.1
[PATCH v3 0/4] support for booting the compressed U-boot binary on Rockchip based ARM64 SOC's
This patchset adds the support on Rockchip based ARM64 SOC's that compress the U-BOOT proper along with dtb and ATF in FIT image format.Second stage bootloader(SPL) loads the compressed binaries, uncompress them and handover control to the next stage. Changes for V3 :- 1. Replaced spl_decompression_enabled() function instead of checking IS_ENABLED(CONFIG_SPL_GZIP) and IS_ENABLED(CONFIG_SPL_LZMA) in spl_fit.c 2. Removed extra wrapping parentheses in spl_decompression_enabled(). Size Comparision between compressed and uncompressed binaries :- size of uncompressed binary:- 9.0M (94,21,824 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 9421824 Sep 10 22:22 u-boot-rockchip.bin size of GZIP compressed binary :- 8.6M (89,85,088 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 8985088 Jul 25 07:42 u-boot-rockchip.bin size of LZMA compressed binary :- 8.6 M (90,06,592 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 9006592 Jul 25 07:47 u-boot-rockchip.bin Test results of Booting time using bootstage command in Uboot command prompt on roc-rk3399-pc board :- 1) Uncompressed U-BOOT : Total boot time ??? 12.063971 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 1,833,884 1,833,884 board_init_f 2,959,528 1,125,644 board_init_r 5,224,521 2,264,993 eth_common_init 5,523,428298,907 eth_initialize 5,523,606178 main_loop 5,523,764158 usb_start 12,063,971 6,540,207 cli_loop 2) GZIP Compressed U-BOOT : Total time ??? 12.824968 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 2,594,709 2,594,709 board_init_f 3,719,969 1,125,260 board_init_r 5,985,450 2,265,481 eth_common_init 6,284,371298,921 eth_initialize 6,284,549178 main_loop 6,284,708159 usb_start 12,824,968 6,540,260 cli_loop 3) LZMA Compressed U-BOOT : Total time ??? 17.025004 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 6,852,254 6,852,254 board_init_f 7,940,143 1,087,889 board_init_r 10,190,458 2,250,315 eth_common_init 10,487,254296,796 eth_initialize 10,487,432178 main_loop 10,487,590158 usb_start 17,025,004 6,537,414 cli_loop As per suggestion from Mr.Jonas Karlman (jo...@kwiboo.se) through Patchset V2,that check boot time with enabling CONFIG_SPL_FIT_SIGNATURE that might impact boot time. Tried to check the boot time with CONFIG_FIT_SIGNATURE enabled, I didnt find any significant boot time improvement with enabling CONFIG_SPL_FIT_SIGNATURE. Comparision of GZIP and LZMA compressed U-boot Boot time with and without Enable of CONFIG_FIT_SIGNATURE :- - GZIP Compressed U-BOOT and CONFIG_FIT_SIGNATURE enabled :- Total time ??? 13.283998 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 3,052,571 3,052,571 board_init_f 4,179,787 1,127,216 board_init_r 6,445,472 2,265,685 eth_common_init 6,744,416298,944 eth_initialize 6,744,593177 main_loop 6,744,751158 usb_start 13,283,998 6,539,247 cli_loop - GZIP Compressed U-BOOT and CONFIG_FIT_SIGNATURE disabled :- Total time ??? 12.824968 seconds - LZMA Compressed U-BOOT and CONFIG_FIT_SIGNATURE enabled :- Total time ??? 17.005996 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 6,775,071 6,775,071 board_init_f 7,902,443 1,127,372 board_init_r 10,167,546 2,265,103 eth_common_init 10,466,418298,872 eth_initialize 10,466,595177 main_loop 10,466,753158 usb_start 17,005,996 6,539,243 cli_loop - LZMA Compressed U-BOOT and CONFIG_FIT_SIGNATURE disabled :- Total time ??? 17.025004 seconds Manoj Sai (4): spl: fit: support for booting a GZIP-compressed U-boot binary spl: fit: support for booting a LZMA-compressed U-boot binary rockchip: Add support to generate GZIP compressed U-boot binary rockchip: Add support to generate LZMA compressed U-boot binary arch/arm/dts/rockchip-u-boot.dtsi | 11 +++ common/spl/spl_fit.c | 20 +--- include/spl.h | 10 ++ 3 files changed, 38 insertions(+), 3 deletions(-) -- 2.25.1
Re: [PATCH v2 0/4] support for booting the compressed U-boot binary on Rockchip based ARM64 SOC's
On Thu, Jul 27, 2023 at 4:51 PM Jonas Karlman wrote: > > On 2023-07-25 05:50, Manoj Sai wrote: > > This patchset adds the support on Rockchip based ARM64 SOC's that compress > > the U-BOOT proper along with dtb > > and ATF in FIT image format.Second stage bootloader(SPL) loads the > > compressed binaries, uncompress > > them and handover control to the next stage. > > > > Changes for V2 :- > > > > - Removed the need to create gzip and lzma compressed U-boot-nodtb files > > using Makefile and added a changeset > > that "compress" field to u-boot-nodtb node and "compression" field to > > u-boot Node in the FIT image, with the help > > of this change binman will create the compressed Binaries. > > > > Size Comparision between compressed and uncompressed binaries :- > > > > size of uncompressed binary :- 9.4 MB (94,26,432 bytes) > > manoj:u-boot$ ls -lb u-boot-rockchip.bin > > -rw-rw-r-- 1 manoj manoj 9426432 Jul 25 07:42 u-boot-rockchip.bin > > > >size of GZIP compressed binary :- 9.0 MB (89,85,088 bytes) > > manoj:u-boot$ ls -lb u-boot-rockchip.bin > > -rw-rw-r-- 1 manoj manoj 8985088 Jul 25 07:42 u-boot-rockchip.bin > > > >size of LZMA compressed binary :- 9.0 MB (90,06,080 bytes) > > manoj:u-boot$ ls -lb u-boot-rockchip.bin > > -rw-rw-r-- 1 manoj manoj 9006080 Jul 25 07:47 u-boot-rockchip.bin > > > > - modified to use the CONFIG_SYS_LOAD_ADDR as the source RAM address to > > store the compressed U-Boot binary which > > will be defined in the machine defconfig file in place of creating a new > > RAM address for a specific board using Kconfig. > > so patchset related to adding a new RAM address to store compressed binary > > has been removed in V2 patchset. > > > > - Removed the patchset related to adding the u-boot-nodtb.bin.gz and > > u-boot-nodtb.bin.lzma as input binary to binman. > > > > > > -- Test results of Booting time using bootstage command in Uboot command > > prompt on roc-rk3399-pc board :- > > > > 1) Uncompressed U-BOOT : Total boot time ≈ 12.3 seconds > > => bootstage report > > Timer summary in microseconds (10 records): > >MarkElapsed Stage > > 0 0 reset > > 1,824,330 1,824,330 board_init_f > > 2,921,678 1,097,348 board_init_r > > 5,179,369 2,257,691 eth_common_init > > 5,478,307298,938 eth_initialize > > 5,478,484177 main_loop > > 5,478,641157 usb_start > > 12,017,936 6,539,295 cli_loop > > > > Accumulated time: > > 15,899 dm_r > >694,371 dm_f > > > > 2) GZIP Compressed U-BOOT : Total boot time ≈ 13.5 seconds > > => bootstage report > > Timer summary in microseconds (10 records): > >MarkElapsed Stage > > 0 0 reset > > 2,591,355 2,591,355 board_init_f > > 3,689,407 1,098,052 board_init_r > > 5,947,314 2,257,907 eth_common_init > > 6,246,250298,936 eth_initialize > > 6,246,427177 main_loop > > 6,246,585158 usb_start > > 12,785,936 6,539,351 cli_loop > > > > Accumulated time: > > 15,902 dm_r > >694,779 dm_f > > > > 2) LZMA Compressed U-BOOT : Total boot time ≈ 23.5 seconds > > => bootstage report > > Timer summary in microseconds (10 records): > >MarkElapsed Stage > > 0 0 reset > > 6,376,405 6,376,405 board_init_f > > 7,471,967 1,095,562 board_init_r > > 9,726,257 2,254,290 eth_common_init > > 10,024,873298,616 eth_initialize > > 10,025,049176 main_loop > > 10,025,208159 usb_start > > 16,564,906 6,539,698 cli_loop > > > > Accumulated time: > > 15,851 dm_r > >693,323 dm_f > > > > > > Patch 1/4 generate a GZIP-compressed U-boot binary using binman if > > CONFIG_SPL_GZIP selected > > Patch 2/4 generate a LZMA-compressed U-boot binary using binman if > > CONFIG_SPL_LZMA selected > > Patch 3/4 uncompress the gzip U-BOOT binary and load the binaries if gzip > > compression supoort is enabled > > Patch 4/4 uncompress the lzma U-BOOT binary and load the binaries if lzma > > compression supoort is enabled > > Boot times seem very slow with compression enabled, please try with > caches enabled, see RFC patch at [1]. Enable
Re: [PATCH 02/10] spl: Kconfig: Address support for compressed U-BOOT raw binary
On Sun, Jul 2, 2023 at 9:04 PM Simon Glass wrote: > > Hi Manoj, > > On Fri, 30 Jun 2023 at 13:12, Manoj Sai > wrote: > > > > Add the support that ,if compression support is enabled in SPL > > a location needs to be defined as the source address where > > compressed U-BOOT raw binary will be stored. > > > > spl_load_fit_image function takes care that, compressed U-Boot raw > > binary which is placed at this address, will be uncompressed to default > > CONFIG_SYS_TEXT_BASE location. > > > > Signed-off-by: Manoj Sai > > Signed-off-by: Suniel Mahesh > > --- > > common/spl/Kconfig | 15 +++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/common/spl/Kconfig b/common/spl/Kconfig > > index 2c042ad306..5dd1f3c469 100644 > > --- a/common/spl/Kconfig > > +++ b/common/spl/Kconfig > > @@ -1547,6 +1547,21 @@ config SPL_AT91_MCK_BYPASS > > The external source has to provide a stable clock on the XIN pin. > > If this option is disabled, the SoC expects a crystal oscillator > > that needs driving on both XIN and XOUT lines. > > blank line here > > > +choice > > + prompt "Location for compressed U-BOOT raw binary" > > compressed U-Boot binary > > > + depends on SPL_GZIP || SPL_LZMA > > + default SPL_UBOOT_COMPRESSED_BINARY_FIT_USER_DEFINED_AREA > > missing help > > This is too long and there is a lot ot redundancy.. How about > SPL_GZIP_FROM_ADDR > > > + > > +config SPL_UBOOT_COMPRESSED_BINARY_FIT_USER_DEFINED_AREA > > + bool "compressed U-BOOT raw binary user-defined location" > > missing help > > blank line > > > +endchoice > > But you only have one thing in the choice, so can you just drop the > choice and use a bool instead? > > > + > > +config SPL_UBOOT_COMPRESSED_BINARY_FIT_USER_DEF_ADDR > > How about SPL_GZIP_LOADADDR? > > Hi simon , We modified to use the CONFIG_SYS_LOAD_ADDR as the source RAM address to store the compressed U-Boot binary which will be defined in a machine defconfig file in place of defining a new RAM address and with the help of this change, able to load and boot the compressed U-boot. -spl_load_fit_image function , will uncompress the U-BOOT binary which is placed in the CONFIG_SYS_LOAD_ADDR to default CONFIG_SYS_TEXT_BASE location and able to load and boot the compressed U-boot. These two patches will be removed in the next v2 patchset which are related to adding new RAM address to store compressed U-boot. 1) https://patchwork.ozlabs.org/project/uboot/patch/20230630121146.513345-3-abbaraju.manoj...@amaruasolutions.com/ 2) https://patchwork.ozlabs.org/project/uboot/patch/20230630121146.513345-4-abbaraju.manoj...@amarulasolutions.com/ Regards, A . Manoj sai > > + hex "Address of memory where compressed U-BOOT raw binary is stored" > > U-Boot (please fix throughout) > > > + depends on SPL_UBOOT_COMPRESSED_BINARY_FIT_USER_DEFINED_AREA > > + help > > + The FIT image containing the compressed U-BOOT raw binary will be > > stored > > + in an area defined at compilation time. This is the address for > > this area. > > endmenu > > > > config TPL > > -- > > 2.25.1 > > > > Regards, > Simon
[PATCH v2 4/4] spl: fit: support for booting a LZMA-compressed U-boot binary
If LZMA Compression support is enabled, LZMA compressed U-Boot
binary will be placed at a specified RAM location which is
defined at CONFIG_SYS_LOAD_ADDR and will be assigned as the
source address.
image_decomp() function, will decompress the LZMA compressed
U-Boot binary which is placed at source address(CONFIG_SYS_LOAD_ADDR)
to the default CONFIG_SYS_TEXT_BASE location.
spl_load_fit_image function will load the decompressed U-Boot
binary, which is placed at the CONFIG_SYS_TEXT_BASE location.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
---
common/spl/spl_fit.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index d728ac71fc..208d2f761e 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -246,7 +246,7 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
debug("%s ", genimg_get_type_name(type));
}
- if (IS_ENABLED(CONFIG_SPL_GZIP)) {
+ if (IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA)) {
fit_image_get_comp(fit, node, &image_comp);
debug("%s ", genimg_get_comp_name(image_comp));
}
@@ -280,8 +280,8 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
__func__, fit_get_name(fit, node, NULL));
return 0;
}
-
- if ((IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP))
+ if ((IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP)
||
+ (IS_ENABLED(CONFIG_SPL_LZMA) && image_comp == IH_COMP_LZMA))
src_ptr = map_sysmem(ALIGN(CONFIG_SYS_LOAD_ADDR,
ARCH_DMA_MINALIGN), len);
else
src_ptr = map_sysmem(ALIGN(load_addr,
ARCH_DMA_MINALIGN), len);
@@ -329,6 +329,16 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return -EIO;
}
length = size;
+ } else if (IS_ENABLED(CONFIG_SPL_LZMA) && image_comp == IH_COMP_LZMA) {
+ size = CONFIG_SYS_BOOTM_LEN;
+ ulong loadEnd;
+
+ if (image_decomp(IH_COMP_LZMA, CONFIG_SYS_LOAD_ADDR, 0, 0,
+load_ptr, src, length, size, &loadEnd)) {
+ puts("Uncompressing error\n");
+ return -EIO;
+ }
+ length = loadEnd - CONFIG_SYS_LOAD_ADDR;
} else {
memcpy(load_ptr, src, length);
}
--
2.25.1
[PATCH v2 0/4] support for booting the compressed U-boot binary on Rockchip based ARM64 SOC's
This patchset adds the support on Rockchip based ARM64 SOC's that compress the U-BOOT proper along with dtb and ATF in FIT image format.Second stage bootloader(SPL) loads the compressed binaries, uncompress them and handover control to the next stage. Changes for V2 :- - Removed the need to create gzip and lzma compressed U-boot-nodtb files using Makefile and added a changeset that "compress" field to u-boot-nodtb node and "compression" field to u-boot Node in the FIT image, with the help of this change binman will create the compressed Binaries. Size Comparision between compressed and uncompressed binaries :- size of uncompressed binary :- 9.4??MB (94,26,432 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 9426432 Jul 25 07:42 u-boot-rockchip.bin size of GZIP compressed binary :- 9.0??MB (89,85,088 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 8985088 Jul 25 07:42 u-boot-rockchip.bin size of LZMA compressed binary :- 9.0??MB (90,06,080 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 9006080 Jul 25 07:47 u-boot-rockchip.bin - modified to use the CONFIG_SYS_LOAD_ADDR as the source RAM address to store the compressed U-Boot binary which will be defined in the machine defconfig file in place of creating a new RAM address for a specific board using Kconfig. so patchset related to adding a new RAM address to store compressed binary has been removed in V2 patchset. - Removed the patchset related to adding the u-boot-nodtb.bin.gz and u-boot-nodtb.bin.lzma as input binary to binman. -- Test results of Booting time using bootstage command in Uboot command prompt on roc-rk3399-pc board :- 1) Uncompressed U-BOOT : Total boot time ??? 12.3 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 1,824,330 1,824,330 board_init_f 2,921,678 1,097,348 board_init_r 5,179,369 2,257,691 eth_common_init 5,478,307298,938 eth_initialize 5,478,484177 main_loop 5,478,641157 usb_start 12,017,936 6,539,295 cli_loop Accumulated time: 15,899 dm_r 694,371 dm_f 2) GZIP Compressed U-BOOT : Total boot time ??? 13.5 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 2,591,355 2,591,355 board_init_f 3,689,407 1,098,052 board_init_r 5,947,314 2,257,907 eth_common_init 6,246,250298,936 eth_initialize 6,246,427177 main_loop 6,246,585158 usb_start 12,785,936 6,539,351 cli_loop Accumulated time: 15,902 dm_r 694,779 dm_f 2) LZMA Compressed U-BOOT : Total boot time ??? 23.5 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 6,376,405 6,376,405 board_init_f 7,471,967 1,095,562 board_init_r 9,726,257 2,254,290 eth_common_init 10,024,873298,616 eth_initialize 10,025,049176 main_loop 10,025,208159 usb_start 16,564,906 6,539,698 cli_loop Accumulated time: 15,851 dm_r 693,323 dm_f Patch 1/4 generate a GZIP-compressed U-boot binary using binman if CONFIG_SPL_GZIP selected Patch 2/4 generate a LZMA-compressed U-boot binary using binman if CONFIG_SPL_LZMA selected Patch 3/4 uncompress the gzip U-BOOT binary and load the binaries if gzip compression supoort is enabled Patch 4/4 uncompress the lzma U-BOOT binary and load the binaries if lzma compression supoort is enabled Manoj Sai (4): rockchip: Add support to generate GZIP compressed U-boot binary rockchip: Add support to generate LZMA compressed U-boot binary spl: fit: support for booting a GZIP-compressed U-boot binary spl: fit: support for booting a LZMA-compressed U-boot binary arch/arm/dts/rockchip-u-boot.dtsi | 11 +++ common/spl/spl_fit.c | 21 + include/spl.h | 10 ++ 3 files changed, 38 insertions(+), 4 deletions(-) -- 2.25.1
[PATCH v2 1/4] rockchip: Add support to generate GZIP compressed U-boot binary
Add support for generating a GZIP-compressed U-boot binary with the
help of binman, if CONFIG_SPL_GZIP is selected.
Signed-off-by: Manoj Sai
---
arch/arm/dts/rockchip-u-boot.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index 2878b80926..524d638e5b 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -48,10 +48,17 @@
type = "standalone";
os = "U-Boot";
arch = "arm64";
+#if defined(CONFIG_SPL_GZIP)
+ compression = "gzip";
+#else
compression = "none";
+#endif
load = ;
entry = ;
u-boot-nodtb {
+#if defined(CONFIG_SPL_GZIP)
+ compress = "gzip";
+#endif
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
--
2.25.1
[PATCH v2 2/4] rockchip: Add support to generate LZMA compressed U-boot binary
Add support for generating a LZMA-compressed U-boot binary with the
help of binman, if CONFIG_SPL_LZMA is selected.
Signed-off-by: Manoj Sai
---
arch/arm/dts/rockchip-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index 524d638e5b..34282bdfb2 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -50,6 +50,8 @@
arch = "arm64";
#if defined(CONFIG_SPL_GZIP)
compression = "gzip";
+#elif defined(CONFIG_SPL_LZMA)
+ compression = "lzma";
#else
compression = "none";
#endif
@@ -58,6 +60,8 @@
u-boot-nodtb {
#if defined(CONFIG_SPL_GZIP)
compress = "gzip";
+#elif defined(CONFIG_SPL_LZMA)
+ compress = "lzma";
#endif
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
--
2.25.1
[PATCH v2 3/4] spl: fit: support for booting a GZIP-compressed U-boot binary
If GZIP Compression support is enabled, GZIP compressed U-Boot binary
will be at a specified RAM location which is defined at
CONFIG_SYS_LOAD_ADDR and will be assign it as the source address.
gunzip function in spl_load_fit_image ,will decompress the GZIP
compressed U-Boot binary which is placed at
source address(CONFIG_SYS_LOAD_ADDR) to the default
CONFIG_SYS_TEXT_BASE location.
spl_load_fit_image function will load the decompressed U-Boot
binary, which is placed at the CONFIG_SYS_TEXT_BASE location.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
---
common/spl/spl_fit.c | 7 +--
include/spl.h| 10 ++
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 730639f756..d728ac71fc 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -239,7 +239,7 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
bool external_data = false;
if (IS_ENABLED(CONFIG_SPL_FPGA) ||
- (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP))) {
+ (IS_ENABLED(CONFIG_SPL_OS_BOOT) && spl_decompression_enabled())) {
if (fit_image_get_type(fit, node, &type))
puts("Cannot get image type.\n");
else
@@ -281,7 +281,10 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return 0;
}
- src_ptr = map_sysmem(ALIGN(load_addr, ARCH_DMA_MINALIGN), len);
+ if ((IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP))
+ src_ptr = map_sysmem(ALIGN(CONFIG_SYS_LOAD_ADDR,
ARCH_DMA_MINALIGN), len);
+ else
+ src_ptr = map_sysmem(ALIGN(load_addr,
ARCH_DMA_MINALIGN), len);
length = len;
overhead = get_aligned_image_overhead(info, offset);
diff --git a/include/spl.h b/include/spl.h
index 92bcaa90a4..088479e357 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -897,4 +897,14 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset,
size_t size);
void board_boot_order(u32 *spl_boot_list);
void spl_save_restore_data(void);
+
+/*
+ * spl_decompression_enabled() - check decompression support is enabled for
SPL build
+ *
+ * Returns true if decompression support is enabled, else False
+ */
+static inline bool spl_decompression_enabled(void)
+{
+ return (IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA));
+}
#endif
--
2.25.1
Re: [PATCH 01/10] Makefile: Add support to generate GZIP compressed raw u-boot binary
Hi Simon, Can you please suggest or briefly explain to me the steps to be followed to generate the compressed u-boot-nodtb.bin.gz and u-boot-nodtb.bin.lzma file with the help of binman , when compression support is enabled . Can you provide me with any reference patch to get it done? Thanks and regards, Manoj sai Amarula Solutions India Pvt. Ltd On Sun, Jul 2, 2023 at 9:04 PM Simon Glass wrote: > > Hi Manoj, > > On Fri, 30 Jun 2023 at 13:12, Manoj Sai > wrote: > > > > Add support for generating a GZIP-compressed raw U-boot binary. > > > > Signed-off-by: Manoj Sai > > Signed-off-by: Suniel Mahesh > > --- > > Makefile | 3 +++ > > 1 file changed, 3 insertions(+) > > Please can you use binman to do that? > > We are trying to remove the extra build rules in the Makefile. > > > > > diff --git a/Makefile b/Makefile > > index 444baaefd0..6e15ebd116 100644 > > --- a/Makefile > > +++ b/Makefile > > @@ -1312,6 +1312,9 @@ endif > > u-boot-nodtb.bin: u-boot FORCE > > $(call if_changed,objcopy_uboot) > > $(BOARD_SIZE_CHECK) > > +ifeq ($(CONFIG_SPL_GZIP),y) > > + @gzip -k u-boot-nodtb.bin > > +endif > > > > u-boot.ldr:u-boot > > $(CREATE_LDR_ENV) > > -- > > 2.25.1 > > > > Regards, > Simon
[PATCH 00/10] support for booting the compressed U-boot binary on Rockchip based SOC's
This patchset adds the support on Rockchip based RK3399 and RK3328 SOC's that compress the U-BOOT proper along with dtb and ATF in FIT image format. Second stage bootloader(SPL) loads the compressed binaries, uncompress them and handover control to the next stage. The size difference observed between uncompressed and compressed FIT images is nearly 67 to 70% and used two compression libraries,LZMA and GZIP. Patch 1/10 generate a GZIP-compressed raw U-boot binary using Makefile Patch 2/10 address to store compressed U-BOOT raw binary using Kconfig Patch 3/10 RAM location to store compressed U-BOOT raw binary for ROCKCHIP based RK3399 and RK3328 SOC's Patch 4/10 uncompress the gzip U-BOOT binary and load the binaries if gzip compression supoort is enabled Patch 5/10 generate a LZMA-compressed raw U-boot binary using Makefile Patch 6/10 uncompress the lzma U-BOOT binary and load the binaries if lzma compression supoort is enabled Patch 7/10 add u-boot-nodtb.bin.gz as an input binary in binman Patch 8/10 add the GZIP compressed uboot raw binary to FIT image Patch 9/10 add u-boot-nodtb.bin.lzma as an input binary in binman Patch 10/10 add the LZMA compressed uboot raw binary to FIT image Manoj Sai (10): Makefile: Add support to generate GZIP compressed raw u-boot binary spl: Kconfig: Address support for compressed U-BOOT raw binary rockchip: RAM location for the compressed U-BOOT raw binary spl: fit: support for booting a GZIP-compressed U-boot raw binary Makefile: Add support to generate LZMA compressed raw u-boot binary spl: fit: support for booting a LZMA-compressed U-boot raw binary binman: Add support for u-boot-nodtb.bin.gz as an input binary rockchip: Add GZIP compressed uboot raw binary to FIT image binman: Add support for u-boot-nodtb.bin.lzma as an input binary rockchip: Add LZMA compressed uboot raw binary to FIT image Makefile | 6 arch/arm/dts/rockchip-u-boot.dtsi| 15 arch/arm/mach-rockchip/Kconfig | 3 ++ common/spl/Kconfig | 15 common/spl/spl_fit.c | 36 +++- tools/binman/etype/283_u_boot_nodtb_lzma.dts | 11 ++ tools/binman/etype/u_boot_nodtb_gzip.py | 28 +++ tools/binman/etype/u_boot_nodtb_lzma.py | 28 +++ tools/binman/ftest.py| 11 ++ tools/binman/test/282_u_boot_nodtb_gzip.dts | 11 ++ 10 files changed, 156 insertions(+), 8 deletions(-) create mode 100644 tools/binman/etype/283_u_boot_nodtb_lzma.dts create mode 100644 tools/binman/etype/u_boot_nodtb_gzip.py create mode 100644 tools/binman/etype/u_boot_nodtb_lzma.py create mode 100644 tools/binman/test/282_u_boot_nodtb_gzip.dts -- 2.25.1
[PATCH 09/10] binman: Add support for u-boot-nodtb.bin.lzma as an input binary
Add an entry type for u-boot-nodtb.bin.lzma, which is a LZMA compressed
raw u-boot binary and a simple test.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
---
tools/binman/etype/283_u_boot_nodtb_lzma.dts | 11
tools/binman/etype/u_boot_nodtb_lzma.py | 28
tools/binman/ftest.py| 6 +
3 files changed, 45 insertions(+)
create mode 100644 tools/binman/etype/283_u_boot_nodtb_lzma.dts
create mode 100644 tools/binman/etype/u_boot_nodtb_lzma.py
diff --git a/tools/binman/etype/283_u_boot_nodtb_lzma.dts
b/tools/binman/etype/283_u_boot_nodtb_lzma.dts
new file mode 100644
index 00..d9a834acf6
--- /dev/null
+++ b/tools/binman/etype/283_u_boot_nodtb_lzma.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot-nodtb-bin-lzma {
+ };
+ };
+};
diff --git a/tools/binman/etype/u_boot_nodtb_lzma.py
b/tools/binman/etype/u_boot_nodtb_lzma.py
new file mode 100644
index 00..c2874aa6e9
--- /dev/null
+++ b/tools/binman/etype/u_boot_nodtb_lzma.py
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2023 Amarula Solutions India
+# Written by Suniel Mahesh
+# Reference from Simon Glass
+#
+# Entry-type module for 'u-boot-nodtb.bin.lzma'
+#
+
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
+
+class Entry_u_boot_nodtb_lzma(Entry_blob):
+"""U-Boot compressed flat binary without device tree appended
+
+Properties / Entry arguments:
+- filename: Filename to include ('u-boot-nodtb.bin.lzma')
+
+This is the U-Boot compressed raw binary, before allowing it to relocate
+itself at runtime it should be decompressed. It does not include a device
+tree blob at the end of it so normally cannot work without it. You can add
a
+u-boot-dtb entry after this one, or use a u-boot entry instead, normally
+expands to a section containing u-boot and u-boot-dtb
+"""
+def __init__(self, section, etype, node):
+super().__init__(section, etype, node)
+
+def GetDefaultFilename(self):
+return 'u-boot-nodtb.bin.lzma'
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 933ebcbd35..d1715523d2 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -43,6 +43,7 @@ from u_boot_pylib import tout
U_BOOT_DATA = b'1234'
U_BOOT_IMG_DATA = b'img'
U_BOOT_NODTB_GZ_DATA = b'uboot nodtb gz'
+U_BOOT_NODTB_LZMA_DATA = b'uboot nodtb lzma'
U_BOOT_SPL_DATA = b'56780123456789abcdefghijklm'
U_BOOT_TPL_DATA = b'tpl9876543210fedcbazywvuts'
U_BOOT_VPL_DATA = b'vpl76543210fedcbazywxyz_'
@@ -6682,5 +6683,10 @@ fdt fdtmapExtract the devicetree
blob from the fdtmap
data = self._DoReadFile('279_u_boot_nodtb_gzip.dts')
self.assertEqual(U_BOOT_NODTB_GZ_DATA, data)
+ def testUBootnodtbBinLzma(self):
+ """Test that u-boot-nodtb.bin.lzma can be put in a file"""
+ data = self._DoReadFile('280_u_boot_nodtb_lzma.dts')
+ self.assertEqual(U_BOOT_NODTB_LZMA_DATA, data)
+
if __name__ == "__main__":
unittest.main()
--
2.25.1
[PATCH 03/10] rockchip: RAM location for the compressed U-BOOT raw binary
Add the support that ,if compression support is enabled in SPL a RAM location needs to be defined as the source address where compressed U-BOOT raw binary will be stored. spl_load_fit_image function takes care that, compressed U-Boot raw binary which is placed at this address, will be uncompressed to default CONFIG_SYS_TEXT_BASE location. Signed-off-by: Manoj Sai --- arch/arm/mach-rockchip/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 9d6d20bf8e..d8d9c1964d 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -520,6 +520,9 @@ config ROCKCHIP_SPI_IMAGE config LNX_KRNL_IMG_TEXT_OFFSET_BASE default TEXT_BASE +config SPL_UBOOT_COMPRESSED_BINARY_FIT_USER_DEF_ADDR + default 0x500 if ROCKCHIP_RK3399 || ROCKCHIP_RK3328 + source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3066/Kconfig" -- 2.25.1
[PATCH 06/10] spl: fit: support for booting a LZMA-compressed U-boot raw binary
If LZMA Compression support is enabled, LZMA compressed U-Boot
raw binary will be at a specified RAM location which is defined
at UBOOT_COMPRESSED_BINARY_FIT_USER_DEF_ADDR and will be assign it as
the source address.
lzmaBuffToBuffDecompress function in spl_load_fit_image ,will decompress
the LZMA compressed U-Boot raw binary which is placed at source address
to the default CONFIG_SYS_TEXT_BASE location.
spl_load_fit_image function will load the decompressed U-Boot
raw binary, which is placed at the CONFIG_SYS_TEXT_BASE location.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
---
common/spl/spl_fit.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index e2101099ef..b4e95d3fb5 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -17,6 +17,9 @@
#include
#include
#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -239,14 +242,15 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
bool external_data = false;
if (IS_ENABLED(CONFIG_SPL_FPGA) ||
- (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP))) {
+ (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP)) ||
+ (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_LZMA))) {
if (fit_image_get_type(fit, node, &type))
puts("Cannot get image type.\n");
else
debug("%s ", genimg_get_type_name(type));
}
- if (IS_ENABLED(CONFIG_SPL_GZIP)) {
+ if (IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA)) {
fit_image_get_comp(fit, node, &image_comp);
debug("%s ", genimg_get_comp_name(image_comp));
}
@@ -281,7 +285,8 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return 0;
}
- if ((IS_ENABLED(CONFIG_SPL_GZIP) && image_comp ==
IH_COMP_GZIP)) {
+ if ((IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP)
||
+ (IS_ENABLED(CONFIG_SPL_LZMA) && image_comp ==
IH_COMP_LZMA)) {
src_ptr =
map_sysmem(ALIGN(CONFIG_VAL(UBOOT_COMPRESSED_BINARY_FIT_USER_DEF_ADDR),
ARCH_DMA_MINALIGN), len);
} else {
@@ -325,13 +330,20 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
load_ptr = map_sysmem(load_addr, length);
- if ((IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP)) {
+ if ((IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) ||
+ (IS_ENABLED(CONFIG_SPL_LZMA) && image_comp == IH_COMP_LZMA)) {
if ((IS_ENABLED(CONFIG_SPL_GZIP) && image_comp ==
IH_COMP_GZIP)) {
size = length;
if (gunzip(load_ptr, CONFIG_SYS_BOOTM_LEN, src, &size))
{
puts("Uncompressing error\n");
return -EIO;
}
+ } else if ((IS_ENABLED(CONFIG_SPL_LZMA) && image_comp ==
IH_COMP_LZMA)) {
+ size = CONFIG_SYS_BOOTM_LEN;
+ if (lzmaBuffToBuffDecompress(load_ptr, &size, src,
length)) {
+ puts("Uncompressing error\n");
+ return -EIO;
+ }
}
length = size;
} else {
--
2.25.1
[PATCH 05/10] Makefile: Add support to generate LZMA compressed raw u-boot binary
Add support for generating LZMA compressed raw u-boot binary. Signed-off-by: Manoj Sai Signed-off-by: Suniel Mahesh --- Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefile b/Makefile index 6e15ebd116..d4f453cce1 100644 --- a/Makefile +++ b/Makefile @@ -1315,6 +1315,9 @@ u-boot-nodtb.bin: u-boot FORCE ifeq ($(CONFIG_SPL_GZIP),y) @gzip -k u-boot-nodtb.bin endif +ifeq ($(CONFIG_SPL_LZMA),y) + @lzma -k u-boot-nodtb.bin +endif u-boot.ldr:u-boot $(CREATE_LDR_ENV) -- 2.25.1
[PATCH 02/10] spl: Kconfig: Address support for compressed U-BOOT raw binary
Add the support that ,if compression support is enabled in SPL a location needs to be defined as the source address where compressed U-BOOT raw binary will be stored. spl_load_fit_image function takes care that, compressed U-Boot raw binary which is placed at this address, will be uncompressed to default CONFIG_SYS_TEXT_BASE location. Signed-off-by: Manoj Sai Signed-off-by: Suniel Mahesh --- common/spl/Kconfig | 15 +++ 1 file changed, 15 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2c042ad306..5dd1f3c469 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1547,6 +1547,21 @@ config SPL_AT91_MCK_BYPASS The external source has to provide a stable clock on the XIN pin. If this option is disabled, the SoC expects a crystal oscillator that needs driving on both XIN and XOUT lines. +choice + prompt "Location for compressed U-BOOT raw binary" + depends on SPL_GZIP || SPL_LZMA + default SPL_UBOOT_COMPRESSED_BINARY_FIT_USER_DEFINED_AREA + +config SPL_UBOOT_COMPRESSED_BINARY_FIT_USER_DEFINED_AREA + bool "compressed U-BOOT raw binary user-defined location" +endchoice + +config SPL_UBOOT_COMPRESSED_BINARY_FIT_USER_DEF_ADDR + hex "Address of memory where compressed U-BOOT raw binary is stored" + depends on SPL_UBOOT_COMPRESSED_BINARY_FIT_USER_DEFINED_AREA + help + The FIT image containing the compressed U-BOOT raw binary will be stored + in an area defined at compilation time. This is the address for this area. endmenu config TPL -- 2.25.1
[PATCH 01/10] Makefile: Add support to generate GZIP compressed raw u-boot binary
Add support for generating a GZIP-compressed raw U-boot binary. Signed-off-by: Manoj Sai Signed-off-by: Suniel Mahesh --- Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefile b/Makefile index 444baaefd0..6e15ebd116 100644 --- a/Makefile +++ b/Makefile @@ -1312,6 +1312,9 @@ endif u-boot-nodtb.bin: u-boot FORCE $(call if_changed,objcopy_uboot) $(BOARD_SIZE_CHECK) +ifeq ($(CONFIG_SPL_GZIP),y) + @gzip -k u-boot-nodtb.bin +endif u-boot.ldr:u-boot $(CREATE_LDR_ENV) -- 2.25.1
[PATCH 04/10] spl: fit: support for booting a GZIP-compressed U-boot raw binary
If GZIP Compression support is enabled, GZIP compressed U-Boot raw binary will
be at a specified RAM location which is defined at
UBOOT_COMPRESSED_BINARY_FIT_USER_DEF_ADDR and will be assign it as
the source address.
gunzip function in spl_load_fit_image ,will decompress the GZIP compressed
U-Boot raw binary which is placed at source address to the default
CONFIG_SYS_TEXT_BASE location.
spl_load_fit_image function will load the decompressed U-Boot
raw binary, which is placed at the CONFIG_SYS_TEXT_BASE location.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
---
common/spl/spl_fit.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 730639f756..e2101099ef 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -281,7 +281,12 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return 0;
}
- src_ptr = map_sysmem(ALIGN(load_addr, ARCH_DMA_MINALIGN), len);
+ if ((IS_ENABLED(CONFIG_SPL_GZIP) && image_comp ==
IH_COMP_GZIP)) {
+ src_ptr =
map_sysmem(ALIGN(CONFIG_VAL(UBOOT_COMPRESSED_BINARY_FIT_USER_DEF_ADDR),
+ ARCH_DMA_MINALIGN), len);
+ } else {
+ src_ptr = map_sysmem(ALIGN(load_addr,
ARCH_DMA_MINALIGN), len);
+ }
length = len;
overhead = get_aligned_image_overhead(info, offset);
@@ -319,11 +324,14 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
board_fit_image_post_process(fit, node, &src, &length);
load_ptr = map_sysmem(load_addr, length);
- if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) {
- size = length;
- if (gunzip(load_ptr, CONFIG_SYS_BOOTM_LEN, src, &size)) {
- puts("Uncompressing error\n");
- return -EIO;
+
+ if ((IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP)) {
+ if ((IS_ENABLED(CONFIG_SPL_GZIP) && image_comp ==
IH_COMP_GZIP)) {
+ size = length;
+ if (gunzip(load_ptr, CONFIG_SYS_BOOTM_LEN, src, &size))
{
+ puts("Uncompressing error\n");
+ return -EIO;
+ }
}
length = size;
} else {
--
2.25.1
[PATCH 10/10] rockchip: Add LZMA compressed uboot raw binary to FIT image
Add LZMA compressed uboot raw binary to FIT image.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
---
arch/arm/dts/rockchip-u-boot.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index 6e95738923..f8a6179c04 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -50,6 +50,8 @@
arch = "arm64";
#if defined(CONFIG_SPL_GZIP)
compression = "gzip";
+#elif defined(CONFIG_SPL_LZMA)
+ compression = "lzma";
#else
compression = "none";
#endif
@@ -58,6 +60,9 @@
#if defined(CONFIG_SPL_GZIP)
u-boot-nodtb-gzip {
};
+#elif defined(CONFIG_SPL_LZMA)
+ u-boot-nodtb-lzma {
+ };
#else
u-boot-nodtb {
};
--
2.25.1
[PATCH 08/10] rockchip: Add GZIP compressed uboot raw binary to FIT image
Add GZIP compressed uboot raw binary to FIT image.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
---
arch/arm/dts/rockchip-u-boot.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index 2878b80926..6e95738923 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -48,11 +48,21 @@
type = "standalone";
os = "U-Boot";
arch = "arm64";
+#if defined(CONFIG_SPL_GZIP)
+ compression = "gzip";
+#else
compression = "none";
+#endif
load = ;
entry = ;
+#if defined(CONFIG_SPL_GZIP)
+ u-boot-nodtb-gzip {
+ };
+#else
u-boot-nodtb {
};
+#endif
+
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
algo = "sha256";
--
2.25.1
[PATCH 07/10] binman: Add support for u-boot-nodtb.bin.gz as an input binary
Add an entry type for u-boot-nodtb.bin.gz, which is a GZIP compressed raw u-boot
binary and a simple test.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
---
tools/binman/etype/u_boot_nodtb_gzip.py | 28 +
tools/binman/ftest.py | 5
tools/binman/test/282_u_boot_nodtb_gzip.dts | 11
3 files changed, 44 insertions(+)
create mode 100644 tools/binman/etype/u_boot_nodtb_gzip.py
create mode 100644 tools/binman/test/282_u_boot_nodtb_gzip.dts
diff --git a/tools/binman/etype/u_boot_nodtb_gzip.py
b/tools/binman/etype/u_boot_nodtb_gzip.py
new file mode 100644
index 00..e8afd3de57
--- /dev/null
+++ b/tools/binman/etype/u_boot_nodtb_gzip.py
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2023 Amarula Solutions India
+# Written by Suniel Mahesh
+# Reference from Simon Glass
+#
+# Entry-type module for 'u-boot-nodtb.bin.gz'
+#
+
+from binman.entry import Entry
+from binman.etype.blob import Entry_blob
+
+class Entry_u_boot_nodtb_gzip(Entry_blob):
+"""U-Boot compressed flat binary without device tree appended
+
+Properties / Entry arguments:
+- filename: Filename to include ('u-boot-nodtb.bin.gz')
+
+This is the U-Boot compressed raw binary, before allowing it to relocate
+itself at runtime it should be decompressed. It does not include a device
+tree blob at the end of it so normally cannot work without it. You can add
a
+u-boot-dtb entry after this one, or use a u-boot entry instead, normally
+expands to a section containing u-boot and u-boot-dtb
+"""
+def __init__(self, section, etype, node):
+super().__init__(section, etype, node)
+
+def GetDefaultFilename(self):
+return 'u-boot-nodtb.bin.gz'
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 43b4f850a6..933ebcbd35 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -42,6 +42,7 @@ from u_boot_pylib import tout
# Contents of test files, corresponding to different entry types
U_BOOT_DATA = b'1234'
U_BOOT_IMG_DATA = b'img'
+U_BOOT_NODTB_GZ_DATA = b'uboot nodtb gz'
U_BOOT_SPL_DATA = b'56780123456789abcdefghijklm'
U_BOOT_TPL_DATA = b'tpl9876543210fedcbazywvuts'
U_BOOT_VPL_DATA = b'vpl76543210fedcbazywxyz_'
@@ -6676,6 +6677,10 @@ fdt fdtmapExtract the devicetree
blob from the fdtmap
['fit'])
self.assertIn("Node '/fit': Missing tool: 'mkimage'", str(e.exception))
+def testUBootnodtbBinGz(self):
+ """Test that u-boot-nodtb.bin.gz can be put in a file"""
+ data = self._DoReadFile('279_u_boot_nodtb_gzip.dts')
+ self.assertEqual(U_BOOT_NODTB_GZ_DATA, data)
if __name__ == "__main__":
unittest.main()
diff --git a/tools/binman/test/282_u_boot_nodtb_gzip.dts
b/tools/binman/test/282_u_boot_nodtb_gzip.dts
new file mode 100644
index 00..79eecea202
--- /dev/null
+++ b/tools/binman/test/282_u_boot_nodtb_gzip.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ u-boot-nodtb-bin-gz {
+ };
+ };
+};
--
2.25.1
[PATCH v2 3/3] rk3566: radxa-cm3: Enable USB OTG
Enable USB OTG support and update the fastboot buffer address for Radxa Compute Module 3 IO Board. This would help to use fastboot by default. Signed-off-by: Manoj Sai --- Changes for v2 :- - Updated the fastboot buffer address in drivers/fastboot/Kconfig. --- configs/radxa-cm3-io-rk3566_defconfig | 2 ++ drivers/fastboot/Kconfig | 1 + 2 files changed, 3 insertions(+) diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index 2100cf2cb2..aba3a65e7f 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -21,6 +21,7 @@ CONFIG_DEBUG_UART_BASE=0xFE66 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y @@ -74,4 +75,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y CONFIG_ERRNO_STR=y diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index eefa34779c..53f0b3a659 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -41,6 +41,7 @@ config FASTBOOT_BUF_ADDR default 0x800800 if ROCKCHIP_RK3288 || ROCKCHIP_RK3329 || \ ROCKCHIP_RK3399 default 0x28 if ROCKCHIP_RK3368 + default 0xc00800 if ROCKCHIP_RK3568 default 0x10 if ARCH_ZYNQMP default 0 if SANDBOX help -- 2.25.1
[PATCH v2 2/3] rockchip: rk356x: update the dwc3_device register offset
update the dwc3_device register offset in board_usb_init()
for rk3568 platforms.
Signed-off-by: Manoj Sai
Reviewed-by: Jagan Teki
---
Changes for v2:-
- None
---
arch/arm/mach-rockchip/board.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index f1f70c81d0..c7729c966a 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -300,6 +300,9 @@ int usb_gadget_handle_interrupts(int index)
int board_usb_init(int index, enum usb_init_type init)
{
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ dwc3_device_data.base = 0xfcc0;
+
return dwc3_uboot_init(&dwc3_device_data);
}
#endif /* CONFIG_USB_DWC3_GADGET */
--
2.25.1
[PATCH v2 1/3] arm: dts: rockchip: rk3566: Enable USB OTG for Radxa CM3
Enable USB OTG support for Radxa Compute Module 3 IO Board
Signed-off-by: Manoj Sai
---
Changes for v2 :-
- None.
Note: Above changeset has sent to kernel mailing list, which is currently under
review.
https://lore.kernel.org/linux-arm-kernel/20230223135929.630787-1-abbaraju.manoj...@amarulasolutions.com/T/#u
---
arch/arm/dts/rk3566-radxa-cm3-io.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts
b/arch/arm/dts/rk3566-radxa-cm3-io.dts
index d89d5263cb..5e4236af4f 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io.dts
+++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts
@@ -254,6 +254,14 @@
status = "okay";
};
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
--
2.25.1
[PATCH 3/3] rk3566: radxa-cm3: Enable USB OTG
Enable USB OTG support and update the fastboot buffer address for Radxa Compute Module 3 IO Board. This would help to use fastboot by default. Signed-off-by: Manoj Sai --- configs/radxa-cm3-io-rk3566_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig index 2100cf2cb2..4d2acef6cd 100644 --- a/configs/radxa-cm3-io-rk3566_defconfig +++ b/configs/radxa-cm3-io-rk3566_defconfig @@ -21,6 +21,7 @@ CONFIG_DEBUG_UART_BASE=0xFE66 CONFIG_DEBUG_UART_CLOCK=2400 CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y +# CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y @@ -47,6 +48,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_BUF_ADDR=0xc00800 CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MISC=y @@ -74,4 +76,5 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y CONFIG_ERRNO_STR=y -- 2.25.1
[PATCH 2/3] rockchip: rk356x: update the dwc3_device register offset
update the dwc3_device register offset in board_usb_init()
for rk3568 platforms.
Signed-off-by: Manoj Sai
---
arch/arm/mach-rockchip/board.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index f1f70c81d0..c7729c966a 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -300,6 +300,9 @@ int usb_gadget_handle_interrupts(int index)
int board_usb_init(int index, enum usb_init_type init)
{
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
+ dwc3_device_data.base = 0xfcc0;
+
return dwc3_uboot_init(&dwc3_device_data);
}
#endif /* CONFIG_USB_DWC3_GADGET */
--
2.25.1
[PATCH 1/3] arm: dts: rockchip: rk3566: Enable USB OTG for Radxa CM3
Enable USB OTG support for Radxa Compute Module 3 IO Board
Signed-off-by: Manoj Sai
---
Note: Above changeset has sent to kernel mailing list, which is currently under
review.
https://lore.kernel.org/linux-arm-kernel/20230223135929.630787-1-abbaraju.manoj...@amarulasolutions.com/T/#u
---
arch/arm/dts/rk3566-radxa-cm3-io.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/rk3566-radxa-cm3-io.dts
b/arch/arm/dts/rk3566-radxa-cm3-io.dts
index d89d5263cb..5e4236af4f 100644
--- a/arch/arm/dts/rk3566-radxa-cm3-io.dts
+++ b/arch/arm/dts/rk3566-radxa-cm3-io.dts
@@ -254,6 +254,14 @@
status = "okay";
};
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
&vop {
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
--
2.25.1
[PATCH 0/3] USB OTG support for radxa cm3 IO board
Patch 1/3 Enable usb otg nodes in device tree. Patch 2/3 Update dwc3_device register offset of rk3568. Patch 3/3 Enable Usb gadget and update the fastboot address in config. Manoj Sai (3): arm: dts: rockchip: rk3566: Enable USB OTG for Radxa CM3 rockchip: rk356x: update the dwc3_device register offset rk3566: radxa-cm3: Enable USB OTG arch/arm/dts/rk3566-radxa-cm3-io.dts | 8 arch/arm/mach-rockchip/board.c| 3 +++ configs/radxa-cm3-io-rk3566_defconfig | 3 +++ 3 files changed, 14 insertions(+) -- 2.25.1
[PATCH 1/1] configs: imx8mp_evk: revert to old ram settings
The 'commit 864ac2cf383e ("board: imx8mp: Add Engicam
i.Core MX8M Plus EDIMM2.2 Starter Kit")' has changed the imx8mp evk ram
settings from 6GB ram to 2GB.
This changeset reverts the above change.
Signed-off-by: Manoj Sai
Reported-by : Peter Bergin
---
include/configs/imx8mp_evk.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h
index 1b533e2c14..d8db83cad8 100644
--- a/include/configs/imx8mp_evk.h
+++ b/include/configs/imx8mp_evk.h
@@ -54,9 +54,11 @@
#define CONFIG_SYS_INIT_RAM_SIZE 0x8
-/* Totally 2GB DDR */
+/* Totally 6GB DDR */
#define CONFIG_SYS_SDRAM_BASE 0x4000
#define PHYS_SDRAM 0x4000
-#define PHYS_SDRAM_SIZE0x8000
+#define PHYS_SDRAM_SIZE0xC000 /* 3 GB */
+#define PHYS_SDRAM_2 0x1
+#define PHYS_SDRAM_2_SIZE 0xC000 /* 3 GB */
#endif
--
2.25.1
[PATCH 0/1] configs: imx8mp_evk: revert to old ram settings
revert the ram settings of imx8mp evk which are changed with
commit id : 864ac2cf383e ("board: imx8mp: Add Engicam i.Core
MX8M Plus EDIMM2.2 Starter Kit")
Manoj Sai (1):
configs: imx8mp_evk: revert to old ram settings
include/configs/imx8mp_evk.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
--
2.25.1
Re: [PATCH v2 3/3] board: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
On Mon, Nov 28, 2022 at 1:37 PM Peter Bergin wrote: > > > On 2022-08-26 14:33, Manoj Sai wrote: > > diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h > > index 388f3bc9ff..140eba3d1c 100644 > > --- a/include/configs/imx8mp_evk.h > > +++ b/include/configs/imx8mp_evk.h > > @@ -55,11 +55,9 @@ > > #define CONFIG_SYS_INIT_RAM_SIZE0x8 > > > > > > -/* Totally 6GB DDR */ > > +/* Totally 2GB DDR */ > > #define CONFIG_SYS_SDRAM_BASE 0x4000 > > #define PHYS_SDRAM 0x4000 > > -#define PHYS_SDRAM_SIZE 0xC000 /* 3 GB */ > > -#define PHYS_SDRAM_2 0x1 > > -#define PHYS_SDRAM_2_SIZE0xC000 /* 3 GB */ > > +#define PHYS_SDRAM_SIZE 0x8000 > > > > #endif > > This patch is applied on master branch since a while, commit > 864ac2cf383e4b8008f09db2e7e53318093c431e. Why does it change RAM size > for NXP's i.Mx8mp EVK from 6GB->2GB? The patch is aimed to add a new > board not to change an existing one. Hi Peter, Thanks for pointing that out. The Mistake is from my side, sent the undesired change. I will revert this change ASAP. Best regards, Manoj sai A > > Best regards, > /Peter >
[PATCH v3] configs:rockchip:roc-rk3399-pc:Enable more configs
This patch enables the following: 1) use preboot configuration to enable usb devices. 2) Enable USB configs so keyboards and other USB devices work, update the number of ports of the usb root hub. - with this addition the updated USB device Tree: 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (12 Mb/s, 0mA) | U-Boot Root Hub | +-2 Hub (12 Mb/s, 100mA) USB 2.0 Hub [MTT] 1 Hub (5 Gb/s, 0mA) U-Boot XHCI Host Controller 3) enable crypto RNG support. 4) Change SPI speed and frequency: - increase the maximum SPI slave device speed, SPI flash max frequency for the environment from 10Mhz to 30MHz. - performance stats for speed update from 10MHz to 30MHz: with 10Mhz speed update: => sf update 0x30 0x80 0x40 4194304 bytes written, 0 bytes skipped in 36.819s, speed 119837 B/s with 30Mhz speed update: => sf update 0x30 0x80 0x40 4194304 bytes written, 0 bytes skipped in 20.319s, speed 220752 B/s Signed-off-by: Manoj Sai Signed-off-by: Da Xue Signed-off-by: dsx724 --- Changes for v3: - shortened the commit header. Changes for v2: - fixed prefix in the commit message. - squash all four patches into a single patch. --- configs/roc-pc-rk3399_defconfig | 8 1 file changed, 8 insertions(+) diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 4625e47537..7754cb8388 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -20,6 +20,7 @@ CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30 # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 @@ -44,6 +45,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_MAX_HZ=3000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y @@ -54,6 +56,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y @@ -66,6 +69,8 @@ CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y @@ -75,6 +80,9 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y -- 2.25.1
[PATCH v2] configs:rockchip: roc-rk3399-pc: Enable the preboot configuration , USB 1.1 support , crypto RNG support and increase the spi flash default speed
This Patch enables the following details of configs to rockchip based roc-rk3399-pc board : 1) Enable preboot configuration to enable usb devices . 2) Fix up USB config options so keyboards and other USB devices work and update the number of ports of the Usb root hub to configuration of CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS . - with this addition the updated USB device Tree : USB device tree: 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (12 Mb/s, 0mA) | U-Boot Root Hub | +-2 Hub (12 Mb/s, 100mA) USB 2.0 Hub [MTT] 1 Hub (5 Gb/s, 0mA) U-Boot XHCI Host Controller 3) enable crypto RNG ( random number generator ) support 4) Set the maximum slave SPI speed to 30MHz : - This patch increases the maximum SPI slave device speed and SPI flash max frequency for environment from 10Mhz to 30MHz . - difference in time of erase and update a region of SPI flash from memory with 10Mhz and 30Mhz frequencey range updation follows :- with 10 Mhz frequency updation :- => sf update 0x30 0x80 0x40 4194304 bytes written, 0 bytes skipped in 36.819s, speed 119837 B/s with 30Mhz frequency updation :- => sf update 0x30 0x80 0x40 4194304 bytes written, 0 bytes skipped in 20.319s, speed 220752 B/s Signed-off-by: Manoj Sai Signed-off-by: Da Xue Signed-off-by: dsx724 --- Changes for v2 :- - fixed prefix in commit message . - squash the all four patches into single patch . --- configs/roc-pc-rk3399_defconfig | 8 1 file changed, 8 insertions(+) diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 4625e47537..7754cb8388 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -20,6 +20,7 @@ CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30 # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 @@ -44,6 +45,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_MAX_HZ=3000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y @@ -54,6 +56,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y @@ -66,6 +69,8 @@ CONFIG_PWM_ROCKCHIP=y # CONFIG_RAM_ROCKCHIP_DEBUG is not set CONFIG_RAM_RK3399_LPDDR4=y CONFIG_DM_RESET=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y @@ -75,6 +80,9 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y -- 2.25.1
[PATCH 4/4] configs: roc-pc-rk3399:Set the maximum slave SPI speed to 30MHz
-While the SPI controller speed is defined by DTS, the maximum slave speed (connected devices) is limited by the pre-defined configuration value CONFIG_SF_DEFAULT_SPEED from 10 MHz to 30Mhz. -set the Value of SPI flash max frequency for environment to 30Mhz. This patch increases this maximum SPI slave device speed and SPI flash max frequency for environment to 30MHz . difference in time of erase and update a region of SPI flash from memory with 10Mhz and 30Mhz frequencey range updation : => sf update 0x30 0x80 0x40 with 10 Mhz frequency updation :- 4194304 bytes written, 0 bytes skipped in 36.819s, speed 119837 B/s with 30Mhz frequency updation :- 4194304 bytes written, 0 bytes skipped in 20.319s, speed 220752 B/s Signed-off-by: Manoj Sai Signed-off-by: Da Xue Signed-off-by: dsx724 --- configs/roc-pc-rk3399_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 84e72e8b60..7754cb8388 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -45,6 +45,7 @@ CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_MAX_HZ=3000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_ROCKCHIP_GPIO=y @@ -55,6 +56,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_SPI_FLASH_WINBOND=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -- 2.25.1
[PATCH 3/4] configs:roc-pc-rk3399 :Enable crypto RNG support
enable crypto RNG support for roc-pc-rk3399. Signed-off-by: Manoj Sai Signed-off-by: Da Xue Signed-off-by: dsx724
[PATCH 2/4] configs: roc-pc-rk3399:fix up USB support
- Fix up USB config options so keyboards and other USB devices work . - Update the number of ports of the Usb root hub to configuration of CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS . USB device tree: 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (12 Mb/s, 0mA) | U-Boot Root Hub | +-2 Hub (12 Mb/s, 100mA) USB 2.0 Hub [MTT] 1 Hub (5 Gb/s, 0mA) U-Boot XHCI Host Controller Signed-off-by: Manoj Sai Signed-off-by: Da Xue Signed-off-by: dsx724 --- configs/roc-pc-rk3399_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 84e82da3cf..ffd809687b 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -76,6 +76,9 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y -- 2.25.1
[PATCH 1/4] configs:roc-pc-rk3399 :Enable CONFIG_USE_PREBOOT
use preboot configuration to enable usb devices Signed-off-by: Manoj Sai Signed-off-by: Da Xue --- configs/roc-pc-rk3399_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig index 4625e47537..84e82da3cf 100644 --- a/configs/roc-pc-rk3399_defconfig +++ b/configs/roc-pc-rk3399_defconfig @@ -20,6 +20,7 @@ CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30 # CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x2e000 -- 2.25.1
[PATCH 0/4] addition of configs for rockchip based roc-pc-rk3399 board
Patch 1/4 use preboot configuration to enable usb devices Patch 2/4 fix up USB support which can recognize any USB1.1 devices Patch 3/4 Enable crypto RNG support Patch 4/4 Set the maximum slave SPI speed to 30MHz Manoj Sai (4): configs: roc-pc-rk3399 :Enable preboot config . configs: roc-pc-rk3399:fix up USB support . configs: roc-pc-rk3399 :Enable crypto RNG support. configs: roc-pc-rk3399:Set the maximum slave SPI speed and spi flash max frequency for environment to 30MHz. configs/roc-pc-rk3399_defconfig | 8 1 file changed, 8 insertions(+) -- 2.25.1
[PATCH v2 3/3] board: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam.
i.Core MX8M Plus needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: Manoj Sai
---
Changes for v2 :
- add no-1-8-v property to SD card Node because if UHS speed modes
a compatible SD card switches down to 1.8V during enumeration
if after this a software reboot/crash takes place and on-chip ROM tries to
enumerate the SD card, the difference in IO voltages (host @ 3.3V and card @
1.8V)
may end up damaging the card and faced the problem of detection of UHS
SD Card .
---
.../imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi | 149 ++
arch/arm/mach-imx/imx8m/Kconfig | 15 +
board/engicam/imx8mp/Kconfig | 15 +
board/engicam/imx8mp/MAINTAINERS |7 +
board/engicam/imx8mp/Makefile | 12 +
board/engicam/imx8mp/icore_mx8mp.c| 73 +
board/engicam/imx8mp/imximage-lpddr4.cfg |8 +
board/engicam/imx8mp/lpddr4_timing.c | 1850 +
board/engicam/imx8mp/spl.c| 152 ++
configs/imx8mp-icore-mx8mp-edimm2.2_defconfig | 112 +
include/configs/imx8mp_evk.h |6 +-
include/configs/imx8mp_icore_mx8mp.h | 64 +
12 files changed, 2459 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
create mode 100644 board/engicam/imx8mp/Kconfig
create mode 100644 board/engicam/imx8mp/MAINTAINERS
create mode 100644 board/engicam/imx8mp/Makefile
create mode 100644 board/engicam/imx8mp/icore_mx8mp.c
create mode 100644 board/engicam/imx8mp/imximage-lpddr4.cfg
create mode 100644 board/engicam/imx8mp/lpddr4_timing.c
create mode 100644 board/engicam/imx8mp/spl.c
create mode 100644 configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
create mode 100644 include/configs/imx8mp_icore_mx8mp.h
diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
new file mode 100644
index 00..342c523b0c
--- /dev/null
+++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+®_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <2>;
+};
+
+®_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&i2c3 {
+ u-boot,dm-spl;
+};
+
+&i2c4 {
+ u-boot,dm-spl;
+};
+
+&i2c5 {
+ u-boot,dm-spl;
+};
+
+&i2c6 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ no-1-8-v;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&eqos {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ðphy0 {
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <15000>;
+ reset-post-delay-us = <10>;
+};
+
+&fec {
+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 979b30ae39..3054248ca5 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -160,6 +160,20 @@ config TARGET_IMX8MP_DH_DHCOM_PDK2
select IMX8M_LPDDR4
select SUPPORT_SPL
+config TARGET_IMX8MP_ICORE_MX8MP
+ bool "Engicam i.Core MX8M Plus SOM"
+ select BINMAN
+ se
[PATCH v2 2/3] arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Plus PCIe
- MIPI CSI
- 2x CAN
- Audio Out
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam.
i.Core MX8M Plus needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.
Add support for it.
Sync the i.Core MX8M Plus is an EDIMM SoM based on NXP
devicetree file from linux-next tree.
commit (arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus
EDIMM2.2 Starter Kit)
Signed-off-by: Manoj Sai
Signed-off-by: Jagan Teki
---
Changes for v2 :
- None
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts | 175 +++
2 files changed, 176 insertions(+)
create mode 100644 arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7330121dba..18b2d36ab3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -969,6 +969,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-phanbell.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-evk.dtb \
+ imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \
imx8mp-venice-gw74xx.dtb \
diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts
b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts
new file mode 100644
index 00..dd703b6a5e
--- /dev/null
+++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+
+#include "imx8mp.dtsi"
+#include "imx8mp-icore-mx8mp.dtsi"
+#include
+
+/ {
+ model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit";
+ compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp",
+"fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ reg_usb1_vbus: regulator-usb1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1>;
+ regulator-max-microvolt = <500>;
+ regulator-min-microvolt = <500>;
+ regulator-name = "usb1_host_vbus";
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-max-microvolt = <330>;
+ regulator-min-microvolt = <330>;
+ regulator-name = "VSD_3V3";
+ };
+};
+
+/* Ethernet */
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,led-mode = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* SDCARD */
+&usdhc2 {
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ pinctrl-names = "default" ;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC
0x2
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO
[PATCH v2 1/3] arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
from Engicam.
General features:
- NXP i.MX8M Plus
- Up to 4GB LDDR4
- 8 eMMC
- Gigabit Ethernet
- USB 3.0, 2.0 Host/OTG
- PCIe 3.0 interface
- I2S
- LVDS
- rest of i.MX8M Plus features
i.Core MX8M Plus needs to mount on top of Engicam baseboards
for creating complete platform solutions.
Add support for it.
Sync the i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
from Engicam devicetree file from linux-next tree.
commit (arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM)
Signed-off-by: Manoj Sai
Signed-off-by: Jagan Teki
---
Changes for v2 :
- Fixed double Signed-Off-by addition in Commit Message .
---
arch/arm/dts/imx8mp-icore-mx8mp.dtsi | 186 +++
1 file changed, 186 insertions(+)
create mode 100644 arch/arm/dts/imx8mp-icore-mx8mp.dtsi
diff --git a/arch/arm/dts/imx8mp-icore-mx8mp.dtsi
b/arch/arm/dts/imx8mp-icore-mx8mp.dtsi
new file mode 100644
index 00..5116079cce
--- /dev/null
+++ b/arch/arm/dts/imx8mp-icore-mx8mp.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+ compatible = "engicam,icore-mx8mp", "fsl,imx8mp";
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&i2c1 {
+ clock-frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pca9450: pmic@25 {
+ compatible = "nxp,pca9450c";
+ interrupt-parent = <&gpio3>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ reg = <0x25>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <72>;
+ regulator-max-microvolt = <100>;
+ regulator-name = "BUCK1";
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ nxp,dvs-run-voltage = <95>;
+ nxp,dvs-standby-voltage = <85>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1025000>;
+ regulator-min-microvolt = <72>;
+ regulator-name = "BUCK2";
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <360>;
+ regulator-min-microvolt = <300>;
+ regulator-name = "BUCK4";
+ };
+
+ buck5: BUCK5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <195>;
+ regulator-min-microvolt = <165>;
+ regulator-name = "BUCK5";
+ };
+
+ buck6: BUCK6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1155000>;
+ regulator-min-microvolt = <1045000>;
+ regulator-name = "BUCK6";
+ };
+
+ ldo1: LDO1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <195>;
+ regulator-min-microvolt = <165>;
+ regulator-name = "LDO1";
+ };
+
+ ldo3: LDO3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <189>;
+
[PATCH v1 3/3] board: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam.
i.Core MX8M Plus needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.
Add support for it.
Signed-off-by: Jagan Teki
Signed-off-by: Manoj Sai
Signed-off-by: Matteo Lisi
---
.../imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi | 148 ++
arch/arm/mach-imx/imx8m/Kconfig | 15 +
board/engicam/imx8mp/Kconfig | 15 +
board/engicam/imx8mp/MAINTAINERS |7 +
board/engicam/imx8mp/Makefile | 12 +
board/engicam/imx8mp/icore_mx8mp.c| 73 +
board/engicam/imx8mp/imximage-lpddr4.cfg |8 +
board/engicam/imx8mp/lpddr4_timing.c | 1850 +
board/engicam/imx8mp/spl.c| 152 ++
configs/imx8mp-icore-mx8mp-edimm2.2_defconfig | 112 +
include/configs/imx8mp_evk.h |6 +-
include/configs/imx8mp_icore_mx8mp.h | 64 +
12 files changed, 2458 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
create mode 100644 board/engicam/imx8mp/Kconfig
create mode 100644 board/engicam/imx8mp/MAINTAINERS
create mode 100644 board/engicam/imx8mp/Makefile
create mode 100644 board/engicam/imx8mp/icore_mx8mp.c
create mode 100644 board/engicam/imx8mp/imximage-lpddr4.cfg
create mode 100644 board/engicam/imx8mp/lpddr4_timing.c
create mode 100644 board/engicam/imx8mp/spl.c
create mode 100644 configs/imx8mp-icore-mx8mp-edimm2.2_defconfig
create mode 100644 include/configs/imx8mp_icore_mx8mp.h
diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
new file mode 100644
index 00..ac4873a21d
--- /dev/null
+++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+®_usdhc2_vmmc {
+ u-boot,off-on-delay-us = <2>;
+};
+
+®_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&i2c3 {
+ u-boot,dm-spl;
+};
+
+&i2c4 {
+ u-boot,dm-spl;
+};
+
+&i2c5 {
+ u-boot,dm-spl;
+};
+
+&i2c6 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&eqos {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ðphy0 {
+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <15000>;
+ reset-post-delay-us = <10>;
+};
+
+&fec {
+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 979b30ae39..3054248ca5 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -160,6 +160,20 @@ config TARGET_IMX8MP_DH_DHCOM_PDK2
select IMX8M_LPDDR4
select SUPPORT_SPL
+config TARGET_IMX8MP_ICORE_MX8MP
+ bool "Engicam i.Core MX8M Plus SOM"
+ select BINMAN
+ select IMX8MP
+ select IMX8M_LPDDR4
+ select SUPPORT_SPL
+ help
+ i.Core MX8M Plus is an EDIMM SOM based on NXP i.MX8MP.
+
+ i.Core MX8M Plus EDIMM2.2:
+ * EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
+ * i.Core MX8M Plus needs to mount on top of EDIMM2.2 for
+ creating complete i.Core MX8M Plus EDIMM2.2 Starter
[PATCH v1 2/3] arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit
Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Plus PCIe
- MIPI CSI
- 2x CAN
- Audio Out
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam.
i.Core MX8M Plus needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit.
Add support for it.
Sync the i.Core MX8M Plus is an EDIMM SoM based on NXP
devicetree file from linux-next tree.
commit (arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus
EDIMM2.2 Starter Kit)
Signed-off-by: Manoj Sai
Signed-off-by: Jagan Teki
Signed-off-by: Matteo Lisi
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts | 176 +++
2 files changed, 177 insertions(+)
create mode 100644 arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7330121dba..18b2d36ab3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -969,6 +969,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-phanbell.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-evk.dtb \
+ imx8mp-icore-mx8mp-edimm2.2.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \
imx8mp-venice-gw74xx.dtb \
diff --git a/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts
b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts
new file mode 100644
index 00..8d81b2b986
--- /dev/null
+++ b/arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts
@@ -0,0 +1,176 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/dts-v1/;
+
+#include "imx8mp.dtsi"
+#include "imx8mp-icore-mx8mp.dtsi"
+#include
+
+/ {
+ model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit";
+ compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp",
+"fsl,imx8mp";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ reg_usb1_vbus: regulator-usb1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb1>;
+ regulator-max-microvolt = <500>;
+ regulator-min-microvolt = <500>;
+ regulator-name = "usb1_host_vbus";
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ regulator-max-microvolt = <330>;
+ regulator-min-microvolt = <330>;
+ regulator-name = "VSD_3V3";
+ };
+};
+
+/* Ethernet */
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-handle = <ðphy0>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ micrel,led-mode = <0>;
+ reg = <7>;
+ };
+ };
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_0 {
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* SDCARD */
+&usdhc2 {
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ no-1-8-v;
+ pinctrl-names = "default" ;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC
0x2
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO
[PATCH v1 1/3] arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
from Engicam.
General features:
- NXP i.MX8M Plus
- Up to 4GB LDDR4
- 8 eMMC
- Gigabit Ethernet
- USB 3.0, 2.0 Host/OTG
- PCIe 3.0 interface
- I2S
- LVDS
- rest of i.MX8M Plus features
i.Core MX8M Plus needs to mount on top of Engicam baseboards
for creating complete platform solutions.
Add support for it.
Sync the i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus
from Engicam devicetree file from linux-next tree.
commit (arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM)
Signed-off-by: Manoj Sai
Signed-off-by: Signed-off-by: Jagan Teki
Signed-off-by: Matteo Lisi
---
arch/arm/dts/imx8mp-icore-mx8mp.dtsi | 186 +++
1 file changed, 186 insertions(+)
create mode 100644 arch/arm/dts/imx8mp-icore-mx8mp.dtsi
diff --git a/arch/arm/dts/imx8mp-icore-mx8mp.dtsi
b/arch/arm/dts/imx8mp-icore-mx8mp.dtsi
new file mode 100644
index 00..5116079cce
--- /dev/null
+++ b/arch/arm/dts/imx8mp-icore-mx8mp.dtsi
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+ compatible = "engicam,icore-mx8mp", "fsl,imx8mp";
+};
+
+&A53_0 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2>;
+};
+
+&i2c1 {
+ clock-frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pca9450: pmic@25 {
+ compatible = "nxp,pca9450c";
+ interrupt-parent = <&gpio3>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ reg = <0x25>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <72>;
+ regulator-max-microvolt = <100>;
+ regulator-name = "BUCK1";
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ nxp,dvs-run-voltage = <95>;
+ nxp,dvs-standby-voltage = <85>;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1025000>;
+ regulator-min-microvolt = <72>;
+ regulator-name = "BUCK2";
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <360>;
+ regulator-min-microvolt = <300>;
+ regulator-name = "BUCK4";
+ };
+
+ buck5: BUCK5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <195>;
+ regulator-min-microvolt = <165>;
+ regulator-name = "BUCK5";
+ };
+
+ buck6: BUCK6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1155000>;
+ regulator-min-microvolt = <1045000>;
+ regulator-name = "BUCK6";
+ };
+
+ ldo1: LDO1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <195>;
+ regulator-min-microvolt = <165>;
+ regulator-name = "LDO1";
+ };
+
+ ldo3: LDO3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <189>;
+ regulator-min-microvolt = <171>;
+
[PATCH v1 0/3] This series adds U-boot bootloader support for
Patch 1/3 adds dts support for Engicam i.Core MX8M Plus SoM Patch 2/3 adds dts support for Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit Patch 3/3 adds board and configs related support for Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit Manoj Sai (3): arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit board: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit arch/arm/dts/Makefile |1 + .../imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi | 148 ++ arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts | 176 ++ arch/arm/dts/imx8mp-icore-mx8mp.dtsi | 186 ++ arch/arm/mach-imx/imx8m/Kconfig | 15 + board/engicam/imx8mp/Kconfig | 15 + board/engicam/imx8mp/MAINTAINERS |7 + board/engicam/imx8mp/Makefile | 12 + board/engicam/imx8mp/icore_mx8mp.c| 73 + board/engicam/imx8mp/imximage-lpddr4.cfg |8 + board/engicam/imx8mp/lpddr4_timing.c | 1850 + board/engicam/imx8mp/spl.c| 152 ++ configs/imx8mp-icore-mx8mp-edimm2.2_defconfig | 112 + include/configs/imx8mp_evk.h |6 +- include/configs/imx8mp_icore_mx8mp.h | 64 + 15 files changed, 2821 insertions(+), 4 deletions(-) create mode 100644 arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-icore-mx8mp-edimm2.2.dts create mode 100644 arch/arm/dts/imx8mp-icore-mx8mp.dtsi create mode 100644 board/engicam/imx8mp/Kconfig create mode 100644 board/engicam/imx8mp/MAINTAINERS create mode 100644 board/engicam/imx8mp/Makefile create mode 100644 board/engicam/imx8mp/icore_mx8mp.c create mode 100644 board/engicam/imx8mp/imximage-lpddr4.cfg create mode 100644 board/engicam/imx8mp/lpddr4_timing.c create mode 100644 board/engicam/imx8mp/spl.c create mode 100644 configs/imx8mp-icore-mx8mp-edimm2.2_defconfig create mode 100644 include/configs/imx8mp_icore_mx8mp.h -- 2.25.1
