Add support for the InnoComm i.MX8MM WB15EVK board
(https://www.innocomm.com/product_inner.aspx?num=2233).
The following functionality is supported:
- eMMC
- MMC/SD
- GPIO
- I2C
- Ethernet
Signed-off-by: Matt Porter
---
arch/arm/dts/Makefile |1 +
arch/arm/dts/imx8mm-wb15evk-u-boot.dtsi | 120 ++
arch/arm/dts/imx8mm-wb15evk.dts | 390
arch/arm/mach-imx/imx8m/Kconfig |7 +
board/innocomm/imx8mm_wb15evk/Kconfig | 16 +
board/innocomm/imx8mm_wb15evk/MAINTAINERS |6 +
board/innocomm/imx8mm_wb15evk/Makefile| 14 +
board/innocomm/imx8mm_wb15evk/README.rst | 46 +
.../innocomm/imx8mm_wb15evk/imx8mm_wb15evk.c | 35 +
.../imx8mm_wb15evk/lpddr4_timing-2400mts.c| 1849 +
board/innocomm/imx8mm_wb15evk/lpddr4_timing.c | 1849 +
board/innocomm/imx8mm_wb15evk/spl.c | 173 ++
configs/imx8mm_wb15evk_defconfig | 83 +
include/configs/imx8mm_wb15evk.h | 156 ++
14 files changed, 4745 insertions(+)
create mode 100644 arch/arm/dts/imx8mm-wb15evk-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mm-wb15evk.dts
create mode 100644 board/innocomm/imx8mm_wb15evk/Kconfig
create mode 100644 board/innocomm/imx8mm_wb15evk/MAINTAINERS
create mode 100644 board/innocomm/imx8mm_wb15evk/Makefile
create mode 100644 board/innocomm/imx8mm_wb15evk/README.rst
create mode 100644 board/innocomm/imx8mm_wb15evk/imx8mm_wb15evk.c
create mode 100644 board/innocomm/imx8mm_wb15evk/lpddr4_timing-2400mts.c
create mode 100644 board/innocomm/imx8mm_wb15evk/lpddr4_timing.c
create mode 100644 board/innocomm/imx8mm_wb15evk/spl.c
create mode 100644 configs/imx8mm_wb15evk_defconfig
create mode 100644 include/configs/imx8mm_wb15evk.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 820ee9733a..128c118ac3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -721,6 +721,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
imx8mm-verdin.dtb \
+ imx8mm-wb15evk.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-evk.dtb \
imx8mp-evk.dtb
diff --git a/arch/arm/dts/imx8mm-wb15evk-u-boot.dtsi
b/arch/arm/dts/imx8mm-wb15evk-u-boot.dtsi
new file mode 100644
index 00..67dce571e5
--- /dev/null
+++ b/arch/arm/dts/imx8mm-wb15evk-u-boot.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright 2020 Konsulko Group
+ */
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+_reg_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+_uart2 {
+ u-boot,dm-spl;
+};
+
+_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+_usdhc2 {
+ u-boot,dm-spl;
+};
+
+_usdhc3 {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+_i2c1 {
+ u-boot,dm-spl;
+};
+
+_pmic {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-wb15evk.dts b/arch/arm/dts/imx8mm-wb15evk.dts
new file mode 100644
index 00..38e49ea11b
--- /dev/null
+++ b/arch/arm/dts/imx8mm-wb15evk.dts
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include
+#include "imx8mm.dtsi"
+
+/ {
+ model = "InnoComm i.MX8MM WB15EVK";
+ compatible = "fsl,imx8mm-wb15evk", "fsl,imx8mm";
+
+ chosen {
+ stdout-path =
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <_reg_usdhc2_vmmc>;
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = < 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+_0 {
+ cpu-supply = <_reg>;
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <>;
+ phy-reset-gpios = < 9