From: haikun
Change address_cells and size_cells of root node and 'soc' node
from 2 to 1.
We backport ls1021a device tree source files from kernel to u-boot.
Kernel files set address_cells and size_cells to 2 in order to access
more than 4GB space.
But we don't have this requirement now and u-boot fdtdec_get_xxx interfaces
can't support property whose size is 'u64' completely.
So make this change.
Signed-off-by: Haikun Wang
---
arch/arm/dts/ls1021a-qds.dts | 6 ++--
arch/arm/dts/ls1021a-twr.dts | 2 +-
arch/arm/dts/ls1021a.dtsi| 72 ++--
3 files changed, 40 insertions(+), 40 deletions(-)
diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
index c89f85e..7454ac6 100644
--- a/arch/arm/dts/ls1021a-qds.dts
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -101,9 +101,9 @@
#address-cells = <2>;
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
- ranges = <0x0 0x0 0x0 0x6000 0x0800
- 0x2 0x0 0x0 0x7e80 0x0001
- 0x3 0x0 0x0 0x7fb0 0x0100>;
+ ranges = <0x0 0x0 0x6000 0x0800
+ 0x2 0x0 0x7e80 0x0001
+ 0x3 0x0 0x7fb0 0x0100>;
status = "okay";
nor@0,0 {
diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts
index 34ac82d..2f0481d 100644
--- a/arch/arm/dts/ls1021a-twr.dts
+++ b/arch/arm/dts/ls1021a-twr.dts
@@ -46,7 +46,7 @@
#address-cells = <2>;
#size-cells = <1>;
/* NOR Flash on board */
- ranges = <0x0 0x0 0x0 0x6000 0x0800>;
+ ranges = <0x0 0x0 0x6000 0x0800>;
status = "okay";
nor@0,0 {
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 434b938..064d10c 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -6,7 +6,7 @@
* SPDX-License-Identifier:GPL-2.0+
*/
-#include "skeleton64.dtsi"
+#include "skeleton.dtsi"
#include
/ {
@@ -58,8 +58,8 @@
soc {
compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
device_type = "soc";
interrupt-parent = <&gic>;
ranges;
@@ -68,29 +68,29 @@
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
- reg = <0x0 0x1401000 0x0 0x1000>,
- <0x0 0x1402000 0x0 0x1000>,
- <0x0 0x1404000 0x0 0x2000>,
- <0x0 0x1406000 0x0 0x2000>;
+ reg = <0x1401000 0x1000>,
+ <0x1402000 0x1000>,
+ <0x1404000 0x2000>,
+ <0x1406000 0x2000>;
interrupts = ;
};
ifc: ifc@153 {
compatible = "fsl,ifc", "simple-bus";
- reg = <0x0 0x153 0x0 0x1>;
+ reg = <0x153 0x1>;
interrupts = ;
};
dcfg: dcfg@1ee {
compatible = "fsl,ls1021a-dcfg", "syscon";
- reg = <0x0 0x1ee 0x0 0x1>;
+ reg = <0x1ee 0x1>;
big-endian;
};
esdhc: esdhc@156 {
compatible = "fsl,esdhc";
- reg = <0x0 0x156 0x0 0x1>;
+ reg = <0x156 0x1>;
interrupts = ;
clock-frequency = <0>;
voltage-ranges = <1800 1800 3300 3300>;
@@ -102,14 +102,14 @@
scfg: scfg@157 {
compatible = "fsl,ls1021a-scfg", "syscon";
- reg = <0x0 0x157 0x0 0x1>;
+ reg = <0x157 0x1>;
big-endian;
};
clockgen: clocking@1ee1000 {
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x0 0x1ee1000 0x1>;
+ ranges = <0x0 0x1ee1000 0x1>;
sysclk: sysclk {
compatible = "fixed-clock";
@@ -148,7 +148,7 @@
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0x0 0x210 0x0 0x1>;
+ reg = <0x210 0x1>;
interrupts = ;
clock-names = "dspi";
clocks = <&platform_clk 1>;
@@ -161,7 +161,7 @@
