Re: [U-Boot] [PATCH v3 11/20] arm: socfpga: Add DDR driver for Arria 10
On Isn, 2017-10-16 at 22:08 -0500, Dinh Nguyen wrote: > > On 10/13/2017 03:08 AM, tien.fong.c...@intel.com wrote: > > > > From: Tien Fong Chee> > > > Add DDR driver suppport for Arria 10. > s/suppport/support > Okay. > > > > > > Signed-off-by: Tien Fong Chee > > --- > > arch/arm/mach-socfpga/include/mach/sdram.h | 2 + > > arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 2 + > > drivers/ddr/altera/Makefile| 1 + > > drivers/ddr/altera/sdram_arria10.c | 736 > > + > > 4 files changed, 741 insertions(+) > > create mode 100644 drivers/ddr/altera/sdram_arria10.c > > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h > > b/arch/arm/mach-socfpga/include/mach/sdram.h > > index 137e073..33f830b 100644 > > --- a/arch/arm/mach-socfpga/include/mach/sdram.h > > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h > > @@ -10,6 +10,8 @@ > > > > #if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > #include > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > +#include > > #endif > > > > #endif > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h > > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h > > index 1d7b7c1..e7a2503 100644 > > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h > > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h > > @@ -8,6 +8,7 @@ > > #define _SOCFPGA_SDRAM_ARRIA10_H_ > > > > #ifndef __ASSEMBLY__ > > +int ddr_calibration_sequence(void); > > > > struct socfpga_ecc_hmc { > > u32 ip_rev_id; > > @@ -204,6 +205,7 @@ struct socfpga_io48_mmr { > > u32 niosreserve1; > > u32 niosreserve2; > > }; > > + > > #endif /*__ASSEMBLY__*/ > > > > #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK0x1 > > F00 > > diff --git a/drivers/ddr/altera/Makefile > > b/drivers/ddr/altera/Makefile > > index ac4ab85..02f8b7c 100644 > > --- a/drivers/ddr/altera/Makefile > > +++ b/drivers/ddr/altera/Makefile > > @@ -10,4 +10,5 @@ > > > > ifdef CONFIG_ALTERA_SDRAM > > obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o > > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o > > endif > > diff --git a/drivers/ddr/altera/sdram_arria10.c > > b/drivers/ddr/altera/sdram_arria10.c > > new file mode 100644 > > index 000..be8aff3 > > --- /dev/null > > +++ b/drivers/ddr/altera/sdram_arria10.c > > @@ -0,0 +1,736 @@ > > +/* > > + * Copyright (C) 2017 Intel Corporation > > + * > > + * SPDX-License-Identifier:GPL-2.0 > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +static void sdram_mmr_init(void); > > +static unsigned long long sdram_size_calc(void); > Use uint64_t > Okay. > > > > + > > +/* FAWBANK - Number of Bank of a given device involved in the FAW > > period. */ > > +#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1) > > + > > +#define ARRIA_DDR_CONFIG(A, B, C, R) \ > > + (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) > > +#define DDR_CONFIG_ELEMENTSARRAY_SIZE(ddr_config) > > +#define DDR_REG_SEQ2CORE0xFFD0507C > > +#define DDR_REG_CORE2SEQ0xFFD05078 > > +#define DDR_READ_LATENCY_DELAY 40 > > +#define DDR_SIZE_2GB_HEX 0x8000 > > +#define DDR_MAX_TRIES 0x0010 > > + > > +#define IO48_MMR_DRAMSTS 0xFFCFA0EC > > +#define IO48_MMR_NIOS2_RESERVE00xFFCFA110 > > +#define IO48_MMR_NIOS2_RESERVE10xFFCFA114 > > +#define IO48_MMR_NIOS2_RESERVE20xFFCFA118 > > + > > +#define SEQ2CORE_MASK 0xF > > +#define CORE2SEQ_INT_REQ 0xF > > +#define SEQ2CORE_INT_RESP_BIT 3 > > + > > +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = > > + (void *)SOCFPGA_SDR_ADDRESS; > > +static const struct socfpga_noc_ddr_scheduler > > *socfpga_noc_ddr_scheduler_base = > > + (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS; > > +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram > > + *socfpga_noc_fw_ddr_mpu_fpga2sdram_base = > > + (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS; > > +static const struct socfpga_noc_fw_ddr_l3 > > *socfpga_noc_fw_ddr_l3_base = > > + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; > > +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base = > > + (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS; > > + > > +/* The followring are the supported configurations */ > s/followring/following > Okay. > > > > +static u32 ddr_config[] = { > > + /* Chip - Row - Bank - Column Style */ > > + /* All Types */ > > + ARRIA_DDR_CONFIG(0, 3, 10, 12), > > + ARRIA_DDR_CONFIG(0, 3, 10, 13), > > + ARRIA_DDR_CONFIG(0, 3, 10, 14), > > + ARRIA_DDR_CONFIG(0, 3, 10, 15), > > + ARRIA_DDR_CONFIG(0, 3, 10, 16), > > + ARRIA_DDR_CONFIG(0, 3, 10, 17), > > + /* LPDDR x16 */ > > +
Re: [U-Boot] [PATCH v3 11/20] arm: socfpga: Add DDR driver for Arria 10
On 10/13/2017 03:08 AM, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee> > Add DDR driver suppport for Arria 10. s/suppport/support > > Signed-off-by: Tien Fong Chee > --- > arch/arm/mach-socfpga/include/mach/sdram.h | 2 + > arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 2 + > drivers/ddr/altera/Makefile| 1 + > drivers/ddr/altera/sdram_arria10.c | 736 > + > 4 files changed, 741 insertions(+) > create mode 100644 drivers/ddr/altera/sdram_arria10.c > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h > b/arch/arm/mach-socfpga/include/mach/sdram.h > index 137e073..33f830b 100644 > --- a/arch/arm/mach-socfpga/include/mach/sdram.h > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h > @@ -10,6 +10,8 @@ > > #if defined(CONFIG_TARGET_SOCFPGA_GEN5) > #include > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > +#include > #endif > > #endif > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h > index 1d7b7c1..e7a2503 100644 > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h > @@ -8,6 +8,7 @@ > #define _SOCFPGA_SDRAM_ARRIA10_H_ > > #ifndef __ASSEMBLY__ > +int ddr_calibration_sequence(void); > > struct socfpga_ecc_hmc { > u32 ip_rev_id; > @@ -204,6 +205,7 @@ struct socfpga_io48_mmr { > u32 niosreserve1; > u32 niosreserve2; > }; > + > #endif /*__ASSEMBLY__*/ > > #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK 0x1F00 > diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile > index ac4ab85..02f8b7c 100644 > --- a/drivers/ddr/altera/Makefile > +++ b/drivers/ddr/altera/Makefile > @@ -10,4 +10,5 @@ > > ifdef CONFIG_ALTERA_SDRAM > obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o > endif > diff --git a/drivers/ddr/altera/sdram_arria10.c > b/drivers/ddr/altera/sdram_arria10.c > new file mode 100644 > index 000..be8aff3 > --- /dev/null > +++ b/drivers/ddr/altera/sdram_arria10.c > @@ -0,0 +1,736 @@ > +/* > + * Copyright (C) 2017 Intel Corporation > + * > + * SPDX-License-Identifier:GPL-2.0 > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static void sdram_mmr_init(void); > +static unsigned long long sdram_size_calc(void); Use uint64_t > + > +/* FAWBANK - Number of Bank of a given device involved in the FAW period. */ > +#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1) > + > +#define ARRIA_DDR_CONFIG(A, B, C, R) \ > + (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) > +#define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config) > +#define DDR_REG_SEQ2CORE0xFFD0507C > +#define DDR_REG_CORE2SEQ0xFFD05078 > +#define DDR_READ_LATENCY_DELAY 40 > +#define DDR_SIZE_2GB_HEX 0x8000 > +#define DDR_MAX_TRIES0x0010 > + > +#define IO48_MMR_DRAMSTS 0xFFCFA0EC > +#define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110 > +#define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114 > +#define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118 > + > +#define SEQ2CORE_MASK0xF > +#define CORE2SEQ_INT_REQ 0xF > +#define SEQ2CORE_INT_RESP_BIT3 > + > +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = > + (void *)SOCFPGA_SDR_ADDRESS; > +static const struct socfpga_noc_ddr_scheduler > *socfpga_noc_ddr_scheduler_base = > + (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS; > +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram > + *socfpga_noc_fw_ddr_mpu_fpga2sdram_base = > + (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS; > +static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base = > + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; > +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base = > + (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS; > + > +/* The followring are the supported configurations */ s/followring/following > +static u32 ddr_config[] = { > + /* Chip - Row - Bank - Column Style */ > + /* All Types */ > + ARRIA_DDR_CONFIG(0, 3, 10, 12), > + ARRIA_DDR_CONFIG(0, 3, 10, 13), > + ARRIA_DDR_CONFIG(0, 3, 10, 14), > + ARRIA_DDR_CONFIG(0, 3, 10, 15), > + ARRIA_DDR_CONFIG(0, 3, 10, 16), > + ARRIA_DDR_CONFIG(0, 3, 10, 17), > + /* LPDDR x16 */ > + ARRIA_DDR_CONFIG(0, 3, 11, 14), > + ARRIA_DDR_CONFIG(0, 3, 11, 15), > + ARRIA_DDR_CONFIG(0, 3, 11, 16), > + ARRIA_DDR_CONFIG(0, 3, 12, 15), > + /* DDR4 Only */ > + ARRIA_DDR_CONFIG(0, 4, 10, 14), > + ARRIA_DDR_CONFIG(0, 4, 10, 15), > + ARRIA_DDR_CONFIG(0, 4, 10, 16), > + ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */ > +
[U-Boot] [PATCH v3 11/20] arm: socfpga: Add DDR driver for Arria 10
From: Tien Fong CheeAdd DDR driver suppport for Arria 10. Signed-off-by: Tien Fong Chee --- arch/arm/mach-socfpga/include/mach/sdram.h | 2 + arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 2 + drivers/ddr/altera/Makefile| 1 + drivers/ddr/altera/sdram_arria10.c | 736 + 4 files changed, 741 insertions(+) create mode 100644 drivers/ddr/altera/sdram_arria10.c diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index 137e073..33f830b 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -10,6 +10,8 @@ #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include #endif #endif diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h index 1d7b7c1..e7a2503 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h @@ -8,6 +8,7 @@ #define _SOCFPGA_SDRAM_ARRIA10_H_ #ifndef __ASSEMBLY__ +int ddr_calibration_sequence(void); struct socfpga_ecc_hmc { u32 ip_rev_id; @@ -204,6 +205,7 @@ struct socfpga_io48_mmr { u32 niosreserve1; u32 niosreserve2; }; + #endif /*__ASSEMBLY__*/ #define IO48_MMR_CTRLCFG0_DB2_BURST_LENGTH_MASK0x1F00 diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index ac4ab85..02f8b7c 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -10,4 +10,5 @@ ifdef CONFIG_ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o endif diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c new file mode 100644 index 000..be8aff3 --- /dev/null +++ b/drivers/ddr/altera/sdram_arria10.c @@ -0,0 +1,736 @@ +/* + * Copyright (C) 2017 Intel Corporation + * + * SPDX-License-Identifier:GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void sdram_mmr_init(void); +static unsigned long long sdram_size_calc(void); + +/* FAWBANK - Number of Bank of a given device involved in the FAW period. */ +#define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1) + +#define ARRIA_DDR_CONFIG(A, B, C, R) \ + (((A) << 24) | ((B) << 16) | ((C) << 8) | (R)) +#define DDR_CONFIG_ELEMENTSARRAY_SIZE(ddr_config) +#define DDR_REG_SEQ2CORE0xFFD0507C +#define DDR_REG_CORE2SEQ0xFFD05078 +#define DDR_READ_LATENCY_DELAY 40 +#define DDR_SIZE_2GB_HEX 0x8000 +#define DDR_MAX_TRIES 0x0010 + +#define IO48_MMR_DRAMSTS 0xFFCFA0EC +#define IO48_MMR_NIOS2_RESERVE00xFFCFA110 +#define IO48_MMR_NIOS2_RESERVE10xFFCFA114 +#define IO48_MMR_NIOS2_RESERVE20xFFCFA118 + +#define SEQ2CORE_MASK 0xF +#define CORE2SEQ_INT_REQ 0xF +#define SEQ2CORE_INT_RESP_BIT 3 + +static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base = + (void *)SOCFPGA_SDR_ADDRESS; +static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base = + (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS; +static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram + *socfpga_noc_fw_ddr_mpu_fpga2sdram_base = + (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS; +static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base = + (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS; +static const struct socfpga_io48_mmr *socfpga_io48_mmr_base = + (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS; + +/* The followring are the supported configurations */ +static u32 ddr_config[] = { + /* Chip - Row - Bank - Column Style */ + /* All Types */ + ARRIA_DDR_CONFIG(0, 3, 10, 12), + ARRIA_DDR_CONFIG(0, 3, 10, 13), + ARRIA_DDR_CONFIG(0, 3, 10, 14), + ARRIA_DDR_CONFIG(0, 3, 10, 15), + ARRIA_DDR_CONFIG(0, 3, 10, 16), + ARRIA_DDR_CONFIG(0, 3, 10, 17), + /* LPDDR x16 */ + ARRIA_DDR_CONFIG(0, 3, 11, 14), + ARRIA_DDR_CONFIG(0, 3, 11, 15), + ARRIA_DDR_CONFIG(0, 3, 11, 16), + ARRIA_DDR_CONFIG(0, 3, 12, 15), + /* DDR4 Only */ + ARRIA_DDR_CONFIG(0, 4, 10, 14), + ARRIA_DDR_CONFIG(0, 4, 10, 15), + ARRIA_DDR_CONFIG(0, 4, 10, 16), + ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */ + /* Chip - Bank - Row - Column Style */ + ARRIA_DDR_CONFIG(1, 3, 10, 12), + ARRIA_DDR_CONFIG(1, 3, 10, 13), + ARRIA_DDR_CONFIG(1, 3, 10, 14), + ARRIA_DDR_CONFIG(1, 3, 10, 15), + ARRIA_DDR_CONFIG(1, 3, 10, 16), + ARRIA_DDR_CONFIG(1, 3, 10, 17), + ARRIA_DDR_CONFIG(1, 3, 11, 14), + ARRIA_DDR_CONFIG(1, 3, 11,