Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, 2019-11-14 at 12:57 +0530, Anup Patel wrote: > On Wed, Nov 13, 2019 at 9:13 AM Rick Chen wrote: > > Hi Lukas > > > > > Hi Rick, > > > > > > On Mon, 2019-11-11 at 15:19 +0800, Rick Chen wrote: > > > > Hi Lukas > > > > > > > > > Hi Rick, > > > > > > > > > > On Fri, 2019-11-08 at 15:27 +0800, Rick Chen wrote: > > > > > > Hi Atish > > > > > > > > > > > > > Hi Atish > > > > > > > > > > > > > > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote: > > > > > > > > > Hi Anup & Lukas > > > > > > > > > > > > > > > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > > > > > > > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > > > > > > > > > wrote: > > > > > > > > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > > > > > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel < > > > > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen < > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen < > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > > > > > > > > > > > > > > < > > > > > > > > > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick > > > > > > > > > > > > > > > > > > > > Chen < > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick > > > > > > > > > > > > > > > > > > > > > > Chen < > > > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 > > > > > > > > > > > > > > > > > > > > > > > > > PM Anup > > > > > > > > > > > > > > > > > > > > > > > > > Patel > > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > > 6:30 AM > > > > > > > > > > > > > > > > > > > > > > > > > > Alan Kao > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. > > > > > > > > > > > > > > > > > > > > > > > > > > > Comments > > > > > > > > > > > > > > > > > > > > > > > > > > > below. > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > Meng wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > > > > 10:50 > > > > > > > > > > > > > > > > > > > > > > > > > > > > AM Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes < > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > due to > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > hart 0 always > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > will be > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Wed, Nov 13, 2019 at 9:13 AM Rick Chen wrote: > > Hi Lukas > > > > > Hi Rick, > > > > On Mon, 2019-11-11 at 15:19 +0800, Rick Chen wrote: > > > Hi Lukas > > > > > > > Hi Rick, > > > > > > > > On Fri, 2019-11-08 at 15:27 +0800, Rick Chen wrote: > > > > > Hi Atish > > > > > > > > > > > Hi Atish > > > > > > > > > > > > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote: > > > > > > > > Hi Anup & Lukas > > > > > > > > > > > > > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > > > > > > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > > > > > > > > wrote: > > > > > > > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > > > > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel < > > > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen < > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen < > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel < > > > > > > > > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > > > > > > > > > > > > > < > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick > > > > > > > > > > > > > > > > > > > > > Chen < > > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM > > > > > > > > > > > > > > > > > > > > > > > > Anup > > > > > > > > > > > > > > > > > > > > > > > > Patel > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 > > > > > > > > > > > > > > > > > > > > > > > > > AM > > > > > > > > > > > > > > > > > > > > > > > > > Alan Kao > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. > > > > > > > > > > > > > > > > > > > > > > > > > > Comments > > > > > > > > > > > > > > > > > > > > > > > > > > below. > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin Meng > > > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > > > 10:50 > > > > > > > > > > > > > > > > > > > > > > > > > > > AM Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > at > > > > > > > > > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes < > > > > > > > > > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > due to > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > hart 0 always will > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > be > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > main > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > hart > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > coincidentally. When > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Lukas > > Hi Rick, > > On Mon, 2019-11-11 at 15:19 +0800, Rick Chen wrote: > > Hi Lukas > > > > > Hi Rick, > > > > > > On Fri, 2019-11-08 at 15:27 +0800, Rick Chen wrote: > > > > Hi Atish > > > > > > > > > Hi Atish > > > > > > > > > > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote: > > > > > > > Hi Anup & Lukas > > > > > > > > > > > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > > > > > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > > > > > > > wrote: > > > > > > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > > > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel < > > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen < > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen < > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel < > > > > > > > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen < > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick > > > > > > > > > > > > > > > > > > > > Chen < > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM > > > > > > > > > > > > > > > > > > > > > > > Anup > > > > > > > > > > > > > > > > > > > > > > > Patel wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM > > > > > > > > > > > > > > > > > > > > > > > > Alan Kao > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. > > > > > > > > > > > > > > > > > > > > > > > > > Comments > > > > > > > > > > > > > > > > > > > > > > > > > below. > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin Meng > > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > > 10:50 > > > > > > > > > > > > > > > > > > > > > > > > > > AM Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes < > > > > > > > > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due > > > > > > > > > > > > > > > > > > > > > > > > > > > > > to > > > > > > > > > > > > > > > > > > > > > > > > > > > > > hart 0 always will be > > > > > > > > > > > > > > > > > > > > > > > > > > > > > main > > > > > > > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > When > > > > > > > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I > > > > > > > > > > > > > > > > > > > > > > > > > > > > > try > > > > > > > > > > > > > > > > > > > > > > > > > > > > > to > > > > > > > > > > > > > > > > > > > > > > > > > > > > > force other harts to > > > > > > > > > > > > > > > > > > > > > > > > > > > > > be > > > > > > > > > > > > > > > > > > > > > > > > > > > > > main hart. And it > > > > > > > > > > > > > > > > > > > > > > > > > > > > > will go > > > > > > > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI > > > > > > > > > > > > > > > > > > > > > > > > > > > > > flow. So fix it. > > > > > > > > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Rick, On Mon, 2019-11-11 at 15:19 +0800, Rick Chen wrote: > Hi Lukas > > > Hi Rick, > > > > On Fri, 2019-11-08 at 15:27 +0800, Rick Chen wrote: > > > Hi Atish > > > > > > > Hi Atish > > > > > > > > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote: > > > > > > Hi Anup & Lukas > > > > > > > > > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > > > > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > > > > > > wrote: > > > > > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel < > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen < > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen < > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel < > > > > > > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen < > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen < > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup > > > > > > > > > > > > > > > > > > > > > > Patel wrote: > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM > > > > > > > > > > > > > > > > > > > > > > > Alan Kao > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. > > > > > > > > > > > > > > > > > > > > > > > > Comments > > > > > > > > > > > > > > > > > > > > > > > > below. > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin Meng > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 > > > > > > > > > > > > > > > > > > > > > > > > > AM Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes < > > > > > > > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to > > > > > > > > > > > > > > > > > > > > > > > > > > > > hart 0 always will be > > > > > > > > > > > > > > > > > > > > > > > > > > > > main > > > > > > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. > > > > > > > > > > > > > > > > > > > > > > > > > > > > When > > > > > > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try > > > > > > > > > > > > > > > > > > > > > > > > > > > > to > > > > > > > > > > > > > > > > > > > > > > > > > > > > force other harts to be > > > > > > > > > > > > > > > > > > > > > > > > > > > > main hart. And it will > > > > > > > > > > > > > > > > > > > > > > > > > > > > go > > > > > > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI > > > > > > > > > > > > > > > > > > > > > > > > > > > > flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit > > > > > > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1 > > > > > > > > > > > > > > > > > > > > > > > > > > > fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. > > > > > > > > > > > > > > > > > > > > > > > > > > But > > > > > > > > > > > > > > > > > > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Lukas > > Hi Rick, > > On Fri, 2019-11-08 at 15:27 +0800, Rick Chen wrote: > > Hi Atish > > > > > Hi Atish > > > > > > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote: > > > > > Hi Anup & Lukas > > > > > > > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > > > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > > > > > wrote: > > > > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > > > > > wrote: > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel < > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen < > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen < > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel < > > > > > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen < > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen < > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup > > > > > > > > > > > > > > > > > > > > > Patel wrote: > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM > > > > > > > > > > > > > > > > > > > > > > Alan Kao > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments > > > > > > > > > > > > > > > > > > > > > > > below. > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin Meng wrote: > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 > > > > > > > > > > > > > > > > > > > > > > > > AM Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes < > > > > > > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to > > > > > > > > > > > > > > > > > > > > > > > > > > > hart 0 always will be > > > > > > > > > > > > > > > > > > > > > > > > > > > main > > > > > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When > > > > > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try > > > > > > > > > > > > > > > > > > > > > > > > > > > to > > > > > > > > > > > > > > > > > > > > > > > > > > > force other harts to be > > > > > > > > > > > > > > > > > > > > > > > > > > > main hart. And it will go > > > > > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI > > > > > > > > > > > > > > > > > > > > > > > > > > > flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit > > > > > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1 > > > > > > > > > > > > > > > > > > > > > > > > > > fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But > > > > > > > > > > > > > > > > > > > > > > > > > they will cause one negative > > > > > > > > > > > > > > > > > > > > > > > > > result > > > > > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi > > > > > > > > > > > > > > > > > > > > > > > > > to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart > > > > > > > > > > > > > > > > > > > > > > > > > > > can be main hart in U- > > > > > > > > > > > > > > > > > > > > > > > > > > > Boot SPL > > > > > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Fri, Nov 8, 2019 at 6:53 AM Rick Chen wrote: > > Hi Anup > > > > > On Thu, Nov 7, 2019 at 5:11 PM Rick Chen wrote: > > > > > > Hi Anup & Lukas > > > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > > > > > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > > > wrote: > > > > > > > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > > > wrote: > > > > > > > Hi Anup > > > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel > > > > > > > > wrote: > > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen > > > > > > > > > wrote: > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen > > > > > > > > > > > wrote: > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup > > > > > > > > > > > > > > > > > > > Patel wrote: > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan > > > > > > > > > > > > > > > > > > > > Kao wrote: > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments > > > > > > > > > > > > > > > > > > > > > below. > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM > > > > > > > > > > > > > > > > > > > > > +0800, Bin Meng wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM > > > > > > > > > > > > > > > > > > > > > > Rick Chen > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM > > > > > > > > > > > > > > > > > > > > > > > > Andes > > > > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart > > > > > > > > > > > > > > > > > > > > > > > > > 0 always will be main > > > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When > > > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try to > > > > > > > > > > > > > > > > > > > > > > > > > force other harts to be main > > > > > > > > > > > > > > > > > > > > > > > > > hart. And it will go > > > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So > > > > > > > > > > > > > > > > > > > > > > > > > fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit > > > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But > > > > > > > > > > > > > > > > > > > > > > > they will cause one negative > > > > > > > > > > > > > > > > > > > > > > > result > > > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi to > > > > > > > > > > > > > > > > > > > > > > > other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can > > > > > > > > > > > > > > > > > > > > > > > > > be main hart in U-Boot SPL > > > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it still > > > > > > > > > > > > > > > > > > > > > > > > > fail somewhere. After dig in > > > > > > > > > > > > > > > > > > > > > > > > > and found there is an > > > > > > > > > > > > > > > > > > > > > > > > > assumption that hart 0 shall > > > > > > > > > > > > > > > > > > > > > > > > > be > > > > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a > > > > > > > > > > > > > > > > > > > > > > > > bug in OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. > > > > > > > > > > > > > > > > > > > > > > > Maybe it is a compatible issue. > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Rick, On Fri, 2019-11-08 at 15:27 +0800, Rick Chen wrote: > Hi Atish > > > Hi Atish > > > > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote: > > > > Hi Anup & Lukas > > > > > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > > > > wrote: > > > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > > > > wrote: > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel < > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen < > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen < > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel < > > > > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen < > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen < > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup > > > > > > > > > > > > > > > > > > > > Patel wrote: > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM > > > > > > > > > > > > > > > > > > > > > Alan Kao > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments > > > > > > > > > > > > > > > > > > > > > > below. > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin Meng wrote: > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 > > > > > > > > > > > > > > > > > > > > > > > AM Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes < > > > > > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to > > > > > > > > > > > > > > > > > > > > > > > > > > hart 0 always will be > > > > > > > > > > > > > > > > > > > > > > > > > > main > > > > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When > > > > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try > > > > > > > > > > > > > > > > > > > > > > > > > > to > > > > > > > > > > > > > > > > > > > > > > > > > > force other harts to be > > > > > > > > > > > > > > > > > > > > > > > > > > main hart. And it will go > > > > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI > > > > > > > > > > > > > > > > > > > > > > > > > > flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit > > > > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1 > > > > > > > > > > > > > > > > > > > > > > > > > fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But > > > > > > > > > > > > > > > > > > > > > > > > they will cause one negative > > > > > > > > > > > > > > > > > > > > > > > > result > > > > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi > > > > > > > > > > > > > > > > > > > > > > > > to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart > > > > > > > > > > > > > > > > > > > > > > > > > > can be main hart in U- > > > > > > > > > > > > > > > > > > > > > > > > > > Boot SPL > > > > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it > > > > > > > > > > > > > > > > > > > > > > > > > > still fail somewhere. > > > > > > > > > > > > > > > > > > > > > > > > > > After dig in > > > > > > > > > > > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Atish > > Hi Atish > > > > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote: > > > Hi Anup & Lukas > > > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > > > wrote: > > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > > > wrote: > > > > > > > Hi Anup > > > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel < > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen < > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen < > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel < > > > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen < > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen < > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup > > > > > > > > > > > > > > > > > > > Patel wrote: > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM > > > > > > > > > > > > > > > > > > > > Alan Kao > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments > > > > > > > > > > > > > > > > > > > > > below. > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin Meng wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 > > > > > > > > > > > > > > > > > > > > > > AM Rick Chen < > > > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at > > > > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes < > > > > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to > > > > > > > > > > > > > > > > > > > > > > > > > hart 0 always will be > > > > > > > > > > > > > > > > > > > > > > > > > main > > > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When > > > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try > > > > > > > > > > > > > > > > > > > > > > > > > to > > > > > > > > > > > > > > > > > > > > > > > > > force other harts to be > > > > > > > > > > > > > > > > > > > > > > > > > main hart. And it will go > > > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI > > > > > > > > > > > > > > > > > > > > > > > > > flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit > > > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1 > > > > > > > > > > > > > > > > > > > > > > > > fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But > > > > > > > > > > > > > > > > > > > > > > > they will cause one negative > > > > > > > > > > > > > > > > > > > > > > > result > > > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi > > > > > > > > > > > > > > > > > > > > > > > to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart > > > > > > > > > > > > > > > > > > > > > > > > > can be main hart in U- > > > > > > > > > > > > > > > > > > > > > > > > > Boot SPL > > > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it > > > > > > > > > > > > > > > > > > > > > > > > > still fail somewhere. > > > > > > > > > > > > > > > > > > > > > > > > > After dig in > > > > > > > > > > > > > > > > > > > > > > > > > and found there is an > > > > > > > > > > > > > > > > > > > > > > > > > assumption that hart 0 > > > > > > > > > > > > > > > > > > > > > > > > > shall be > > > > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Anup > > On Thu, Nov 7, 2019 at 5:11 PM Rick Chen wrote: > > > > Hi Anup & Lukas > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > > > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > > wrote: > > > > > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > > wrote: > > > > > > Hi Anup > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel > > > > > > > wrote: > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen > > > > > > > > wrote: > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen > > > > > > > > > > wrote: > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > > > > > > > wrote: > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM > > > > > > > > > > > > > > > > > > > > +0800, Bin Meng wrote: > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick > > > > > > > > > > > > > > > > > > > > > Chen wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM > > > > > > > > > > > > > > > > > > > > > > > Andes wrote: > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 > > > > > > > > > > > > > > > > > > > > > > > > always will be main > > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When > > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try to > > > > > > > > > > > > > > > > > > > > > > > > force other harts to be main > > > > > > > > > > > > > > > > > > > > > > > > hart. And it will go > > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So > > > > > > > > > > > > > > > > > > > > > > > > fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit > > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they > > > > > > > > > > > > > > > > > > > > > > will cause one negative result > > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi to > > > > > > > > > > > > > > > > > > > > > > other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can > > > > > > > > > > > > > > > > > > > > > > > > be main hart in U-Boot SPL > > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it still > > > > > > > > > > > > > > > > > > > > > > > > fail somewhere. After dig in > > > > > > > > > > > > > > > > > > > > > > > > and found there is an > > > > > > > > > > > > > > > > > > > > > > > > assumption that hart 0 shall be > > > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug > > > > > > > > > > > > > > > > > > > > > > > in OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe > > > > > > > > > > > > > > > > > > > > > > it is a compatible issue. > > > > > > > > > > > > > > > > > > > > > > There is a limitation that only > > > > > > > > > > > > > > > > > > > > > > hart 0 can be main hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such > > > > > > > > > > > > > > > > > > > > > limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Atish > > On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote: > > Hi Anup & Lukas > > > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > > wrote: > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > > wrote: > > > > > > Hi Anup > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel < > > > > > > > a...@brainfault.org> wrote: > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen < > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen < > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel < > > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen < > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen < > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup > > > > > > > > > > > > > > > > > > Patel wrote: > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM > > > > > > > > > > > > > > > > > > > Alan Kao > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments > > > > > > > > > > > > > > > > > > > > below. > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin Meng wrote: > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 > > > > > > > > > > > > > > > > > > > > > AM Rick Chen < > > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at > > > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes < > > > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to > > > > > > > > > > > > > > > > > > > > > > > > hart 0 always will be > > > > > > > > > > > > > > > > > > > > > > > > main > > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When > > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try > > > > > > > > > > > > > > > > > > > > > > > > to > > > > > > > > > > > > > > > > > > > > > > > > force other harts to be > > > > > > > > > > > > > > > > > > > > > > > > main hart. And it will go > > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI > > > > > > > > > > > > > > > > > > > > > > > > flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit > > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1 > > > > > > > > > > > > > > > > > > > > > > > fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But > > > > > > > > > > > > > > > > > > > > > > they will cause one negative > > > > > > > > > > > > > > > > > > > > > > result > > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi > > > > > > > > > > > > > > > > > > > > > > to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart > > > > > > > > > > > > > > > > > > > > > > > > can be main hart in U- > > > > > > > > > > > > > > > > > > > > > > > > Boot SPL > > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it > > > > > > > > > > > > > > > > > > > > > > > > still fail somewhere. > > > > > > > > > > > > > > > > > > > > > > > > After dig in > > > > > > > > > > > > > > > > > > > > > > > > and found there is an > > > > > > > > > > > > > > > > > > > > > > > > assumption that hart 0 > > > > > > > > > > > > > > > > > > > > > > > > shall be > > > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is > > > > > > > > > > > > > > > > > > > > > > > a bug in OpenSBI too? > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, 2019-11-07 at 19:41 +0800, Rick Chen wrote: > Hi Anup & Lukas > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > wrote: > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > wrote: > > > > > Hi Anup > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel < > > > > > > a...@brainfault.org> wrote: > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen < > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen < > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel < > > > > > > > > > > > a...@brainfault.org> wrote: > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen < > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen < > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup > > > > > > > > > > > > > > > > > Patel wrote: > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM > > > > > > > > > > > > > > > > > > Alan Kao > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments > > > > > > > > > > > > > > > > > > > below. > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at > > > > > > > > > > > > > > > > > > > 06:38:00PM +0800, Bin Meng wrote: > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 > > > > > > > > > > > > > > > > > > > > AM Rick Chen < > > > > > > > > > > > > > > > > > > > > rickche...@gmail.com> wrote: > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at > > > > > > > > > > > > > > > > > > > > > > 2:18 PM Andes < > > > > > > > > > > > > > > > > > > > > > > ub...@andestech.com> wrote: > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen < > > > > > > > > > > > > > > > > > > > > > > > r...@andestech.com> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to > > > > > > > > > > > > > > > > > > > > > > > hart 0 always will be > > > > > > > > > > > > > > > > > > > > > > > main > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try > > > > > > > > > > > > > > > > > > > > > > > to > > > > > > > > > > > > > > > > > > > > > > > force other harts to be > > > > > > > > > > > > > > > > > > > > > > > main hart. And it will go > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI > > > > > > > > > > > > > > > > > > > > > > > flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1 > > > > > > > > > > > > > > > > > > > > > > fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But > > > > > > > > > > > > > > > > > > > > > they will cause one negative > > > > > > > > > > > > > > > > > > > > > result > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi > > > > > > > > > > > > > > > > > > > > > to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart > > > > > > > > > > > > > > > > > > > > > > > can be main hart in U- > > > > > > > > > > > > > > > > > > > > > > > Boot SPL > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it > > > > > > > > > > > > > > > > > > > > > > > still fail somewhere. > > > > > > > > > > > > > > > > > > > > > > > After dig in > > > > > > > > > > > > > > > > > > > > > > > and found there is an > > > > > > > > > > > > > > > > > > > > > > > assumption that hart 0 > > > > > > > > > > > > > > > > > > > > > > > shall be > > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is > > > > > > > > > > > > > > > > > > > > > > a bug in OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. > > > > > > > > > > > > > > > > > > > > > Maybe it is a compatible > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, 2019-11-07 at 17:57 +0530, Anup Patel wrote: > On Thu, Nov 7, 2019 at 5:14 PM Auer, Lukas > wrote: > > On Thu, 2019-11-07 at 16:14 +0530, Anup Patel wrote: > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > > wrote: > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen > > > > > wrote: > > > > > > Hi Anup > > > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel > > > > > > > wrote: > > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen > > > > > > > > wrote: > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen > > > > > > > > > > wrote: > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > > > > > > > wrote: > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM > > > > > > > > > > > > > > > > > > > > +0800, Bin Meng wrote: > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick > > > > > > > > > > > > > > > > > > > > > Chen wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM > > > > > > > > > > > > > > > > > > > > > > > Andes wrote: > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 > > > > > > > > > > > > > > > > > > > > > > > > always will be main > > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When > > > > > > > > > > > > > > > > > > > > > > > > develop SPL flow, I try to > > > > > > > > > > > > > > > > > > > > > > > > force other harts to be main > > > > > > > > > > > > > > > > > > > > > > > > hart. And it will go > > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So > > > > > > > > > > > > > > > > > > > > > > > > fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit > > > > > > > > > > > > > > > > > > > > > > > contain 2 fixes, or just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they > > > > > > > > > > > > > > > > > > > > > > will cause one negative result > > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi to > > > > > > > > > > > > > > > > > > > > > > other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can > > > > > > > > > > > > > > > > > > > > > > > > be main hart in U-Boot SPL > > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it still > > > > > > > > > > > > > > > > > > > > > > > > fail somewhere. After dig in > > > > > > > > > > > > > > > > > > > > > > > > and found there is an > > > > > > > > > > > > > > > > > > > > > > > > assumption that hart 0 shall be > > > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug > > > > > > > > > > > > > > > > > > > > > > > in OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe > > > > > > > > > > > > > > > > > > > > > > it is a compatible issue. > > > > > > > > > > > > > > > > > > > > > > There is a limitation that only > > > > > > > > > > > > > > > > > > > > > > hart 0 can be main hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such > > > > > > > > > > > > > > > > > > > > > limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, Nov 7, 2019 at 5:14 PM Auer, Lukas wrote: > > On Thu, 2019-11-07 at 16:14 +0530, Anup Patel wrote: > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > wrote: > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote: > > > > > Hi Anup > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel > > > > > > wrote: > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen > > > > > > > wrote: > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen > > > > > > > > > wrote: > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > > > > > > wrote: > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > > > > > > wrote: > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, > > > > > > > > > > > > > > > > > > > Bin Meng wrote: > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick > > > > > > > > > > > > > > > > > > > > Chen wrote: > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM > > > > > > > > > > > > > > > > > > > > > > Andes wrote: > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 > > > > > > > > > > > > > > > > > > > > > > > always will be main > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When develop > > > > > > > > > > > > > > > > > > > > > > > SPL flow, I try to > > > > > > > > > > > > > > > > > > > > > > > force other harts to be main > > > > > > > > > > > > > > > > > > > > > > > hart. And it will go > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So fix > > > > > > > > > > > > > > > > > > > > > > > it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain > > > > > > > > > > > > > > > > > > > > > > 2 fixes, or just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they > > > > > > > > > > > > > > > > > > > > > will cause one negative result > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi to > > > > > > > > > > > > > > > > > > > > > other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be > > > > > > > > > > > > > > > > > > > > > > > main hart in U-Boot SPL > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it still fail > > > > > > > > > > > > > > > > > > > > > > > somewhere. After dig in > > > > > > > > > > > > > > > > > > > > > > > and found there is an assumption > > > > > > > > > > > > > > > > > > > > > > > that hart 0 shall be > > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in > > > > > > > > > > > > > > > > > > > > > > OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe > > > > > > > > > > > > > > > > > > > > > it is a compatible issue. > > > > > > > > > > > > > > > > > > > > > There is a limitation that only hart > > > > > > > > > > > > > > > > > > > > > 0 can be main hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such > > > > > > > > > > > > > > > > > > > > limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, Nov 7, 2019 at 5:11 PM Rick Chen wrote: > > Hi Anup & Lukas > > Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > > wrote: > > > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote: > > > > > Hi Anup > > > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel > > > > > > wrote: > > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen > > > > > > > wrote: > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen > > > > > > > > > wrote: > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > > > > > > wrote: > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > > > > > > wrote: > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, > > > > > > > > > > > > > > > > > > > Bin Meng wrote: > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick > > > > > > > > > > > > > > > > > > > > Chen wrote: > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM > > > > > > > > > > > > > > > > > > > > > > Andes wrote: > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 > > > > > > > > > > > > > > > > > > > > > > > always will be main > > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When develop > > > > > > > > > > > > > > > > > > > > > > > SPL flow, I try to > > > > > > > > > > > > > > > > > > > > > > > force other harts to be main > > > > > > > > > > > > > > > > > > > > > > > hart. And it will go > > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So fix > > > > > > > > > > > > > > > > > > > > > > > it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain > > > > > > > > > > > > > > > > > > > > > > 2 fixes, or just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they > > > > > > > > > > > > > > > > > > > > > will cause one negative result > > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi to > > > > > > > > > > > > > > > > > > > > > other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be > > > > > > > > > > > > > > > > > > > > > > > main hart in U-Boot SPL > > > > > > > > > > > > > > > > > > > > > > > theoretically, but it still fail > > > > > > > > > > > > > > > > > > > > > > > somewhere. After dig in > > > > > > > > > > > > > > > > > > > > > > > and found there is an assumption > > > > > > > > > > > > > > > > > > > > > > > that hart 0 shall be > > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in > > > > > > > > > > > > > > > > > > > > > > OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe > > > > > > > > > > > > > > > > > > > > > it is a compatible issue. > > > > > > > > > > > > > > > > > > > > > There is a limitation that only hart > > > > > > > > > > > > > > > > > > > > > 0 can be main hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such > > > > > > > > > > > > > > > > > > > > limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, 2019-11-07 at 16:14 +0530, Anup Patel wrote: > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > wrote: > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote: > > > > Hi Anup > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel > > > > > wrote: > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen > > > > > > wrote: > > > > > > > Hi Anup > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen > > > > > > > > wrote: > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > > > > > wrote: > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > > > > > wrote: > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, > > > > > > > > > > > > > > > > > > Bin Meng wrote: > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick > > > > > > > > > > > > > > > > > > > Chen wrote: > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 > > > > > > > > > > > > > > > > > > > > > > always will be main > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When develop > > > > > > > > > > > > > > > > > > > > > > SPL flow, I try to > > > > > > > > > > > > > > > > > > > > > > force other harts to be main hart. > > > > > > > > > > > > > > > > > > > > > > And it will go > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So fix > > > > > > > > > > > > > > > > > > > > > > it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 > > > > > > > > > > > > > > > > > > > > > fixes, or just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will > > > > > > > > > > > > > > > > > > > > cause one negative result > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi to other > > > > > > > > > > > > > > > > > > > > harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be > > > > > > > > > > > > > > > > > > > > > > main hart in U-Boot SPL > > > > > > > > > > > > > > > > > > > > > > theoretically, but it still fail > > > > > > > > > > > > > > > > > > > > > > somewhere. After dig in > > > > > > > > > > > > > > > > > > > > > > and found there is an assumption > > > > > > > > > > > > > > > > > > > > > > that hart 0 shall be > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in > > > > > > > > > > > > > > > > > > > > > OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it > > > > > > > > > > > > > > > > > > > > is a compatible issue. > > > > > > > > > > > > > > > > > > > > There is a limitation that only hart 0 > > > > > > > > > > > > > > > > > > > > can be main hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the > > > > > > > > > > > > > > > > > > initialization are the > > > > > > > > > > > > > > > > > > 1. get hart ID. > > > > > > > > > > > > > > > > > > 2. determine which route to take based on > > > > > > > > > > > > > > > > > > their ID respectively. > > > > > > > > > > > > > > > > > > > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Anup & Lukas Anup Patel 於 2019年11月7日 週四 下午6:44寫道： > > On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas > wrote: > > > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote: > > > > Hi Anup > > > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel > > > > > wrote: > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen > > > > > > wrote: > > > > > > > Hi Anup > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen > > > > > > > > wrote: > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > > > > > wrote: > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > > > > > wrote: > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, > > > > > > > > > > > > > > > > > > Bin Meng wrote: > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick > > > > > > > > > > > > > > > > > > > Chen wrote: > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 > > > > > > > > > > > > > > > > > > > > > > always will be main > > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When develop > > > > > > > > > > > > > > > > > > > > > > SPL flow, I try to > > > > > > > > > > > > > > > > > > > > > > force other harts to be main hart. > > > > > > > > > > > > > > > > > > > > > > And it will go > > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So fix > > > > > > > > > > > > > > > > > > > > > > it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 > > > > > > > > > > > > > > > > > > > > > fixes, or just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will > > > > > > > > > > > > > > > > > > > > cause one negative result > > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi to other > > > > > > > > > > > > > > > > > > > > harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be > > > > > > > > > > > > > > > > > > > > > > main hart in U-Boot SPL > > > > > > > > > > > > > > > > > > > > > > theoretically, but it still fail > > > > > > > > > > > > > > > > > > > > > > somewhere. After dig in > > > > > > > > > > > > > > > > > > > > > > and found there is an assumption > > > > > > > > > > > > > > > > > > > > > > that hart 0 shall be > > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in > > > > > > > > > > > > > > > > > > > > > OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it > > > > > > > > > > > > > > > > > > > > is a compatible issue. > > > > > > > > > > > > > > > > > > > > There is a limitation that only hart 0 > > > > > > > > > > > > > > > > > > > > can be main hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the > > > > > > > > > > > > > > > > > > initialization are the > > > > > > > > > > > > > > > > > > 1. get hart ID. > > > > > > > > > > > > > > > > > > 2. determine which route to take based on > > > > > > > > > > > > > > > > > > their ID respectively. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, Nov 7, 2019 at 3:11 PM Auer, Lukas wrote: > > On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote: > > > Hi Anup > > > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote: > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote: > > > > > > Hi Anup > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen > > > > > > > wrote: > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > > > > wrote: > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > > > > wrote: > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > > > > > wrote: > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin > > > > > > > > > > > > > > > > > Meng wrote: > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 > > > > > > > > > > > > > > > > > > > > > always will be main > > > > > > > > > > > > > > > > > > > > > hart coincidentally. When develop SPL > > > > > > > > > > > > > > > > > > > > > flow, I try to > > > > > > > > > > > > > > > > > > > > > force other harts to be main hart. > > > > > > > > > > > > > > > > > > > > > And it will go > > > > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 > > > > > > > > > > > > > > > > > > > > fixes, or just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will > > > > > > > > > > > > > > > > > > > cause one negative result > > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi to other > > > > > > > > > > > > > > > > > > > harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main > > > > > > > > > > > > > > > > > > > > > hart in U-Boot SPL > > > > > > > > > > > > > > > > > > > > > theoretically, but it still fail > > > > > > > > > > > > > > > > > > > > > somewhere. After dig in > > > > > > > > > > > > > > > > > > > > > and found there is an assumption that > > > > > > > > > > > > > > > > > > > > > hart 0 shall be > > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in > > > > > > > > > > > > > > > > > > > > OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is > > > > > > > > > > > > > > > > > > > a compatible issue. > > > > > > > > > > > > > > > > > > > There is a limitation that only hart 0 > > > > > > > > > > > > > > > > > > > can be main hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the > > > > > > > > > > > > > > > > > initialization are the > > > > > > > > > > > > > > > > > 1. get hart ID. > > > > > > > > > > > > > > > > > 2. determine which route to take based on > > > > > > > > > > > > > > > > > their ID respectively. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So, I do think OpenSBI has this signature, if > > > > > > > > > > > > > > > > > you are not willing to call it > > > > > > > > > > > > > > > > > a limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > This dependency on hart id #0 was not there > > > > > > > > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, 2019-11-07 at 11:48 +0530, Anup Patel wrote: > On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote: > > Hi Anup > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote: > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote: > > > > > Hi Anup > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen > > > > > > wrote: > > > > > > > Hi Anup > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > > > wrote: > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > > > wrote: > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > > > > wrote: > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin > > > > > > > > > > > > > > > > Meng wrote: > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always > > > > > > > > > > > > > > > > > > > > will be main > > > > > > > > > > > > > > > > > > > > hart coincidentally. When develop SPL > > > > > > > > > > > > > > > > > > > > flow, I try to > > > > > > > > > > > > > > > > > > > > force other harts to be main hart. And > > > > > > > > > > > > > > > > > > > > it will go > > > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 > > > > > > > > > > > > > > > > > > > fixes, or just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will > > > > > > > > > > > > > > > > > > cause one negative result > > > > > > > > > > > > > > > > > > that only hart 0 can send ipi to other > > > > > > > > > > > > > > > > > > harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main > > > > > > > > > > > > > > > > > > > > hart in U-Boot SPL > > > > > > > > > > > > > > > > > > > > theoretically, but it still fail > > > > > > > > > > > > > > > > > > > > somewhere. After dig in > > > > > > > > > > > > > > > > > > > > and found there is an assumption that > > > > > > > > > > > > > > > > > > > > hart 0 shall be > > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in > > > > > > > > > > > > > > > > > > > OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a > > > > > > > > > > > > > > > > > > compatible issue. > > > > > > > > > > > > > > > > > > There is a limitation that only hart 0 can > > > > > > > > > > > > > > > > > > be main hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the > > > > > > > > > > > > > > > > initialization are the > > > > > > > > > > > > > > > > 1. get hart ID. > > > > > > > > > > > > > > > > 2. determine which route to take based on their > > > > > > > > > > > > > > > > ID respectively. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So, I do think OpenSBI has this signature, if > > > > > > > > > > > > > > > > you are not willing to call it > > > > > > > > > > > > > > > > a limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > This dependency on hart id #0 was not there until > > > > > > > > > > > > > > > we added self-relocation > > > > > > > > > > > > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I will try to fix this in OpenSBI but we might > > > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, Nov 7, 2019 at 11:40 AM Rick Chen wrote: > > Hi Anup > > > > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote: > > > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote: > > > > > > > > Hi Anup > > > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote: > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > > wrote: > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin > > > > > > > > > > > > > > > Meng wrote: > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always > > > > > > > > > > > > > > > > > > > will be main > > > > > > > > > > > > > > > > > > > hart coincidentally. When develop SPL > > > > > > > > > > > > > > > > > > > flow, I try to > > > > > > > > > > > > > > > > > > > force other harts to be main hart. And it > > > > > > > > > > > > > > > > > > > will go > > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, > > > > > > > > > > > > > > > > > > or just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will cause > > > > > > > > > > > > > > > > > one negative result > > > > > > > > > > > > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main > > > > > > > > > > > > > > > > > > > hart in U-Boot SPL > > > > > > > > > > > > > > > > > > > theoretically, but it still fail > > > > > > > > > > > > > > > > > > > somewhere. After dig in > > > > > > > > > > > > > > > > > > > and found there is an assumption that > > > > > > > > > > > > > > > > > > > hart 0 shall be > > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI > > > > > > > > > > > > > > > > > > too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a > > > > > > > > > > > > > > > > > compatible issue. > > > > > > > > > > > > > > > > > There is a limitation that only hart 0 can be > > > > > > > > > > > > > > > > > main hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the > > > > > > > > > > > > > > > initialization are the > > > > > > > > > > > > > > > 1. get hart ID. > > > > > > > > > > > > > > > 2. determine which route to take based on their > > > > > > > > > > > > > > > ID respectively. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So, I do think OpenSBI has this signature, if you > > > > > > > > > > > > > > > are not willing to call it > > > > > > > > > > > > > > > a limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > This dependency on hart id #0 was not there until > > > > > > > > > > > > > > we added self-relocation > > > > > > > > > > > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > > > > > > > > > > > > > > > > > > > > > I will try to
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Anup > > On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote: > > > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote: > > > > > > Hi Anup > > > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote: > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel > > > > > > wrote: > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always will > > > > > > > > > > > > > > > > > > be main > > > > > > > > > > > > > > > > > > hart coincidentally. When develop SPL flow, > > > > > > > > > > > > > > > > > > I try to > > > > > > > > > > > > > > > > > > force other harts to be main hart. And it > > > > > > > > > > > > > > > > > > will go > > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, > > > > > > > > > > > > > > > > > or just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will cause > > > > > > > > > > > > > > > > one negative result > > > > > > > > > > > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main hart > > > > > > > > > > > > > > > > > > in U-Boot SPL > > > > > > > > > > > > > > > > > > theoretically, but it still fail somewhere. > > > > > > > > > > > > > > > > > > After dig in > > > > > > > > > > > > > > > > > > and found there is an assumption that hart > > > > > > > > > > > > > > > > > > 0 shall be > > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI > > > > > > > > > > > > > > > > > too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a > > > > > > > > > > > > > > > > compatible issue. > > > > > > > > > > > > > > > > There is a limitation that only hart 0 can be > > > > > > > > > > > > > > > > main hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the > > > > > > > > > > > > > > initialization are the > > > > > > > > > > > > > > 1. get hart ID. > > > > > > > > > > > > > > 2. determine which route to take based on their ID > > > > > > > > > > > > > > respectively. > > > > > > > > > > > > > > > > > > > > > > > > > > > > So, I do think OpenSBI has this signature, if you > > > > > > > > > > > > > > are not willing to call it > > > > > > > > > > > > > > a limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > This dependency on hart id #0 was not there until we > > > > > > > > > > > > > added self-relocation > > > > > > > > > > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > > > > > > > > > > > > > > > > > > > I will try to fix this in OpenSBI but we might end-up > > > > > > > > > > > > > having boot_lottery. > > > > > > > > > > > > > > > > > > > > > > > > I have send a patch to fix this OpenSBI: > > > > > > > > > > > > "[PATCH] firmware: Introduce relocation lottery" > > > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, Nov 7, 2019 at 10:45 AM Anup Patel wrote: > > On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote: > > > > Hi Anup > > > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote: > > > > > > > > Hi Anup > > > > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote: > > > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > > wrote: > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always will > > > > > > > > > > > > > > > > > be main > > > > > > > > > > > > > > > > > hart coincidentally. When develop SPL flow, I > > > > > > > > > > > > > > > > > try to > > > > > > > > > > > > > > > > > force other harts to be main hart. And it > > > > > > > > > > > > > > > > > will go > > > > > > > > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, or > > > > > > > > > > > > > > > > just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will cause one > > > > > > > > > > > > > > > negative result > > > > > > > > > > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main hart in > > > > > > > > > > > > > > > > > U-Boot SPL > > > > > > > > > > > > > > > > > theoretically, but it still fail somewhere. > > > > > > > > > > > > > > > > > After dig in > > > > > > > > > > > > > > > > > and found there is an assumption that hart 0 > > > > > > > > > > > > > > > > > shall be > > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a > > > > > > > > > > > > > > > compatible issue. > > > > > > > > > > > > > > > There is a limitation that only hart 0 can be > > > > > > > > > > > > > > > main hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the initialization > > > > > > > > > > > > > are the > > > > > > > > > > > > > 1. get hart ID. > > > > > > > > > > > > > 2. determine which route to take based on their ID > > > > > > > > > > > > > respectively. > > > > > > > > > > > > > > > > > > > > > > > > > > So, I do think OpenSBI has this signature, if you are > > > > > > > > > > > > > not willing to call it > > > > > > > > > > > > > a limitation. > > > > > > > > > > > > > > > > > > > > > > > > This dependency on hart id #0 was not there until we > > > > > > > > > > > > added self-relocation > > > > > > > > > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > > > > > > > > > > > > > > > > > I will try to fix this in OpenSBI but we might end-up > > > > > > > > > > > > having boot_lottery. > > > > > > > > > > > > > > > > > > > > > > I have send a patch to fix this OpenSBI: > > > > > > > > > > > "[PATCH] firmware: Introduce relocation lottery" > > > > > > > > > > > > > > > > > > > > > > Can you try above patch and see if that helps ? > > > > > > > > > > > > > > > > > > > > > > It will be great if you can provide Tested-by to my patch > > > > > > > > > > > as well. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, Nov 7, 2019 at 7:04 AM Rick Chen wrote: > > Hi Anup > > > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote: > > > > > > Hi Anup > > > > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote: > > > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen > > > > > wrote: > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng > > > > > > > > > > > > wrote: > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always will be > > > > > > > > > > > > > > > > main > > > > > > > > > > > > > > > > hart coincidentally. When develop SPL flow, I > > > > > > > > > > > > > > > > try to > > > > > > > > > > > > > > > > force other harts to be main hart. And it will > > > > > > > > > > > > > > > > go > > > > > > > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, or > > > > > > > > > > > > > > > just 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will cause one > > > > > > > > > > > > > > negative result > > > > > > > > > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main hart in > > > > > > > > > > > > > > > > U-Boot SPL > > > > > > > > > > > > > > > > theoretically, but it still fail somewhere. > > > > > > > > > > > > > > > > After dig in > > > > > > > > > > > > > > > > and found there is an assumption that hart 0 > > > > > > > > > > > > > > > > shall be > > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a > > > > > > > > > > > > > > compatible issue. > > > > > > > > > > > > > > There is a limitation that only hart 0 can be main > > > > > > > > > > > > > > hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the initialization > > > > > > > > > > > > are the > > > > > > > > > > > > 1. get hart ID. > > > > > > > > > > > > 2. determine which route to take based on their ID > > > > > > > > > > > > respectively. > > > > > > > > > > > > > > > > > > > > > > > > So, I do think OpenSBI has this signature, if you are > > > > > > > > > > > > not willing to call it > > > > > > > > > > > > a limitation. > > > > > > > > > > > > > > > > > > > > > > This dependency on hart id #0 was not there until we > > > > > > > > > > > added self-relocation > > > > > > > > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > > > > > > > > > > > > > > > I will try to fix this in OpenSBI but we might end-up > > > > > > > > > > > having boot_lottery. > > > > > > > > > > > > > > > > > > > > I have send a patch to fix this OpenSBI: > > > > > > > > > > "[PATCH] firmware: Introduce relocation lottery" > > > > > > > > > > > > > > > > > > > > Can you try above patch and see if that helps ? > > > > > > > > > > > > > > > > > > > > It will be great if you can provide Tested-by to my patch > > > > > > > > > > as well. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I can not find this patch in mailing list. > > > > > > > > Can you provide a hyperlink ? > > > > > > > > > > > > > > You can try latest riscv/opensbi master. > > > > > > > > > > > > > > I have tested the patch on SiFive Unleashed multiple times. > > > > > > > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Anup > On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote: > > > > Hi Anup > > > > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote: > > > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen wrote: > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen > > > > > > wrote: > > > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote: > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always will be > > > > > > > > > > > > > > > main > > > > > > > > > > > > > > > hart coincidentally. When develop SPL flow, I try > > > > > > > > > > > > > > > to > > > > > > > > > > > > > > > force other harts to be main hart. And it will go > > > > > > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, or just > > > > > > > > > > > > > > 1 fix? > > > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will cause one > > > > > > > > > > > > > negative result > > > > > > > > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main hart in > > > > > > > > > > > > > > > U-Boot SPL > > > > > > > > > > > > > > > theoretically, but it still fail somewhere. After > > > > > > > > > > > > > > > dig in > > > > > > > > > > > > > > > and found there is an assumption that hart 0 > > > > > > > > > > > > > > > shall be > > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a > > > > > > > > > > > > > compatible issue. > > > > > > > > > > > > > There is a limitation that only hart 0 can be main > > > > > > > > > > > > > hart in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the initialization are > > > > > > > > > > > the > > > > > > > > > > > 1. get hart ID. > > > > > > > > > > > 2. determine which route to take based on their ID > > > > > > > > > > > respectively. > > > > > > > > > > > > > > > > > > > > > > So, I do think OpenSBI has this signature, if you are not > > > > > > > > > > > willing to call it > > > > > > > > > > > a limitation. > > > > > > > > > > > > > > > > > > > > This dependency on hart id #0 was not there until we added > > > > > > > > > > self-relocation > > > > > > > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > > > > > > > > > > > > > I will try to fix this in OpenSBI but we might end-up > > > > > > > > > > having boot_lottery. > > > > > > > > > > > > > > > > > > I have send a patch to fix this OpenSBI: > > > > > > > > > "[PATCH] firmware: Introduce relocation lottery" > > > > > > > > > > > > > > > > > > Can you try above patch and see if that helps ? > > > > > > > > > > > > > > > > > > It will be great if you can provide Tested-by to my patch as > > > > > > > > > well. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > I can not find this patch in mailing list. > > > > > > > Can you provide a hyperlink ? > > > > > > > > > > > > You can try latest riscv/opensbi master. > > > > > > > > > > > > I have tested the patch on SiFive Unleashed multiple times. > > > > > > > > > > I have tried this patch, but it fail > > > > > firmware: Introduce relocation lottery( > > > > > 98f4a208995b027662a7b04a25e4fa5df5f3eefe) > > > > > > > > > > The scenario was as below: > > > > > There are 4 harts run in U-Boot SPL, hart 0 play as main hart. > > > > > The hart 1 will receive ipi and come into OpenSBI(0x100) from > > > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Wed, Nov 6, 2019 at 2:51 PM Rick Chen wrote: > > Hi Anup > > > > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote: > > > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen wrote: > > > > > > > > Hi Anup > > > > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote: > > > > > > > > > > > > Hi Anup > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote: > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always will be main > > > > > > > > > > > > > > hart coincidentally. When develop SPL flow, I try to > > > > > > > > > > > > > > force other harts to be main hart. And it will go > > > > > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, or just 1 > > > > > > > > > > > > > fix? > > > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will cause one > > > > > > > > > > > > negative result > > > > > > > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main hart in > > > > > > > > > > > > > > U-Boot SPL > > > > > > > > > > > > > > theoretically, but it still fail somewhere. After > > > > > > > > > > > > > > dig in > > > > > > > > > > > > > > and found there is an assumption that hart 0 shall > > > > > > > > > > > > > > be > > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a compatible > > > > > > > > > > > > issue. > > > > > > > > > > > > There is a limitation that only hart 0 can be main hart > > > > > > > > > > > > in OpenSBI. > > > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the initialization are > > > > > > > > > > the > > > > > > > > > > 1. get hart ID. > > > > > > > > > > 2. determine which route to take based on their ID > > > > > > > > > > respectively. > > > > > > > > > > > > > > > > > > > > So, I do think OpenSBI has this signature, if you are not > > > > > > > > > > willing to call it > > > > > > > > > > a limitation. > > > > > > > > > > > > > > > > > > This dependency on hart id #0 was not there until we added > > > > > > > > > self-relocation > > > > > > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > > > > > > > > > > > I will try to fix this in OpenSBI but we might end-up having > > > > > > > > > boot_lottery. > > > > > > > > > > > > > > > > I have send a patch to fix this OpenSBI: > > > > > > > > "[PATCH] firmware: Introduce relocation lottery" > > > > > > > > > > > > > > > > Can you try above patch and see if that helps ? > > > > > > > > > > > > > > > > It will be great if you can provide Tested-by to my patch as > > > > > > > > well. > > > > > > > > > > > > > > > > > > > > > > > > > > > I can not find this patch in mailing list. > > > > > > Can you provide a hyperlink ? > > > > > > > > > > You can try latest riscv/opensbi master. > > > > > > > > > > I have tested the patch on SiFive Unleashed multiple times. > > > > > > > > I have tried this patch, but it fail > > > > firmware: Introduce relocation lottery( > > > > 98f4a208995b027662a7b04a25e4fa5df5f3eefe) > > > > > > > > The scenario was as below: > > > > There are 4 harts run in U-Boot SPL, hart 0 play as main hart. > > > > The hart 1 will receive ipi and come into OpenSBI(0x100) from > > > > U-Boot SPL(0x0), meanwhile hart 0,2,3 still run in U-Boot SPL. > > > > Then hart 1 will do _relocate_copy_to_lower which will copy data from > > > > 0x100 to 0x0. > > > > And it will corrupt U-Boot SPL. > > > > > > The self-relocation in OpenSBI firmwares ensures that OpenSBI firmware > > > are moved to the
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Anup > > On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote: > > > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen wrote: > > > > > > Hi Anup > > > > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote: > > > > > > > > > > Hi Anup > > > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > > wrote: > > > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote: > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always will be main > > > > > > > > > > > > > hart coincidentally. When develop SPL flow, I try to > > > > > > > > > > > > > force other harts to be main hart. And it will go > > > > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, or just 1 > > > > > > > > > > > > fix? > > > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will cause one > > > > > > > > > > > negative result > > > > > > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main hart in U-Boot > > > > > > > > > > > > > SPL > > > > > > > > > > > > > theoretically, but it still fail somewhere. After dig > > > > > > > > > > > > > in > > > > > > > > > > > > > and found there is an assumption that hart 0 shall be > > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI too? > > > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a compatible > > > > > > > > > > > issue. > > > > > > > > > > > There is a limitation that only hart 0 can be main hart > > > > > > > > > > > in OpenSBI. > > > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the initialization are the > > > > > > > > > 1. get hart ID. > > > > > > > > > 2. determine which route to take based on their ID > > > > > > > > > respectively. > > > > > > > > > > > > > > > > > > So, I do think OpenSBI has this signature, if you are not > > > > > > > > > willing to call it > > > > > > > > > a limitation. > > > > > > > > > > > > > > > > This dependency on hart id #0 was not there until we added > > > > > > > > self-relocation > > > > > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > > > > > > > > > I will try to fix this in OpenSBI but we might end-up having > > > > > > > > boot_lottery. > > > > > > > > > > > > > > I have send a patch to fix this OpenSBI: > > > > > > > "[PATCH] firmware: Introduce relocation lottery" > > > > > > > > > > > > > > Can you try above patch and see if that helps ? > > > > > > > > > > > > > > It will be great if you can provide Tested-by to my patch as well. > > > > > > > > > > > > > > > > > > > > > > > I can not find this patch in mailing list. > > > > > Can you provide a hyperlink ? > > > > > > > > You can try latest riscv/opensbi master. > > > > > > > > I have tested the patch on SiFive Unleashed multiple times. > > > > > > I have tried this patch, but it fail > > > firmware: Introduce relocation lottery( > > > 98f4a208995b027662a7b04a25e4fa5df5f3eefe) > > > > > > The scenario was as below: > > > There are 4 harts run in U-Boot SPL, hart 0 play as main hart. > > > The hart 1 will receive ipi and come into OpenSBI(0x100) from > > > U-Boot SPL(0x0), meanwhile hart 0,2,3 still run in U-Boot SPL. > > > Then hart 1 will do _relocate_copy_to_lower which will copy data from > > > 0x100 to 0x0. > > > And it will corrupt U-Boot SPL. > > > > The self-relocation in OpenSBI firmwares ensures that OpenSBI firmware > > are moved to the FW_TEXT_START before entering C code. This helps > > us load OpenSBI firmwares anywhere in RAM. > > > > However, OpenSBI firmwares don't know where the U-Boot SPL is running. > > > > In your case, both OpenSBI FW_DYNAMIC and U-Boot SPL are linked to > > address same address 0x0. This means secondary HARTs cannot safely > > wait while primary HART enters OpenSBI.
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Wed, Nov 6, 2019 at 2:18 PM Anup Patel wrote: > > On Wed, Nov 6, 2019 at 12:14 PM Rick Chen wrote: > > > > Hi Anup > > > > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote: > > > > > > > > Hi Anup > > > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > > wrote: > > > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote: > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always will be main > > > > > > > > > > > > hart coincidentally. When develop SPL flow, I try to > > > > > > > > > > > > force other harts to be main hart. And it will go > > > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, or just 1 fix? > > > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will cause one negative > > > > > > > > > > result > > > > > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main hart in U-Boot SPL > > > > > > > > > > > > theoretically, but it still fail somewhere. After dig in > > > > > > > > > > > > and found there is an assumption that hart 0 shall be > > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI too? > > > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a compatible > > > > > > > > > > issue. > > > > > > > > > > There is a limitation that only hart 0 can be main hart in > > > > > > > > > > OpenSBI. > > > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the initialization are the > > > > > > > > 1. get hart ID. > > > > > > > > 2. determine which route to take based on their ID respectively. > > > > > > > > > > > > > > > > So, I do think OpenSBI has this signature, if you are not > > > > > > > > willing to call it > > > > > > > > a limitation. > > > > > > > > > > > > > > This dependency on hart id #0 was not there until we added > > > > > > > self-relocation > > > > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > > > > > > > I will try to fix this in OpenSBI but we might end-up having > > > > > > > boot_lottery. > > > > > > > > > > > > I have send a patch to fix this OpenSBI: > > > > > > "[PATCH] firmware: Introduce relocation lottery" > > > > > > > > > > > > Can you try above patch and see if that helps ? > > > > > > > > > > > > It will be great if you can provide Tested-by to my patch as well. > > > > > > > > > > > > > > > > > > > I can not find this patch in mailing list. > > > > Can you provide a hyperlink ? > > > > > > You can try latest riscv/opensbi master. > > > > > > I have tested the patch on SiFive Unleashed multiple times. > > > > I have tried this patch, but it fail > > firmware: Introduce relocation lottery( > > 98f4a208995b027662a7b04a25e4fa5df5f3eefe) > > > > The scenario was as below: > > There are 4 harts run in U-Boot SPL, hart 0 play as main hart. > > The hart 1 will receive ipi and come into OpenSBI(0x100) from > > U-Boot SPL(0x0), meanwhile hart 0,2,3 still run in U-Boot SPL. > > Then hart 1 will do _relocate_copy_to_lower which will copy data from > > 0x100 to 0x0. > > And it will corrupt U-Boot SPL. > > The self-relocation in OpenSBI firmwares ensures that OpenSBI firmware > are moved to the FW_TEXT_START before entering C code. This helps > us load OpenSBI firmwares anywhere in RAM. > > However, OpenSBI firmwares don't know where the U-Boot SPL is running. > > In your case, both OpenSBI FW_DYNAMIC and U-Boot SPL are linked to > address same address 0x0. This means secondary HARTs cannot safely > wait while primary HART enters OpenSBI. You should hold secondary HARTs > in U-Boot SPL only till OpenSBI FW_DYNAMIC and U-Boot proper are > loaded in RAM by primary HART. All your HARTs should jump to OpenSBI > at the same time after everything is loaded in RAM. I see the issue now. The U-Boot SPL is first letting secondary HART jump to OpenSBI and primary HART jumps to OpenSBI at
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Wed, Nov 6, 2019 at 12:14 PM Rick Chen wrote: > > Hi Anup > > > > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote: > > > > > > Hi Anup > > > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel > > > > > wrote: > > > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > > wrote: > > > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote: > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always will be main > > > > > > > > > > > hart coincidentally. When develop SPL flow, I try to > > > > > > > > > > > force other harts to be main hart. And it will go > > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, or just 1 fix? > > > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will cause one negative > > > > > > > > > result > > > > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main hart in U-Boot SPL > > > > > > > > > > > theoretically, but it still fail somewhere. After dig in > > > > > > > > > > > and found there is an assumption that hart 0 shall be > > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI too? > > > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a compatible issue. > > > > > > > > > There is a limitation that only hart 0 can be main hart in > > > > > > > > > OpenSBI. > > > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the initialization are the > > > > > > > 1. get hart ID. > > > > > > > 2. determine which route to take based on their ID respectively. > > > > > > > > > > > > > > So, I do think OpenSBI has this signature, if you are not willing > > > > > > > to call it > > > > > > > a limitation. > > > > > > > > > > > > This dependency on hart id #0 was not there until we added > > > > > > self-relocation > > > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > > > > > I will try to fix this in OpenSBI but we might end-up having > > > > > > boot_lottery. > > > > > > > > > > I have send a patch to fix this OpenSBI: > > > > > "[PATCH] firmware: Introduce relocation lottery" > > > > > > > > > > Can you try above patch and see if that helps ? > > > > > > > > > > It will be great if you can provide Tested-by to my patch as well. > > > > > > > > > > > > > > > I can not find this patch in mailing list. > > > Can you provide a hyperlink ? > > > > You can try latest riscv/opensbi master. > > > > I have tested the patch on SiFive Unleashed multiple times. > > I have tried this patch, but it fail > firmware: Introduce relocation lottery( > 98f4a208995b027662a7b04a25e4fa5df5f3eefe) > > The scenario was as below: > There are 4 harts run in U-Boot SPL, hart 0 play as main hart. > The hart 1 will receive ipi and come into OpenSBI(0x100) from > U-Boot SPL(0x0), meanwhile hart 0,2,3 still run in U-Boot SPL. > Then hart 1 will do _relocate_copy_to_lower which will copy data from > 0x100 to 0x0. > And it will corrupt U-Boot SPL. The self-relocation in OpenSBI firmwares ensures that OpenSBI firmware are moved to the FW_TEXT_START before entering C code. This helps us load OpenSBI firmwares anywhere in RAM. However, OpenSBI firmwares don't know where the U-Boot SPL is running. In your case, both OpenSBI FW_DYNAMIC and U-Boot SPL are linked to address same address 0x0. This means secondary HARTs cannot safely wait while primary HART enters OpenSBI. You should hold secondary HARTs in U-Boot SPL only till OpenSBI FW_DYNAMIC and U-Boot proper are loaded in RAM by primary HART. All your HARTs should jump to OpenSBI at the same time after everything is loaded in RAM. Regards, Anup ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Anup > > On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote: > > > > Hi Anup > > > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel wrote: > > > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao > > > > > wrote: > > > > > > > > > > > > Hi Bin, > > > > > > > > > > > > Thanks for the critics. Comments below. > > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote: > > > > > > > Hi Rick, > > > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > > wrote: > > > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always will be main > > > > > > > > > > hart coincidentally. When develop SPL flow, I try to > > > > > > > > > > force other harts to be main hart. And it will go > > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, or just 1 fix? > > > > > > > > > > > > > > > > Yes, it include two fixs. But they will cause one negative > > > > > > > > result > > > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main hart in U-Boot SPL > > > > > > > > > > theoretically, but it still fail somewhere. After dig in > > > > > > > > > > and found there is an assumption that hart 0 shall be > > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI too? > > > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a compatible issue. > > > > > > > > There is a limitation that only hart 0 can be main hart in > > > > > > > > OpenSBI. > > > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > > > > Please check the source. > > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > > > Apparently, the FIRST TWO LINEs of the initialization are the > > > > > > 1. get hart ID. > > > > > > 2. determine which route to take based on their ID respectively. > > > > > > > > > > > > So, I do think OpenSBI has this signature, if you are not willing > > > > > > to call it > > > > > > a limitation. > > > > > > > > > > This dependency on hart id #0 was not there until we added > > > > > self-relocation > > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > > > I will try to fix this in OpenSBI but we might end-up having > > > > > boot_lottery. > > > > > > > > I have send a patch to fix this OpenSBI: > > > > "[PATCH] firmware: Introduce relocation lottery" > > > > > > > > Can you try above patch and see if that helps ? > > > > > > > > It will be great if you can provide Tested-by to my patch as well. > > > > > > > > > > > I can not find this patch in mailing list. > > Can you provide a hyperlink ? > > You can try latest riscv/opensbi master. > > I have tested the patch on SiFive Unleashed multiple times. I have tried this patch, but it fail firmware: Introduce relocation lottery( 98f4a208995b027662a7b04a25e4fa5df5f3eefe) The scenario was as below: There are 4 harts run in U-Boot SPL, hart 0 play as main hart. The hart 1 will receive ipi and come into OpenSBI(0x100) from U-Boot SPL(0x0), meanwhile hart 0,2,3 still run in U-Boot SPL. Then hart 1 will do _relocate_copy_to_lower which will copy data from 0x100 to 0x0. And it will corrupt U-Boot SPL. Thanks Rick > > Regards, > Anup > > > > > Thanks > > Rick ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Tue, Nov 5, 2019 at 7:19 AM Rick Chen wrote: > > Hi Anup > > > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel wrote: > > > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao wrote: > > > > > > > > > > Hi Bin, > > > > > > > > > > Thanks for the critics. Comments below. > > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote: > > > > > > Hi Rick, > > > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > > wrote: > > > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes > > > > > > > > wrote: > > > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > > > It will work fine due to hart 0 always will be main > > > > > > > > > hart coincidentally. When develop SPL flow, I try to > > > > > > > > > force other harts to be main hart. And it will go > > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, or just 1 fix? > > > > > > > > > > > > > > Yes, it include two fixs. But they will cause one negative result > > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main hart in U-Boot SPL > > > > > > > > > theoretically, but it still fail somewhere. After dig in > > > > > > > > > and found there is an assumption that hart 0 shall be > > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI too? > > > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a compatible issue. > > > > > > > There is a limitation that only hart 0 can be main hart in > > > > > > > OpenSBI. > > > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > > > > Please check the source. > > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > > > Apparently, the FIRST TWO LINEs of the initialization are the > > > > > 1. get hart ID. > > > > > 2. determine which route to take based on their ID respectively. > > > > > > > > > > So, I do think OpenSBI has this signature, if you are not willing to > > > > > call it > > > > > a limitation. > > > > > > > > This dependency on hart id #0 was not there until we added > > > > self-relocation > > > > in OpenSBI for FW_DYNAMIC. > > > > > > > > I will try to fix this in OpenSBI but we might end-up having > > > > boot_lottery. > > > > > > I have send a patch to fix this OpenSBI: > > > "[PATCH] firmware: Introduce relocation lottery" > > > > > > Can you try above patch and see if that helps ? > > > > > > It will be great if you can provide Tested-by to my patch as well. > > > > > > > I can not find this patch in mailing list. > Can you provide a hyperlink ? You can try latest riscv/opensbi master. I have tested the patch on SiFive Unleashed multiple times. Regards, Anup > > Thanks > Rick ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Anup > > On Thu, Oct 31, 2019 at 1:42 PM Anup Patel wrote: > > > > > > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao wrote: > > > > > > > > Hi Bin, > > > > > > > > Thanks for the critics. Comments below. > > > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote: > > > > > Hi Rick, > > > > > > > > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen > > > > > wrote: > > > > > > > > > > > > Hi Bin > > > > > > > > > > > > > > > > > > > > Hi Rick, > > > > > > > > > > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote: > > > > > > > > > > > > > > > > From: Rick Chen > > > > > > > > > > > > > > > > It will work fine due to hart 0 always will be main > > > > > > > > hart coincidentally. When develop SPL flow, I try to > > > > > > > > force other harts to be main hart. And it will go > > > > > > > > wrong in sending IPI flow. So fix it. > > > > > > > > > > > > > > Fix what? Does this commit contain 2 fixes, or just 1 fix? > > > > > > > > > > > > Yes, it include two fixs. But they will cause one negative result > > > > > > that only hart 0 can send ipi to other harts. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Having this fix, any hart can be main hart in U-Boot SPL > > > > > > > > theoretically, but it still fail somewhere. After dig in > > > > > > > > and found there is an assumption that hart 0 shall be > > > > > > > > main hart in OpenSbi. > > > > > > > > > > > > > > So does this mean there is a bug in OpenSBI too? > > > > > > > > > > > > I am not sure if it is a bug. Maybe it is a compatible issue. > > > > > > There is a limitation that only hart 0 can be main hart in OpenSBI. > > > > > > > > > > I don't think OpenSBI has such limitation. > > > > > > > > > > > > > Please check the source. > > > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54 > > > > > > > > Apparently, the FIRST TWO LINEs of the initialization are the > > > > 1. get hart ID. > > > > 2. determine which route to take based on their ID respectively. > > > > > > > > So, I do think OpenSBI has this signature, if you are not willing to > > > > call it > > > > a limitation. > > > > > > This dependency on hart id #0 was not there until we added self-relocation > > > in OpenSBI for FW_DYNAMIC. > > > > > > I will try to fix this in OpenSBI but we might end-up having boot_lottery. > > > > I have send a patch to fix this OpenSBI: > > "[PATCH] firmware: Introduce relocation lottery" > > > > Can you try above patch and see if that helps ? > > > > It will be great if you can provide Tested-by to my patch as well. > > > I can not find this patch in mailing list. Can you provide a hyperlink ? Thanks Rick ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Anup
>
> On Thu, Oct 31, 2019 at 1:42 PM Anup Patel wrote:
> >
> > On Thu, Oct 31, 2019 at 6:30 AM Alan Kao wrote:
> > >
> > > Hi Bin,
> > >
> > > Thanks for the critics. Comments below.
> > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote:
> > > > Hi Rick,
> > > >
> > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
> > > > >
> > > > > Hi Bin
> > > > >
> > > > > >
> > > > > > Hi Rick,
> > > > > >
> > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > > > > > >
> > > > > > > From: Rick Chen
> > > > > > >
> > > > > > > It will work fine due to hart 0 always will be main
> > > > > > > hart coincidentally. When develop SPL flow, I try to
> > > > > > > force other harts to be main hart. And it will go
> > > > > > > wrong in sending IPI flow. So fix it.
> > > > > >
> > > > > > Fix what? Does this commit contain 2 fixes, or just 1 fix?
> > > > >
> > > > > Yes, it include two fixs. But they will cause one negative result
> > > > > that only hart 0 can send ipi to other harts.
> > > > >
> > > > > >
> > > > > > >
> > > > > > > Having this fix, any hart can be main hart in U-Boot SPL
> > > > > > > theoretically, but it still fail somewhere. After dig in
> > > > > > > and found there is an assumption that hart 0 shall be
> > > > > > > main hart in OpenSbi.
> > > > > >
> > > > > > So does this mean there is a bug in OpenSBI too?
> > > > >
> > > > > I am not sure if it is a bug. Maybe it is a compatible issue.
> > > > > There is a limitation that only hart 0 can be main hart in OpenSBI.
> > > >
> > > > I don't think OpenSBI has such limitation.
> > > >
> > >
> > > Please check the source.
> > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54
> > >
> > > Apparently, the FIRST TWO LINEs of the initialization are the
> > > 1. get hart ID.
> > > 2. determine which route to take based on their ID respectively.
> > >
> > > So, I do think OpenSBI has this signature, if you are not willing to call
> > > it
> > > a limitation.
> >
> > This dependency on hart id #0 was not there until we added self-relocation
> > in OpenSBI for FW_DYNAMIC.
> >
> > I will try to fix this in OpenSBI but we might end-up having boot_lottery.
>
> I have send a patch to fix this OpenSBI:
> "[PATCH] firmware: Introduce relocation lottery"
>
> Can you try above patch and see if that helps ?
>
> It will be great if you can provide Tested-by to my patch as well.
>
OK
Thanks
Rick
> Regards,
> Anup
>
> >
> > >
> > > > > But any hart can be main hart in U-Boot.
> > > > >
> > > > > In general case, hart 0 will be main and it is fine when U-Boot jump
> > > > > ot OpenSBI.
> > > > > But if we force hart 1 to be main hart, when hart 0 jump to OPenSBI
> > > > > from U-Boot,
> > > > > It will do relocation flow in OpenSBI which willcorrupt U-Boot SPL,
> > > > > but hart 0 still in U-Boot SPL.
> > > > >
> > > > > >
> > > > > > >
> > > > > > > After some work-arounds, it can pass the verifications
> > > > > > > that any hart can be main hart and boots U-Boot SPL ->
> > > > > > > OpenSbi -> U-Boot proper -> Linux Kernel successfully.
> > > > > > >
> > > > > >
> > > > > > It's a bit hard for me to understand what was described here in the
> > > > > > commit message. Maybe you need rewrite something.
> > > > >
> > > > > OK. I will rewrite this commit message.
> > > > >
> > > > > >
> > > > > > > Signed-off-by: Rick Chen
> > > > > > > Cc: KC Lin
> > > > > > > Cc: Alan Kao
> > > > > > > ---
> > > > > > > arch/riscv/lib/andes_plic.c | 11 +++
> > > > > > > 1 file changed, 7 insertions(+), 4 deletions(-)
> > > > > > >
> > > > > > > diff --git a/arch/riscv/lib/andes_plic.c
> > > > > > > b/arch/riscv/lib/andes_plic.c
> > > > > > > index 28568e4..42394b9 100644
> > > > > > > --- a/arch/riscv/lib/andes_plic.c
> > > > > > > +++ b/arch/riscv/lib/andes_plic.c
> > > > > > > @@ -19,7 +19,7 @@
> > > > > > > #include
> > > > > > >
> > > > > > > /* pending register */
> > > > > > > -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > > > (hart) * 8)
> > > > > > > +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > > > ((hart) / 4) * 4)
> > > > > > > /* enable register */
> > > > > > > #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart)
> > > > > > > * 0x80)
> > > > > > > /* claim register */
> > > > > > > @@ -46,7 +46,7 @@ static int init_plic(void);
> > > > > > >
> > > > > > > static int enable_ipi(int hart)
> > > > > > > {
> > > > > > > - int en;
> > > > > > > + unsigned int en;
> > > > > >
> > > > > > Is this for some compiler warning fix?
> > > > >
> > > > > No, it is not a warning fix. It is a bug fix.
> > > > > I hope en can be 0x80808080 instead of 0x80808080,
> > > >
> > > > But it is int, which is only 32-bit. The example you gave was a 64-bit
> > > > number.
> > > >
> > >
> > > Please consider the following simple program:
> > >
> > > > #define MASK 0x80808080
> > > >int main(){
> > > >int en;
> > > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Bin,
Thanks for the critics. Comments below.
On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote:
> Hi Rick,
>
> On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
> >
> > Hi Bin
> >
> > >
> > > Hi Rick,
> > >
> > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > > >
> > > > From: Rick Chen
> > > >
> > > > It will work fine due to hart 0 always will be main
> > > > hart coincidentally. When develop SPL flow, I try to
> > > > force other harts to be main hart. And it will go
> > > > wrong in sending IPI flow. So fix it.
> > >
> > > Fix what? Does this commit contain 2 fixes, or just 1 fix?
> >
> > Yes, it include two fixs. But they will cause one negative result
> > that only hart 0 can send ipi to other harts.
> >
> > >
> > > >
> > > > Having this fix, any hart can be main hart in U-Boot SPL
> > > > theoretically, but it still fail somewhere. After dig in
> > > > and found there is an assumption that hart 0 shall be
> > > > main hart in OpenSbi.
> > >
> > > So does this mean there is a bug in OpenSBI too?
> >
> > I am not sure if it is a bug. Maybe it is a compatible issue.
> > There is a limitation that only hart 0 can be main hart in OpenSBI.
>
> I don't think OpenSBI has such limitation.
>
Please check the source.
https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54
Apparently, the FIRST TWO LINEs of the initialization are the
1. get hart ID.
2. determine which route to take based on their ID respectively.
So, I do think OpenSBI has this signature, if you are not willing to call it
a limitation.
> > But any hart can be main hart in U-Boot.
> >
> > In general case, hart 0 will be main and it is fine when U-Boot jump ot
> > OpenSBI.
> > But if we force hart 1 to be main hart, when hart 0 jump to OPenSBI from
> > U-Boot,
> > It will do relocation flow in OpenSBI which willcorrupt U-Boot SPL,
> > but hart 0 still in U-Boot SPL.
> >
> > >
> > > >
> > > > After some work-arounds, it can pass the verifications
> > > > that any hart can be main hart and boots U-Boot SPL ->
> > > > OpenSbi -> U-Boot proper -> Linux Kernel successfully.
> > > >
> > >
> > > It's a bit hard for me to understand what was described here in the
> > > commit message. Maybe you need rewrite something.
> >
> > OK. I will rewrite this commit message.
> >
> > >
> > > > Signed-off-by: Rick Chen
> > > > Cc: KC Lin
> > > > Cc: Alan Kao
> > > > ---
> > > > arch/riscv/lib/andes_plic.c | 11 +++
> > > > 1 file changed, 7 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> > > > index 28568e4..42394b9 100644
> > > > --- a/arch/riscv/lib/andes_plic.c
> > > > +++ b/arch/riscv/lib/andes_plic.c
> > > > @@ -19,7 +19,7 @@
> > > > #include
> > > >
> > > > /* pending register */
> > > > -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > (hart) * 8)
> > > > +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > ((hart) / 4) * 4)
> > > > /* enable register */
> > > > #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
> > > > /* claim register */
> > > > @@ -46,7 +46,7 @@ static int init_plic(void);
> > > >
> > > > static int enable_ipi(int hart)
> > > > {
> > > > - int en;
> > > > + unsigned int en;
> > >
> > > Is this for some compiler warning fix?
> >
> > No, it is not a warning fix. It is a bug fix.
> > I hope en can be 0x80808080 instead of 0x80808080,
>
> But it is int, which is only 32-bit. The example you gave was a 64-bit number.
>
Please consider the following simple program:
> #define MASK 0x80808080
>int main(){
>int en;
>en = MASK;
>printf("%x, shifted %x\n", en, en >> 1);
>return 0;
>}
Would you mind sharing what you get after running this on your x86_64
(if you have one) computer? Really appreiciate that.
The almost identical episode is in the patch, specifically,
> en = ENABLE_HART_IPI >> hart
> > or it will cause IPI sending errors.
> >
>
> Regards,
> Bin
Best,
Alan
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Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, Oct 31, 2019 at 1:42 PM Anup Patel wrote:
>
> On Thu, Oct 31, 2019 at 6:30 AM Alan Kao wrote:
> >
> > Hi Bin,
> >
> > Thanks for the critics. Comments below.
> > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote:
> > > Hi Rick,
> > >
> > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
> > > >
> > > > Hi Bin
> > > >
> > > > >
> > > > > Hi Rick,
> > > > >
> > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > > > > >
> > > > > > From: Rick Chen
> > > > > >
> > > > > > It will work fine due to hart 0 always will be main
> > > > > > hart coincidentally. When develop SPL flow, I try to
> > > > > > force other harts to be main hart. And it will go
> > > > > > wrong in sending IPI flow. So fix it.
> > > > >
> > > > > Fix what? Does this commit contain 2 fixes, or just 1 fix?
> > > >
> > > > Yes, it include two fixs. But they will cause one negative result
> > > > that only hart 0 can send ipi to other harts.
> > > >
> > > > >
> > > > > >
> > > > > > Having this fix, any hart can be main hart in U-Boot SPL
> > > > > > theoretically, but it still fail somewhere. After dig in
> > > > > > and found there is an assumption that hart 0 shall be
> > > > > > main hart in OpenSbi.
> > > > >
> > > > > So does this mean there is a bug in OpenSBI too?
> > > >
> > > > I am not sure if it is a bug. Maybe it is a compatible issue.
> > > > There is a limitation that only hart 0 can be main hart in OpenSBI.
> > >
> > > I don't think OpenSBI has such limitation.
> > >
> >
> > Please check the source.
> > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54
> >
> > Apparently, the FIRST TWO LINEs of the initialization are the
> > 1. get hart ID.
> > 2. determine which route to take based on their ID respectively.
> >
> > So, I do think OpenSBI has this signature, if you are not willing to call it
> > a limitation.
>
> This dependency on hart id #0 was not there until we added self-relocation
> in OpenSBI for FW_DYNAMIC.
>
> I will try to fix this in OpenSBI but we might end-up having boot_lottery.
I have send a patch to fix this OpenSBI:
"[PATCH] firmware: Introduce relocation lottery"
Can you try above patch and see if that helps ?
It will be great if you can provide Tested-by to my patch as well.
Regards,
Anup
>
> >
> > > > But any hart can be main hart in U-Boot.
> > > >
> > > > In general case, hart 0 will be main and it is fine when U-Boot jump ot
> > > > OpenSBI.
> > > > But if we force hart 1 to be main hart, when hart 0 jump to OPenSBI
> > > > from U-Boot,
> > > > It will do relocation flow in OpenSBI which willcorrupt U-Boot SPL,
> > > > but hart 0 still in U-Boot SPL.
> > > >
> > > > >
> > > > > >
> > > > > > After some work-arounds, it can pass the verifications
> > > > > > that any hart can be main hart and boots U-Boot SPL ->
> > > > > > OpenSbi -> U-Boot proper -> Linux Kernel successfully.
> > > > > >
> > > > >
> > > > > It's a bit hard for me to understand what was described here in the
> > > > > commit message. Maybe you need rewrite something.
> > > >
> > > > OK. I will rewrite this commit message.
> > > >
> > > > >
> > > > > > Signed-off-by: Rick Chen
> > > > > > Cc: KC Lin
> > > > > > Cc: Alan Kao
> > > > > > ---
> > > > > > arch/riscv/lib/andes_plic.c | 11 +++
> > > > > > 1 file changed, 7 insertions(+), 4 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/riscv/lib/andes_plic.c
> > > > > > b/arch/riscv/lib/andes_plic.c
> > > > > > index 28568e4..42394b9 100644
> > > > > > --- a/arch/riscv/lib/andes_plic.c
> > > > > > +++ b/arch/riscv/lib/andes_plic.c
> > > > > > @@ -19,7 +19,7 @@
> > > > > > #include
> > > > > >
> > > > > > /* pending register */
> > > > > > -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > > (hart) * 8)
> > > > > > +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > > ((hart) / 4) * 4)
> > > > > > /* enable register */
> > > > > > #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) *
> > > > > > 0x80)
> > > > > > /* claim register */
> > > > > > @@ -46,7 +46,7 @@ static int init_plic(void);
> > > > > >
> > > > > > static int enable_ipi(int hart)
> > > > > > {
> > > > > > - int en;
> > > > > > + unsigned int en;
> > > > >
> > > > > Is this for some compiler warning fix?
> > > >
> > > > No, it is not a warning fix. It is a bug fix.
> > > > I hope en can be 0x80808080 instead of 0x80808080,
> > >
> > > But it is int, which is only 32-bit. The example you gave was a 64-bit
> > > number.
> > >
> >
> > Please consider the following simple program:
> >
> > > #define MASK 0x80808080
> > >int main(){
> > >int en;
> > >en = MASK;
> > >printf("%x, shifted %x\n", en, en >> 1);
> > >return 0;
> > >}
> >
> > Would you mind sharing what you get after running this on your x86_64
> > (if you have one) computer? Really appreiciate that.
> >
> > The almost identical episode is in the patch, specifically,
> > >
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, Oct 31, 2019 at 11:36:48AM +0800, Bin Meng wrote:
> Hi Alan,
>
> On Thu, Oct 31, 2019 at 9:00 AM Alan Kao wrote:
> >
> > Hi Bin,
> >
> > Thanks for the critics. Comments below.
> > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote:
> > > Hi Rick,
> > >
> > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
> > > >
> > > > Hi Bin
> > > >
> > > > >
> > > > > Hi Rick,
> > > > >
> > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > > > > >
> > > > > > From: Rick Chen
> > > > > >
> > > > > > It will work fine due to hart 0 always will be main
> > > > > > hart coincidentally. When develop SPL flow, I try to
> > > > > > force other harts to be main hart. And it will go
> > > > > > wrong in sending IPI flow. So fix it.
> > > > >
> > > > > Fix what? Does this commit contain 2 fixes, or just 1 fix?
> > > >
> > > > Yes, it include two fixs. But they will cause one negative result
> > > > that only hart 0 can send ipi to other harts.
> > > >
> > > > >
> > > > > >
> > > > > > Having this fix, any hart can be main hart in U-Boot SPL
> > > > > > theoretically, but it still fail somewhere. After dig in
> > > > > > and found there is an assumption that hart 0 shall be
> > > > > > main hart in OpenSbi.
> > > > >
> > > > > So does this mean there is a bug in OpenSBI too?
> > > >
> > > > I am not sure if it is a bug. Maybe it is a compatible issue.
> > > > There is a limitation that only hart 0 can be main hart in OpenSBI.
> > >
> > > I don't think OpenSBI has such limitation.
> > >
> >
> > Please check the source.
> > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54
> >
> > Apparently, the FIRST TWO LINEs of the initialization are the
> > 1. get hart ID.
> > 2. determine which route to take based on their ID respectively.
> >
>
> This is true only for the very first a few instructions when OpenSBI
> boots. Later OpenSBI main initialization does not require hart to be
> zero.
>
> > So, I do think OpenSBI has this signature, if you are not willing to call it
> > a limitation.
> >
> > > > But any hart can be main hart in U-Boot.
> > > >
> > > > In general case, hart 0 will be main and it is fine when U-Boot jump ot
> > > > OpenSBI.
> > > > But if we force hart 1 to be main hart, when hart 0 jump to OPenSBI
> > > > from U-Boot,
> > > > It will do relocation flow in OpenSBI which willcorrupt U-Boot SPL,
> > > > but hart 0 still in U-Boot SPL.
> > > >
> > > > >
> > > > > >
> > > > > > After some work-arounds, it can pass the verifications
> > > > > > that any hart can be main hart and boots U-Boot SPL ->
> > > > > > OpenSbi -> U-Boot proper -> Linux Kernel successfully.
> > > > > >
> > > > >
> > > > > It's a bit hard for me to understand what was described here in the
> > > > > commit message. Maybe you need rewrite something.
> > > >
> > > > OK. I will rewrite this commit message.
> > > >
> > > > >
> > > > > > Signed-off-by: Rick Chen
> > > > > > Cc: KC Lin
> > > > > > Cc: Alan Kao
> > > > > > ---
> > > > > > arch/riscv/lib/andes_plic.c | 11 +++
> > > > > > 1 file changed, 7 insertions(+), 4 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/riscv/lib/andes_plic.c
> > > > > > b/arch/riscv/lib/andes_plic.c
> > > > > > index 28568e4..42394b9 100644
> > > > > > --- a/arch/riscv/lib/andes_plic.c
> > > > > > +++ b/arch/riscv/lib/andes_plic.c
> > > > > > @@ -19,7 +19,7 @@
> > > > > > #include
> > > > > >
> > > > > > /* pending register */
> > > > > > -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > > (hart) * 8)
> > > > > > +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > > ((hart) / 4) * 4)
> > > > > > /* enable register */
> > > > > > #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) *
> > > > > > 0x80)
> > > > > > /* claim register */
> > > > > > @@ -46,7 +46,7 @@ static int init_plic(void);
> > > > > >
> > > > > > static int enable_ipi(int hart)
> > > > > > {
> > > > > > - int en;
> > > > > > + unsigned int en;
> > > > >
> > > > > Is this for some compiler warning fix?
> > > >
> > > > No, it is not a warning fix. It is a bug fix.
> > > > I hope en can be 0x80808080 instead of 0x80808080,
> > >
> > > But it is int, which is only 32-bit. The example you gave was a 64-bit
> > > number.
> > >
> >
> > Please consider the following simple program:
> >
> > > #define MASK 0x80808080
> > >int main(){
> > >int en;
> > >en = MASK;
> > >printf("%x, shifted %x\n", en, en >> 1);
> > >return 0;
> > >}
> >
> > Would you mind sharing what you get after running this on your x86_64
> > (if you have one) computer? Really appreiciate that.
> >
> > The almost identical episode is in the patch, specifically,
> > > en = ENABLE_HART_IPI >> hart
>
> Yes, this is a bug. ...
Wait, what do you mean but "this"? What is a bug here?
If you want to be helpful, please also be specific or anyone else reviewing
this patch will be confused.
> ... But I was
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
On Thu, Oct 31, 2019 at 6:30 AM Alan Kao wrote:
>
> Hi Bin,
>
> Thanks for the critics. Comments below.
> On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote:
> > Hi Rick,
> >
> > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
> > >
> > > Hi Bin
> > >
> > > >
> > > > Hi Rick,
> > > >
> > > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > > > >
> > > > > From: Rick Chen
> > > > >
> > > > > It will work fine due to hart 0 always will be main
> > > > > hart coincidentally. When develop SPL flow, I try to
> > > > > force other harts to be main hart. And it will go
> > > > > wrong in sending IPI flow. So fix it.
> > > >
> > > > Fix what? Does this commit contain 2 fixes, or just 1 fix?
> > >
> > > Yes, it include two fixs. But they will cause one negative result
> > > that only hart 0 can send ipi to other harts.
> > >
> > > >
> > > > >
> > > > > Having this fix, any hart can be main hart in U-Boot SPL
> > > > > theoretically, but it still fail somewhere. After dig in
> > > > > and found there is an assumption that hart 0 shall be
> > > > > main hart in OpenSbi.
> > > >
> > > > So does this mean there is a bug in OpenSBI too?
> > >
> > > I am not sure if it is a bug. Maybe it is a compatible issue.
> > > There is a limitation that only hart 0 can be main hart in OpenSBI.
> >
> > I don't think OpenSBI has such limitation.
> >
>
> Please check the source.
> https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54
>
> Apparently, the FIRST TWO LINEs of the initialization are the
> 1. get hart ID.
> 2. determine which route to take based on their ID respectively.
>
> So, I do think OpenSBI has this signature, if you are not willing to call it
> a limitation.
This dependency on hart id #0 was not there until we added self-relocation
in OpenSBI for FW_DYNAMIC.
I will try to fix this in OpenSBI but we might end-up having boot_lottery.
>
> > > But any hart can be main hart in U-Boot.
> > >
> > > In general case, hart 0 will be main and it is fine when U-Boot jump ot
> > > OpenSBI.
> > > But if we force hart 1 to be main hart, when hart 0 jump to OPenSBI from
> > > U-Boot,
> > > It will do relocation flow in OpenSBI which willcorrupt U-Boot SPL,
> > > but hart 0 still in U-Boot SPL.
> > >
> > > >
> > > > >
> > > > > After some work-arounds, it can pass the verifications
> > > > > that any hart can be main hart and boots U-Boot SPL ->
> > > > > OpenSbi -> U-Boot proper -> Linux Kernel successfully.
> > > > >
> > > >
> > > > It's a bit hard for me to understand what was described here in the
> > > > commit message. Maybe you need rewrite something.
> > >
> > > OK. I will rewrite this commit message.
> > >
> > > >
> > > > > Signed-off-by: Rick Chen
> > > > > Cc: KC Lin
> > > > > Cc: Alan Kao
> > > > > ---
> > > > > arch/riscv/lib/andes_plic.c | 11 +++
> > > > > 1 file changed, 7 insertions(+), 4 deletions(-)
> > > > >
> > > > > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> > > > > index 28568e4..42394b9 100644
> > > > > --- a/arch/riscv/lib/andes_plic.c
> > > > > +++ b/arch/riscv/lib/andes_plic.c
> > > > > @@ -19,7 +19,7 @@
> > > > > #include
> > > > >
> > > > > /* pending register */
> > > > > -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > (hart) * 8)
> > > > > +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > ((hart) / 4) * 4)
> > > > > /* enable register */
> > > > > #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) *
> > > > > 0x80)
> > > > > /* claim register */
> > > > > @@ -46,7 +46,7 @@ static int init_plic(void);
> > > > >
> > > > > static int enable_ipi(int hart)
> > > > > {
> > > > > - int en;
> > > > > + unsigned int en;
> > > >
> > > > Is this for some compiler warning fix?
> > >
> > > No, it is not a warning fix. It is a bug fix.
> > > I hope en can be 0x80808080 instead of 0x80808080,
> >
> > But it is int, which is only 32-bit. The example you gave was a 64-bit
> > number.
> >
>
> Please consider the following simple program:
>
> > #define MASK 0x80808080
> >int main(){
> >int en;
> >en = MASK;
> >printf("%x, shifted %x\n", en, en >> 1);
> >return 0;
> >}
>
> Would you mind sharing what you get after running this on your x86_64
> (if you have one) computer? Really appreiciate that.
>
> The almost identical episode is in the patch, specifically,
> > en = ENABLE_HART_IPI >> hart
>
> > > or it will cause IPI sending errors.
> > >
> >
> > Regards,
> > Bin
>
> Best,
> Alan
Regards,
Anup
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Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Alan,
On Thu, Oct 31, 2019 at 3:49 PM Alan Kao wrote:
>
>
> On Thu, Oct 31, 2019 at 11:36:48AM +0800, Bin Meng wrote:
> > Hi Alan,
> >
> > On Thu, Oct 31, 2019 at 9:00 AM Alan Kao wrote:
> > >
> > > Hi Bin,
> > >
> > > Thanks for the critics. Comments below.
> > > On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote:
> > > > Hi Rick,
> > > >
> > > > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
> > > > >
> > > > > Hi Bin
> > > > >
> > > > > >
> > > > > > Hi Rick,
> > > > > >
> > > > > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > > > > > >
> > > > > > > From: Rick Chen
> > > > > > >
> > > > > > > It will work fine due to hart 0 always will be main
> > > > > > > hart coincidentally. When develop SPL flow, I try to
> > > > > > > force other harts to be main hart. And it will go
> > > > > > > wrong in sending IPI flow. So fix it.
> > > > > >
> > > > > > Fix what? Does this commit contain 2 fixes, or just 1 fix?
> > > > >
> > > > > Yes, it include two fixs. But they will cause one negative result
> > > > > that only hart 0 can send ipi to other harts.
> > > > >
> > > > > >
> > > > > > >
> > > > > > > Having this fix, any hart can be main hart in U-Boot SPL
> > > > > > > theoretically, but it still fail somewhere. After dig in
> > > > > > > and found there is an assumption that hart 0 shall be
> > > > > > > main hart in OpenSbi.
> > > > > >
> > > > > > So does this mean there is a bug in OpenSBI too?
> > > > >
> > > > > I am not sure if it is a bug. Maybe it is a compatible issue.
> > > > > There is a limitation that only hart 0 can be main hart in OpenSBI.
> > > >
> > > > I don't think OpenSBI has such limitation.
> > > >
> > >
> > > Please check the source.
> > > https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54
> > >
> > > Apparently, the FIRST TWO LINEs of the initialization are the
> > > 1. get hart ID.
> > > 2. determine which route to take based on their ID respectively.
> > >
> >
> > This is true only for the very first a few instructions when OpenSBI
> > boots. Later OpenSBI main initialization does not require hart to be
> > zero.
> >
> > > So, I do think OpenSBI has this signature, if you are not willing to call
> > > it
> > > a limitation.
> > >
> > > > > But any hart can be main hart in U-Boot.
> > > > >
> > > > > In general case, hart 0 will be main and it is fine when U-Boot jump
> > > > > ot OpenSBI.
> > > > > But if we force hart 1 to be main hart, when hart 0 jump to OPenSBI
> > > > > from U-Boot,
> > > > > It will do relocation flow in OpenSBI which willcorrupt U-Boot SPL,
> > > > > but hart 0 still in U-Boot SPL.
> > > > >
> > > > > >
> > > > > > >
> > > > > > > After some work-arounds, it can pass the verifications
> > > > > > > that any hart can be main hart and boots U-Boot SPL ->
> > > > > > > OpenSbi -> U-Boot proper -> Linux Kernel successfully.
> > > > > > >
> > > > > >
> > > > > > It's a bit hard for me to understand what was described here in the
> > > > > > commit message. Maybe you need rewrite something.
> > > > >
> > > > > OK. I will rewrite this commit message.
> > > > >
> > > > > >
> > > > > > > Signed-off-by: Rick Chen
> > > > > > > Cc: KC Lin
> > > > > > > Cc: Alan Kao
> > > > > > > ---
> > > > > > > arch/riscv/lib/andes_plic.c | 11 +++
> > > > > > > 1 file changed, 7 insertions(+), 4 deletions(-)
> > > > > > >
> > > > > > > diff --git a/arch/riscv/lib/andes_plic.c
> > > > > > > b/arch/riscv/lib/andes_plic.c
> > > > > > > index 28568e4..42394b9 100644
> > > > > > > --- a/arch/riscv/lib/andes_plic.c
> > > > > > > +++ b/arch/riscv/lib/andes_plic.c
> > > > > > > @@ -19,7 +19,7 @@
> > > > > > > #include
> > > > > > >
> > > > > > > /* pending register */
> > > > > > > -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > > > (hart) * 8)
> > > > > > > +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > > > ((hart) / 4) * 4)
> > > > > > > /* enable register */
> > > > > > > #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart)
> > > > > > > * 0x80)
> > > > > > > /* claim register */
> > > > > > > @@ -46,7 +46,7 @@ static int init_plic(void);
> > > > > > >
> > > > > > > static int enable_ipi(int hart)
> > > > > > > {
> > > > > > > - int en;
> > > > > > > + unsigned int en;
> > > > > >
> > > > > > Is this for some compiler warning fix?
> > > > >
> > > > > No, it is not a warning fix. It is a bug fix.
> > > > > I hope en can be 0x80808080 instead of 0x80808080,
> > > >
> > > > But it is int, which is only 32-bit. The example you gave was a 64-bit
> > > > number.
> > > >
> > >
> > > Please consider the following simple program:
> > >
> > > > #define MASK 0x80808080
> > > >int main(){
> > > >int en;
> > > >en = MASK;
> > > >printf("%x, shifted %x\n", en, en >> 1);
> > > >return 0;
> > > >}
> > >
> > > Would you mind sharing what you get after running this on your x86_64
> > > (if you have one) computer?
Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Alan,
On Thu, Oct 31, 2019 at 9:00 AM Alan Kao wrote:
>
> Hi Bin,
>
> Thanks for the critics. Comments below.
> On Wed, Oct 30, 2019 at 06:38:00PM +0800, Bin Meng wrote:
> > Hi Rick,
> >
> > On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
> > >
> > > Hi Bin
> > >
> > > >
> > > > Hi Rick,
> > > >
> > > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > > > >
> > > > > From: Rick Chen
> > > > >
> > > > > It will work fine due to hart 0 always will be main
> > > > > hart coincidentally. When develop SPL flow, I try to
> > > > > force other harts to be main hart. And it will go
> > > > > wrong in sending IPI flow. So fix it.
> > > >
> > > > Fix what? Does this commit contain 2 fixes, or just 1 fix?
> > >
> > > Yes, it include two fixs. But they will cause one negative result
> > > that only hart 0 can send ipi to other harts.
> > >
> > > >
> > > > >
> > > > > Having this fix, any hart can be main hart in U-Boot SPL
> > > > > theoretically, but it still fail somewhere. After dig in
> > > > > and found there is an assumption that hart 0 shall be
> > > > > main hart in OpenSbi.
> > > >
> > > > So does this mean there is a bug in OpenSBI too?
> > >
> > > I am not sure if it is a bug. Maybe it is a compatible issue.
> > > There is a limitation that only hart 0 can be main hart in OpenSBI.
> >
> > I don't think OpenSBI has such limitation.
> >
>
> Please check the source.
> https://github.com/riscv/opensbi/blob/master/firmware/fw_base.S#L54
>
> Apparently, the FIRST TWO LINEs of the initialization are the
> 1. get hart ID.
> 2. determine which route to take based on their ID respectively.
>
This is true only for the very first a few instructions when OpenSBI
boots. Later OpenSBI main initialization does not require hart to be
zero.
> So, I do think OpenSBI has this signature, if you are not willing to call it
> a limitation.
>
> > > But any hart can be main hart in U-Boot.
> > >
> > > In general case, hart 0 will be main and it is fine when U-Boot jump ot
> > > OpenSBI.
> > > But if we force hart 1 to be main hart, when hart 0 jump to OPenSBI from
> > > U-Boot,
> > > It will do relocation flow in OpenSBI which willcorrupt U-Boot SPL,
> > > but hart 0 still in U-Boot SPL.
> > >
> > > >
> > > > >
> > > > > After some work-arounds, it can pass the verifications
> > > > > that any hart can be main hart and boots U-Boot SPL ->
> > > > > OpenSbi -> U-Boot proper -> Linux Kernel successfully.
> > > > >
> > > >
> > > > It's a bit hard for me to understand what was described here in the
> > > > commit message. Maybe you need rewrite something.
> > >
> > > OK. I will rewrite this commit message.
> > >
> > > >
> > > > > Signed-off-by: Rick Chen
> > > > > Cc: KC Lin
> > > > > Cc: Alan Kao
> > > > > ---
> > > > > arch/riscv/lib/andes_plic.c | 11 +++
> > > > > 1 file changed, 7 insertions(+), 4 deletions(-)
> > > > >
> > > > > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> > > > > index 28568e4..42394b9 100644
> > > > > --- a/arch/riscv/lib/andes_plic.c
> > > > > +++ b/arch/riscv/lib/andes_plic.c
> > > > > @@ -19,7 +19,7 @@
> > > > > #include
> > > > >
> > > > > /* pending register */
> > > > > -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > (hart) * 8)
> > > > > +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > > ((hart) / 4) * 4)
> > > > > /* enable register */
> > > > > #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) *
> > > > > 0x80)
> > > > > /* claim register */
> > > > > @@ -46,7 +46,7 @@ static int init_plic(void);
> > > > >
> > > > > static int enable_ipi(int hart)
> > > > > {
> > > > > - int en;
> > > > > + unsigned int en;
> > > >
> > > > Is this for some compiler warning fix?
> > >
> > > No, it is not a warning fix. It is a bug fix.
> > > I hope en can be 0x80808080 instead of 0x80808080,
> >
> > But it is int, which is only 32-bit. The example you gave was a 64-bit
> > number.
> >
>
> Please consider the following simple program:
>
> > #define MASK 0x80808080
> >int main(){
> >int en;
> >en = MASK;
> >printf("%x, shifted %x\n", en, en >> 1);
> >return 0;
> >}
>
> Would you mind sharing what you get after running this on your x86_64
> (if you have one) computer? Really appreiciate that.
>
> The almost identical episode is in the patch, specifically,
> > en = ENABLE_HART_IPI >> hart
Yes, this is a bug. But I was confused by Rick's comments as he was
using a 64-bit number as int is never to be a 64-bit for both 32-bit
and 64-bit.
Regards,
Bin
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Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Bin
>
> Hi Rick,
>
> On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
> >
> > Hi Bin
> >
> > >
> > > Hi Rick,
> > >
> > > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > > >
> > > > From: Rick Chen
> > > >
> > > > It will work fine due to hart 0 always will be main
> > > > hart coincidentally. When develop SPL flow, I try to
> > > > force other harts to be main hart. And it will go
> > > > wrong in sending IPI flow. So fix it.
> > >
> > > Fix what? Does this commit contain 2 fixes, or just 1 fix?
> >
> > Yes, it include two fixs. But they will cause one negative result
> > that only hart 0 can send ipi to other harts.
> >
> > >
> > > >
> > > > Having this fix, any hart can be main hart in U-Boot SPL
> > > > theoretically, but it still fail somewhere. After dig in
> > > > and found there is an assumption that hart 0 shall be
> > > > main hart in OpenSbi.
> > >
> > > So does this mean there is a bug in OpenSBI too?
> >
> > I am not sure if it is a bug. Maybe it is a compatible issue.
> > There is a limitation that only hart 0 can be main hart in OpenSBI.
>
> I don't think OpenSBI has such limitation.
OK.
But there is a hint in OpenSBI indeed.
Maybe it is just different interpretation each other.
/*
* Jump to warm-boot if this is not the first core booting,
* that is, for mhartid != 0
*/
>
> > But any hart can be main hart in U-Boot.
> >
> > In general case, hart 0 will be main and it is fine when U-Boot jump ot
> > OpenSBI.
> > But if we force hart 1 to be main hart, when hart 0 jump to OPenSBI from
> > U-Boot,
> > It will do relocation flow in OpenSBI which willcorrupt U-Boot SPL,
> > but hart 0 still in U-Boot SPL.
> >
> > >
> > > >
> > > > After some work-arounds, it can pass the verifications
> > > > that any hart can be main hart and boots U-Boot SPL ->
> > > > OpenSbi -> U-Boot proper -> Linux Kernel successfully.
> > > >
> > >
> > > It's a bit hard for me to understand what was described here in the
> > > commit message. Maybe you need rewrite something.
> >
> > OK. I will rewrite this commit message.
> >
> > >
> > > > Signed-off-by: Rick Chen
> > > > Cc: KC Lin
> > > > Cc: Alan Kao
> > > > ---
> > > > arch/riscv/lib/andes_plic.c | 11 +++
> > > > 1 file changed, 7 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> > > > index 28568e4..42394b9 100644
> > > > --- a/arch/riscv/lib/andes_plic.c
> > > > +++ b/arch/riscv/lib/andes_plic.c
> > > > @@ -19,7 +19,7 @@
> > > > #include
> > > >
> > > > /* pending register */
> > > > -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > (hart) * 8)
> > > > +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 +
> > > > ((hart) / 4) * 4)
> > > > /* enable register */
> > > > #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
> > > > /* claim register */
> > > > @@ -46,7 +46,7 @@ static int init_plic(void);
> > > >
> > > > static int enable_ipi(int hart)
> > > > {
> > > > - int en;
> > > > + unsigned int en;
> > >
> > > Is this for some compiler warning fix?
> >
> > No, it is not a warning fix. It is a bug fix.
> > I hope en can be 0x80808080 instead of 0x80808080,
>
> But it is int, which is only 32-bit. The example you gave was a 64-bit number.
The verification runs on RV64, so it is a 64-bit number example.
Thanks
Rick
>
> > or it will cause IPI sending errors.
> >
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Rick,
On Wed, Oct 30, 2019 at 10:50 AM Rick Chen wrote:
>
> Hi Bin
>
> >
> > Hi Rick,
> >
> > On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> > >
> > > From: Rick Chen
> > >
> > > It will work fine due to hart 0 always will be main
> > > hart coincidentally. When develop SPL flow, I try to
> > > force other harts to be main hart. And it will go
> > > wrong in sending IPI flow. So fix it.
> >
> > Fix what? Does this commit contain 2 fixes, or just 1 fix?
>
> Yes, it include two fixs. But they will cause one negative result
> that only hart 0 can send ipi to other harts.
>
> >
> > >
> > > Having this fix, any hart can be main hart in U-Boot SPL
> > > theoretically, but it still fail somewhere. After dig in
> > > and found there is an assumption that hart 0 shall be
> > > main hart in OpenSbi.
> >
> > So does this mean there is a bug in OpenSBI too?
>
> I am not sure if it is a bug. Maybe it is a compatible issue.
> There is a limitation that only hart 0 can be main hart in OpenSBI.
I don't think OpenSBI has such limitation.
> But any hart can be main hart in U-Boot.
>
> In general case, hart 0 will be main and it is fine when U-Boot jump ot
> OpenSBI.
> But if we force hart 1 to be main hart, when hart 0 jump to OPenSBI from
> U-Boot,
> It will do relocation flow in OpenSBI which willcorrupt U-Boot SPL,
> but hart 0 still in U-Boot SPL.
>
> >
> > >
> > > After some work-arounds, it can pass the verifications
> > > that any hart can be main hart and boots U-Boot SPL ->
> > > OpenSbi -> U-Boot proper -> Linux Kernel successfully.
> > >
> >
> > It's a bit hard for me to understand what was described here in the
> > commit message. Maybe you need rewrite something.
>
> OK. I will rewrite this commit message.
>
> >
> > > Signed-off-by: Rick Chen
> > > Cc: KC Lin
> > > Cc: Alan Kao
> > > ---
> > > arch/riscv/lib/andes_plic.c | 11 +++
> > > 1 file changed, 7 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> > > index 28568e4..42394b9 100644
> > > --- a/arch/riscv/lib/andes_plic.c
> > > +++ b/arch/riscv/lib/andes_plic.c
> > > @@ -19,7 +19,7 @@
> > > #include
> > >
> > > /* pending register */
> > > -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + (hart)
> > > * 8)
> > > +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + ((hart)
> > > / 4) * 4)
> > > /* enable register */
> > > #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
> > > /* claim register */
> > > @@ -46,7 +46,7 @@ static int init_plic(void);
> > >
> > > static int enable_ipi(int hart)
> > > {
> > > - int en;
> > > + unsigned int en;
> >
> > Is this for some compiler warning fix?
>
> No, it is not a warning fix. It is a bug fix.
> I hope en can be 0x80808080 instead of 0x80808080,
But it is int, which is only 32-bit. The example you gave was a 64-bit number.
> or it will cause IPI sending errors.
>
Regards,
Bin
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Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Bin
>
> Hi Rick,
>
> On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
> >
> > From: Rick Chen
> >
> > It will work fine due to hart 0 always will be main
> > hart coincidentally. When develop SPL flow, I try to
> > force other harts to be main hart. And it will go
> > wrong in sending IPI flow. So fix it.
>
> Fix what? Does this commit contain 2 fixes, or just 1 fix?
Yes, it include two fixs. But they will cause one negative result
that only hart 0 can send ipi to other harts.
>
> >
> > Having this fix, any hart can be main hart in U-Boot SPL
> > theoretically, but it still fail somewhere. After dig in
> > and found there is an assumption that hart 0 shall be
> > main hart in OpenSbi.
>
> So does this mean there is a bug in OpenSBI too?
I am not sure if it is a bug. Maybe it is a compatible issue.
There is a limitation that only hart 0 can be main hart in OpenSBI.
But any hart can be main hart in U-Boot.
In general case, hart 0 will be main and it is fine when U-Boot jump ot OpenSBI.
But if we force hart 1 to be main hart, when hart 0 jump to OPenSBI from U-Boot,
It will do relocation flow in OpenSBI which willcorrupt U-Boot SPL,
but hart 0 still in U-Boot SPL.
>
> >
> > After some work-arounds, it can pass the verifications
> > that any hart can be main hart and boots U-Boot SPL ->
> > OpenSbi -> U-Boot proper -> Linux Kernel successfully.
> >
>
> It's a bit hard for me to understand what was described here in the
> commit message. Maybe you need rewrite something.
OK. I will rewrite this commit message.
>
> > Signed-off-by: Rick Chen
> > Cc: KC Lin
> > Cc: Alan Kao
> > ---
> > arch/riscv/lib/andes_plic.c | 11 +++
> > 1 file changed, 7 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> > index 28568e4..42394b9 100644
> > --- a/arch/riscv/lib/andes_plic.c
> > +++ b/arch/riscv/lib/andes_plic.c
> > @@ -19,7 +19,7 @@
> > #include
> >
> > /* pending register */
> > -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + (hart) *
> > 8)
> > +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + ((hart) /
> > 4) * 4)
> > /* enable register */
> > #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
> > /* claim register */
> > @@ -46,7 +46,7 @@ static int init_plic(void);
> >
> > static int enable_ipi(int hart)
> > {
> > - int en;
> > + unsigned int en;
>
> Is this for some compiler warning fix?
No, it is not a warning fix. It is a bug fix.
I hope en can be 0x80808080 instead of 0x80808080,
or it will cause IPI sending errors.
Thanks
Rick
>
> >
> > en = ENABLE_HART_IPI >> hart;
> > writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
> > @@ -94,10 +94,13 @@ static int init_plic(void)
> >
> > int riscv_send_ipi(int hart)
> > {
> > + unsigned int ipi;
> > +
> > PLIC_BASE_GET();
> >
> > - writel(SEND_IPI_TO_HART(hart),
> > - (void __iomem *)PENDING_REG(gd->arch.plic,
> > gd->arch.boot_hart));
> > + ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
> > + writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
> > + gd->arch.boot_hart));
> >
> > return 0;
> > }
> > --
>
> Regards,
> Bin
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Re: [U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations
Hi Rick,
On Fri, Oct 25, 2019 at 2:18 PM Andes wrote:
>
> From: Rick Chen
>
> It will work fine due to hart 0 always will be main
> hart coincidentally. When develop SPL flow, I try to
> force other harts to be main hart. And it will go
> wrong in sending IPI flow. So fix it.
Fix what? Does this commit contain 2 fixes, or just 1 fix?
>
> Having this fix, any hart can be main hart in U-Boot SPL
> theoretically, but it still fail somewhere. After dig in
> and found there is an assumption that hart 0 shall be
> main hart in OpenSbi.
So does this mean there is a bug in OpenSBI too?
>
> After some work-arounds, it can pass the verifications
> that any hart can be main hart and boots U-Boot SPL ->
> OpenSbi -> U-Boot proper -> Linux Kernel successfully.
>
It's a bit hard for me to understand what was described here in the
commit message. Maybe you need rewrite something.
> Signed-off-by: Rick Chen
> Cc: KC Lin
> Cc: Alan Kao
> ---
> arch/riscv/lib/andes_plic.c | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
> index 28568e4..42394b9 100644
> --- a/arch/riscv/lib/andes_plic.c
> +++ b/arch/riscv/lib/andes_plic.c
> @@ -19,7 +19,7 @@
> #include
>
> /* pending register */
> -#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + (hart) * 8)
> +#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + ((hart) /
> 4) * 4)
> /* enable register */
> #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
> /* claim register */
> @@ -46,7 +46,7 @@ static int init_plic(void);
>
> static int enable_ipi(int hart)
> {
> - int en;
> + unsigned int en;
Is this for some compiler warning fix?
>
> en = ENABLE_HART_IPI >> hart;
> writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
> @@ -94,10 +94,13 @@ static int init_plic(void)
>
> int riscv_send_ipi(int hart)
> {
> + unsigned int ipi;
> +
> PLIC_BASE_GET();
>
> - writel(SEND_IPI_TO_HART(hart),
> - (void __iomem *)PENDING_REG(gd->arch.plic,
> gd->arch.boot_hart));
> + ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
> + writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
> + gd->arch.boot_hart));
>
> return 0;
> }
> --
Regards,
Bin
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