Re: [uClinux-dev] [PATCH] m68knommu: add support for Coldfire MCF547x/MCF548x interrupt controller.
Hi Philippe, Philippe De Muyter wrote: On Fri, Aug 27, 2010 at 04:22:13PM +1000, Greg Ungerer wrote: Hi Philippe, Philippe De Muyter wrote: The Coldfire MCF547x/MCF548x have the same interrupt controller than the MCF528x, e.g., but only one, not two as in the MCF528x. Modify intc-2.c to support only one interrupt controller if MCFICM_INTC1 is not defined. Signed-off-by: Philippe De Muyter --- arch/m68knommu/platform/coldfire/intc-2.c | 30 +++- 1 files changed, 24 insertions(+), 6 deletions(-) diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c index a0c72ec..060ff7b 100644 --- a/arch/m68knommu/platform/coldfire/intc-2.c +++ b/arch/m68knommu/platform/coldfire/intc-2.c @@ -1,9 +1,11 @@ /* * intc-2.c * - * General interrupt controller code for the many ColdFire version 2 cores - * that use the two region INTC interrupt controller. This includes the - * 523x family, 5270, 5271, 5274, 5275, and the 528x families. + * General interrupt controller code for the many ColdFire cores that use + * interrupt controllers with 63 interrupt sources, organized as 56 fully- + * programmable + 7 fixed-level interrupt sources. This includes the 523x + * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such + * controllers, and the 547x and 548x families which have only one of them. * * (C) Copyright 2009, Greg Ungerer * @@ -27,17 +29,27 @@ * We don't really care so much what they are, we don't rely on the * tranditional priority interrupt scheme of the m68k/ColdFire. */ -static u8 intc_intpri = 0x36; +static u8 intc_intpri = 066; ^^^ Why change this to octal? Because it reflects the organisation of the ICRn registers : 2 bits unused 3 bits for level 3 bits for priority in level Do you want me to add a comment ? I think we should leave it the way it was :-) Irrespective of encoding most headers use hex to define bit fields. Grepping through arch/m68k/include/asm the only exception to this is termbits.h - and that is completely historical. Regards Greg Greg Ungerer -- Principal EngineerEMAIL: g...@snapgear.com SnapGear Group, McAfee PHONE: +61 7 3435 2888 8 Gardner Close FAX: +61 7 3217 5323 Milton, QLD, 4064, AustraliaWEB: http://www.SnapGear.com ___ uClinux-dev mailing list uClinux-dev@uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev@uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev
Re: [uClinux-dev] [PATCH] m68knommu: add support for Coldfire MCF547x/MCF548x interrupt controller.
On Fri, Aug 27, 2010 at 04:22:13PM +1000, Greg Ungerer wrote: > > Hi Philippe, > > Philippe De Muyter wrote: >> The Coldfire MCF547x/MCF548x have the same interrupt controller than >> the MCF528x, e.g., but only one, not two as in the MCF528x. Modify >> intc-2.c to support only one interrupt controller if MCFICM_INTC1 is >> not defined. >> Signed-off-by: Philippe De Muyter >> --- >> arch/m68knommu/platform/coldfire/intc-2.c | 30 >> +++- >> 1 files changed, 24 insertions(+), 6 deletions(-) >> diff --git a/arch/m68knommu/platform/coldfire/intc-2.c >> b/arch/m68knommu/platform/coldfire/intc-2.c >> index a0c72ec..060ff7b 100644 >> --- a/arch/m68knommu/platform/coldfire/intc-2.c >> +++ b/arch/m68knommu/platform/coldfire/intc-2.c >> @@ -1,9 +1,11 @@ >> /* >> * intc-2.c >> * >> - * General interrupt controller code for the many ColdFire version 2 >> cores >> - * that use the two region INTC interrupt controller. This includes the >> - * 523x family, 5270, 5271, 5274, 5275, and the 528x families. >> + * General interrupt controller code for the many ColdFire cores that use >> + * interrupt controllers with 63 interrupt sources, organized as 56 >> fully- >> + * programmable + 7 fixed-level interrupt sources. This includes the 523x >> + * family, the 5270, 5271, 5274, 5275, and the 528x family which have two >> such >> + * controllers, and the 547x and 548x families which have only one of >> them. >> * >> * (C) Copyright 2009, Greg Ungerer >> * >> @@ -27,17 +29,27 @@ >> * We don't really care so much what they are, we don't rely on the >> * tranditional priority interrupt scheme of the m68k/ColdFire. >> */ >> -static u8 intc_intpri = 0x36; >> +static u8 intc_intpri = 066; >^^^ > Why change this to octal? Because it reflects the organisation of the ICRn registers : 2 bits unused 3 bits for level 3 bits for priority in level Do you want me to add a comment ? Philippe -- Philippe De Muyter phdm at macqel dot be Tel +32 27029044 Macq Electronique SA rue de l'Aeronef 2 B-1140 Bruxelles Fax +32 27029077 ___ uClinux-dev mailing list uClinux-dev@uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev@uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev
Re: [uClinux-dev] [PATCH] m68knommu: add support for Coldfire MCF547x/MCF548x interrupt controller.
Hi Philippe, Philippe De Muyter wrote: The Coldfire MCF547x/MCF548x have the same interrupt controller than the MCF528x, e.g., but only one, not two as in the MCF528x. Modify intc-2.c to support only one interrupt controller if MCFICM_INTC1 is not defined. Signed-off-by: Philippe De Muyter --- arch/m68knommu/platform/coldfire/intc-2.c | 30 +++- 1 files changed, 24 insertions(+), 6 deletions(-) diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c index a0c72ec..060ff7b 100644 --- a/arch/m68knommu/platform/coldfire/intc-2.c +++ b/arch/m68knommu/platform/coldfire/intc-2.c @@ -1,9 +1,11 @@ /* * intc-2.c * - * General interrupt controller code for the many ColdFire version 2 cores - * that use the two region INTC interrupt controller. This includes the - * 523x family, 5270, 5271, 5274, 5275, and the 528x families. + * General interrupt controller code for the many ColdFire cores that use + * interrupt controllers with 63 interrupt sources, organized as 56 fully- + * programmable + 7 fixed-level interrupt sources. This includes the 523x + * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such + * controllers, and the 547x and 548x families which have only one of them. * * (C) Copyright 2009, Greg Ungerer * @@ -27,17 +29,27 @@ * We don't really care so much what they are, we don't rely on the * tranditional priority interrupt scheme of the m68k/ColdFire. */ -static u8 intc_intpri = 0x36; +static u8 intc_intpri = 066; ^^^ Why change this to octal? Otherwise looks ok. Regards Greg + +#ifdef MCFICM_INTC1 +#define NR_VECS128 +#else +#define NR_VECS64 +#endif static void intc_irq_mask(unsigned int irq) { - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) { unsigned long imraddr; u32 val, imrbit; irq -= MCFINT_VECBASE; imraddr = MCF_IPSBAR; +#ifdef MCFICM_INTC1 imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; +#else + imraddr += MCFICM_INTC0; +#endif imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; imrbit = 0x1 << (irq & 0x1f); @@ -48,13 +60,17 @@ static void intc_irq_mask(unsigned int irq) static void intc_irq_unmask(unsigned int irq) { - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) { unsigned long intaddr, imraddr, icraddr; u32 val, imrbit; irq -= MCFINT_VECBASE; intaddr = MCF_IPSBAR; +#ifdef MCFICM_INTC1 intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; +#else + intaddr += MCFICM_INTC0; +#endif imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f); imrbit = 0x1 << (irq & 0x1f); @@ -85,7 +101,9 @@ void __init init_IRQ(void) /* Mask all interrupt sources */ __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL); +#ifdef MCFICM_INTC1 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL); +#endif for (irq = 0; (irq < NR_IRQS); irq++) { irq_desc[irq].status = IRQ_DISABLED; -- Greg Ungerer -- Principal EngineerEMAIL: g...@snapgear.com SnapGear Group, McAfee PHONE: +61 7 3435 2888 8 Gardner Close FAX: +61 7 3217 5323 Milton, QLD, 4064, AustraliaWEB: http://www.SnapGear.com ___ uClinux-dev mailing list uClinux-dev@uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev@uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev
[uClinux-dev] [PATCH] m68knommu: add support for Coldfire MCF547x/MCF548x interrupt controller.
The Coldfire MCF547x/MCF548x have the same interrupt controller than the MCF528x, e.g., but only one, not two as in the MCF528x. Modify intc-2.c to support only one interrupt controller if MCFICM_INTC1 is not defined. Signed-off-by: Philippe De Muyter --- arch/m68knommu/platform/coldfire/intc-2.c | 30 +++- 1 files changed, 24 insertions(+), 6 deletions(-) diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c index a0c72ec..060ff7b 100644 --- a/arch/m68knommu/platform/coldfire/intc-2.c +++ b/arch/m68knommu/platform/coldfire/intc-2.c @@ -1,9 +1,11 @@ /* * intc-2.c * - * General interrupt controller code for the many ColdFire version 2 cores - * that use the two region INTC interrupt controller. This includes the - * 523x family, 5270, 5271, 5274, 5275, and the 528x families. + * General interrupt controller code for the many ColdFire cores that use + * interrupt controllers with 63 interrupt sources, organized as 56 fully- + * programmable + 7 fixed-level interrupt sources. This includes the 523x + * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such + * controllers, and the 547x and 548x families which have only one of them. * * (C) Copyright 2009, Greg Ungerer * @@ -27,17 +29,27 @@ * We don't really care so much what they are, we don't rely on the * tranditional priority interrupt scheme of the m68k/ColdFire. */ -static u8 intc_intpri = 0x36; +static u8 intc_intpri = 066; + +#ifdef MCFICM_INTC1 +#define NR_VECS128 +#else +#define NR_VECS64 +#endif static void intc_irq_mask(unsigned int irq) { - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) { unsigned long imraddr; u32 val, imrbit; irq -= MCFINT_VECBASE; imraddr = MCF_IPSBAR; +#ifdef MCFICM_INTC1 imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; +#else + imraddr += MCFICM_INTC0; +#endif imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; imrbit = 0x1 << (irq & 0x1f); @@ -48,13 +60,17 @@ static void intc_irq_mask(unsigned int irq) static void intc_irq_unmask(unsigned int irq) { - if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { + if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) { unsigned long intaddr, imraddr, icraddr; u32 val, imrbit; irq -= MCFINT_VECBASE; intaddr = MCF_IPSBAR; +#ifdef MCFICM_INTC1 intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; +#else + intaddr += MCFICM_INTC0; +#endif imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f); imrbit = 0x1 << (irq & 0x1f); @@ -85,7 +101,9 @@ void __init init_IRQ(void) /* Mask all interrupt sources */ __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL); +#ifdef MCFICM_INTC1 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL); +#endif for (irq = 0; (irq < NR_IRQS); irq++) { irq_desc[irq].status = IRQ_DISABLED; -- 1.6.3.3 ___ uClinux-dev mailing list uClinux-dev@uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev@uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev