[Xen-devel] [PATCH v4 4/4] x86/cpuid: Enable new SSE/AVX/AVX512 cpu features

2018-01-03 Thread Yang Zhong
Intel IceLake cpu has added new cpu features: AVX512VBMI2/GFNI/
VAES/AVX512VNNI/AVX512BITALG/VPCLMULQDQ. Those new cpu features
need expose to guest.

The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512VBMI2
CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI
CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES
CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512VNNI
CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Yang Zhong 
Acked-by: Jan Beulich 
---
 docs/man/xl.cfg.pod.5.in|  3 ++-
 tools/libxl/libxl_cpuid.c   |  6 ++
 tools/misc/xen-cpuid.c  | 12 +++-
 xen/include/public/arch-x86/cpufeatureset.h |  6 ++
 xen/tools/gen-cpuid.py  |  3 ++-
 5 files changed, 23 insertions(+), 7 deletions(-)

diff --git a/docs/man/xl.cfg.pod.5.in b/docs/man/xl.cfg.pod.5.in
index b7b91d8..d056768 100644
--- a/docs/man/xl.cfg.pod.5.in
+++ b/docs/man/xl.cfg.pod.5.in
@@ -1731,7 +1731,8 @@ perfctr_core perfctr_nb pge pku popcnt pse pse36 psn 
rdrand rdseed rdtscp rtm
 sha skinit smap smep smx ss sse sse2 sse3 sse4.1 sse4.2 sse4_1 sse4_2 sse4a
 ssse3 svm svm_decode svm_lbrv svm_npt svm_nrips svm_pausefilt svm_tscrate
 svm_vmcbclean syscall sysenter tbm tm tm2 topoext tsc tsc-deadline tsc_adjust
-umip vme vmx wdt x2apic xop xsave xtpr
+umip vme vmx wdt x2apic xop xsave xtpr avx512_vbmi2 gfni vaes vpclmulqdq
+avx512_vnni avx512_bitalg
 
 
 The xend syntax is a list of values in the form of
diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c
index e692b61..614991f 100644
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -199,6 +199,12 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list 
*cpuid, const char* str)
 {"umip", 0x0007,  0, CPUID_REG_ECX,  2,  1},
 {"pku",  0x0007,  0, CPUID_REG_ECX,  3,  1},
 {"ospke",0x0007,  0, CPUID_REG_ECX,  4,  1},
+{"avx512_vbmi2", 0x0007,  0, CPUID_REG_ECX,  6,  1},
+{"gfni", 0x0007,  0, CPUID_REG_ECX,  8,  1},
+{"vaes", 0x0007,  0, CPUID_REG_ECX,  9,  1},
+{"vpclmulqdq",   0x0007,  0, CPUID_REG_ECX, 10,  1},
+{"avx512_vnni",  0x0007,  0, CPUID_REG_ECX, 11,  1},
+{"avx512_bitalg",0x0007,  0, CPUID_REG_ECX, 12,  1},
 
 {"avx512-4vnniw",0x0007,  0, CPUID_REG_EDX,  2,  1},
 {"avx512-4fmaps",0x0007,  0, CPUID_REG_EDX,  3,  1},
diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index 0831f75..ef15252 100644
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -120,11 +120,13 @@ static const char *str_Da1[32] =
 
 static const char *str_7c0[32] =
 {
-[ 0] = "prechwt1", [ 1] = "avx512vbmi",
-[ 2] = "umip", [ 3] = "pku",
-[ 4] = "ospke",
-
-[5 ... 13] = "REZ",
+[ 0] = "prechwt1", [ 1] = "avx512vbmi",
+[ 2] = "umip", [ 3] = "pku",
+[ 4] = "ospke",[ 5] = "REZ",
+[ 6] = "avx512_vbmi2", [ 7] = "REZ",
+[ 8] = "gfni", [ 9] = "vaes",
+[10] = "vpclmulqdq",   [11] = "avx512_vnni",
+[12] = "avx512_bitalg",[13] = "REZ",
 
 [14] = "avx512_vpopcntdq",
 
diff --git a/xen/include/public/arch-x86/cpufeatureset.h 
b/xen/include/public/arch-x86/cpufeatureset.h
index be6da8e..85ad59a 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -228,6 +228,12 @@ XEN_CPUFEATURE(AVX512VBMI,6*32+ 1) /*A  AVX-512 Vector 
Byte Manipulation Ins
 XEN_CPUFEATURE(UMIP,  6*32+ 2) /*S  User Mode Instruction Prevention */
 XEN_CPUFEATURE(PKU,   6*32+ 3) /*H  Protection Keys for Userspace */
 XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*!  OS Protection Keys Enable */
+XEN_CPUFEATURE(AVX512_VBMI2,  6*32+ 6) /*A  addition AVX-512 VBMI Instructions 
*/
+XEN_CPUFEATURE(GFNI,  6*32+ 8) /*A  Galois Field New Instructions */
+XEN_CPUFEATURE(VAES,  6*32+ 9) /*A  Vector AES instructions */
+XEN_CPUFEATURE(VPCLMULQDQ,6*32+ 10) /*A  vector PCLMULQDQ instructions */
+XEN_CPUFEATURE(AVX512_VNNI,   6*32+ 11) /*A  Vector Neural Network 
Instructions */
+XEN_CPUFEATURE(AVX512_BITALG, 6*32+ 12) /*A  support for VPOPCNT[B,W] and 
VPSHUFBITQMB */
 XEN_CPUFEATURE(AVX512_VPOPCNTDQ, 6*32+14) /*A  POPCNT for vectors of DW/QW */
 XEN_CPUFEATURE(RDPID, 6*32+22) /*A  RDPID instruction */
 
diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index 9ec4486..be8df48 100755
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -255,7 +255,8 @@ def crunch_numbers(state):
 # top of AVX512F
 AVX512F: [AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD,
   AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW,
-  AVX512_4FMAPS, AVX512_VPOPCNTDQ],
+

Re: [Xen-devel] [PATCH v4 4/4] x86/cpuid: Enable new SSE/AVX/AVX512 cpu features

2018-01-03 Thread Jan Beulich
>>> On 03.01.18 at 09:26,  wrote:
> Intel IceLake cpu has added new cpu features: AVX512VBMI2/GFNI/
> VAES/AVX512VNNI/AVX512BITALG/VPCLMULQDQ. Those new cpu features
> need expose to guest.
> 
> The bit definition:
> CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512VBMI2
> CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI
> CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES
> CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
> CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512VNNI
> CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
> 
> The release document ref below link:
> https://software.intel.com/sites/default/files/managed/c5/15/\ 
> architecture-instruction-set-extensions-programming-reference.pdf
> 
> Signed-off-by: Yang Zhong 
> Acked-by: Jan Beulich 

I have to withdraw my ack here.

> --- a/xen/include/public/arch-x86/cpufeatureset.h
> +++ b/xen/include/public/arch-x86/cpufeatureset.h
> @@ -228,6 +228,12 @@ XEN_CPUFEATURE(AVX512VBMI,6*32+ 1) /*A  AVX-512 
> Vector Byte Manipulation Ins
>  XEN_CPUFEATURE(UMIP,  6*32+ 2) /*S  User Mode Instruction Prevention 
> */
>  XEN_CPUFEATURE(PKU,   6*32+ 3) /*H  Protection Keys for Userspace */
>  XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*!  OS Protection Keys Enable */
> +XEN_CPUFEATURE(AVX512_VBMI2,  6*32+ 6) /*A  addition AVX-512 VBMI 
> Instructions */

"additional"?

> --- a/xen/tools/gen-cpuid.py
> +++ b/xen/tools/gen-cpuid.py
> @@ -255,7 +255,8 @@ def crunch_numbers(state):
>  # top of AVX512F
>  AVX512F: [AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD,
>AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW,
> -  AVX512_4FMAPS, AVX512_VPOPCNTDQ],
> +  AVX512_4FMAPS, AVX512_VPOPCNTDQ, AVX512_VBMI2,
> +  AVX512_VNNI, AVX512_BITALG],
>  }

This is insufficient afaict: VAES and VPCLMULQDQ ought to be
made dependent upon AVX.

Jan


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Re: [Xen-devel] [PATCH v4 4/4] x86/cpuid: Enable new SSE/AVX/AVX512 cpu features

2018-01-03 Thread Yang Zhong
On Wed, Jan 03, 2018 at 01:46:09AM -0700, Jan Beulich wrote:

> > --- a/xen/include/public/arch-x86/cpufeatureset.h
> > +++ b/xen/include/public/arch-x86/cpufeatureset.h
> > @@ -228,6 +228,12 @@ XEN_CPUFEATURE(AVX512VBMI,6*32+ 1) /*A  AVX-512 
> > Vector Byte Manipulation Ins
> >  XEN_CPUFEATURE(UMIP,  6*32+ 2) /*S  User Mode Instruction 
> > Prevention */
> >  XEN_CPUFEATURE(PKU,   6*32+ 3) /*H  Protection Keys for Userspace 
> > */
> >  XEN_CPUFEATURE(OSPKE, 6*32+ 4) /*!  OS Protection Keys Enable */
> > +XEN_CPUFEATURE(AVX512_VBMI2,  6*32+ 6) /*A  addition AVX-512 VBMI 
> > Instructions */
> 
> "additional"?
  Jan, i will change "addition" to "additional", thanks! Yang.
 
> > --- a/xen/tools/gen-cpuid.py
> > +++ b/xen/tools/gen-cpuid.py
> > @@ -255,7 +255,8 @@ def crunch_numbers(state):
> >  # top of AVX512F
> >  AVX512F: [AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD,
> >AVX512BW, AVX512VL, AVX512VBMI, AVX512_4VNNIW,
> > -  AVX512_4FMAPS, AVX512_VPOPCNTDQ],
> > +  AVX512_4FMAPS, AVX512_VPOPCNTDQ, AVX512_VBMI2,
> > +  AVX512_VNNI, AVX512_BITALG],
> >  }
> 
> This is insufficient afaict: VAES and VPCLMULQDQ ought to be
> made dependent upon AVX.

  Thanks Jan, i will do below changes for this.  Yang.

-AVX: [FMA, FMA4, F16C, AVX2, XOP],
+AVX: [FMA, FMA4, F16C, AVX2, XOP, VAES, VPCLMULQDQ],

> 
> Jan

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