[AMD Official Use Only]
For quick workaround, I agree with the solution. But regarding the root cause,
the list is still messed up.
Can we make ras_list to be a global variable across all cards, and add list
empty check (or add a flag to indicate the register status of ras block) before
list ad
On Fri, Jan 28, 2022 at 06:43:23PM +0800, Yu, Lang wrote:
> We observed a GPU hang when querying GMC CG state(i.e.,
> cat amdgpu_pm_info) on cyan skillfish. Acctually, cyan
> skillfish doesn't support any CG features.
>
> Just prevent cyan skillfish from accessing GMC CG registers.
>
> Signed-off
OK
-Original Message-
From: Chen, Guchun
Sent: Saturday, January 29, 2022 12:02 PM
To: Chai, Thomas ; amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Zhang, Hawking ;
Clements, John ; Chai, Thomas ;
Chai, Thomas
Subject: RE: [PATCH] drm/amdgpu: Add judgement to avoid infinite loop
[Pu
[AMD Official Use Only]
Reviewed-by: John Clements
-Original Message-
From: Chai, Thomas
Sent: Saturday, January 29, 2022 11:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Chai, Thomas ; Zhang, Hawking ;
Zhou1, Tao ; Clements, John ; Chai,
Thomas
Subject: [PATCH] drm/amdgpu: Add judgem
[Public]
Please add a Fixes tag, as it should fix a regression from former patch.
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of yipechai
Sent: Saturday, January 29, 2022 11:53 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Zhang, Hawking ;
Clements, John ; Chai,
1. The infinite loop causing soft lock occurs on multiple amdgpu cards
supporting ras feature.
2. This a workaround patch. It is valid for multiple amdgpu cards of the
same type.
3. The root cause is that each GPU card device has a separate .ras_list
link header, but the instance and linke
[Public]
> -Original Message-
> From: amd-gfx On Behalf Of Agustin
> Gutierrez
> Sent: 2022/January/28, Friday 6:07 PM
> To: amd-gfx@lists.freedesktop.org; Gutierrez, Agustin
>
> Cc: Gutierrez, Agustin
> Subject: [PATCH] drm/amd/display: Update watermark values for DCN301
>
> [Why]
[Why]
There is underflow / visual corruption DCN301, for high
bandwidth MST DSC configurations such as 2x1440p144 or 2x4k60.
[How]
Use up-to-date watermark values for DCN301.
Signed-off-by: Agustin Gutierrez
---
.../amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c | 16 -
On Fri, Jan 28, 2022 at 03:08:33PM +0900, Tomohito Esaki wrote:
> Some drivers whose planes only support linear layout fb do not support format
> modifiers.
> These drivers should support modifiers, however the DRM core should handle
> this
> rather than open-coding in every driver.
>
> In this p
Test cases such as migrate_fault and migrate_multiple, were modified to
explicit migrate from device to sys memory without the need of page
faults, when using device coherent type.
Snapshot test case updated to read memory device type first and based
on that, get the proper returned results migrat
Add two more parameters to set spm_addr_dev0 & spm_addr_dev1
addresses. These two parameters configure the start SP
addresses for each device in test_hmm driver.
Consequently, this configures zone device type as coherent.
Signed-off-by: Alex Sierra
Acked-by: Felix Kuehling
Reviewed-by: Alistair
Coherent device type memory on VRAM to RAM migration, has similar access
as System RAM from the CPU. This flag sets the source from the sender.
Which in Coherent type case, should be set as
MIGRATE_VMA_SELECT_DEVICE_COHERENT.
Signed-off-by: Alex Sierra
Reviewed-by: Felix Kuehling
---
drivers/gp
Device Coherent type uses device memory that is coherently accesible by
the CPU. This could be shown as SP (special purpose) memory range
at the BIOS-e820 memory enumeration. If no SP memory is supported in
system, this could be faked by setting CONFIG_EFI_FAKE_MEMMAP.
Currently, test_hmm only sup
When CPU is connected throug XGMI, it has coherent
access to VRAM resource. In this case that resource
is taken from a table in the device gmc aperture base.
This resource is used along with the device type, which could
be DEVICE_PRIVATE or DEVICE_COHERENT to create the device
page map region.
Sig
new ioctl cmd added to query zone device type. This will be
used once the test_hmm adds zone device coherent type.
Signed-off-by: Alex Sierra
Acked-by: Felix Kuehling
Reviewed-by: Alistair Poppple
---
lib/test_hmm.c | 23 +--
lib/test_hmm_uapi.h | 8
2 files
In order to configure device coherent in test_hmm, two module parameters
should be passed, which correspond to the SP start address of each
device (2) spm_addr_dev0 & spm_addr_dev1. If no parameters are passed,
private device type is configured.
Signed-off-by: Alex Sierra
Acked-by: Felix Kuehling
Device memory that is cache coherent from device and CPU point of view.
This is used on platforms that have an advanced system bus (like CAPI
or CXL). Any page of a process can be migrated to such memory. However,
no one should be allowed to pin such memory so that it can always be
evicted.
Signed
Avoid long term pinning for Coherent device type pages. This could
interfere with their own device memory manager. For now, we are just
returning error for PIN_LONGTERM Coherent device type pages. Eventually,
these type of pages will get migrated to system memory, once the device
migration pages su
This case is used to migrate pages from device memory, back to system
memory. Device coherent type memory is cache coherent from device and CPU
point of view.
Signed-off-by: Alex Sierra
Acked-by: Felix Kuehling
---
v2:
condition added when migrations from device coherent pages.
---
include/linu
This patch series introduces MEMORY_DEVICE_COHERENT, a type of memory
owned by a device that can be mapped into CPU page tables like
MEMORY_DEVICE_GENERIC and can also be migrated like
MEMORY_DEVICE_PRIVATE.
Christoph, the suggestion to incorporate Ralph Campbell’s refcount
cleanup patch into our
Just a gentle ping if people have more comments on this patch set ?
Especially last 5 patches
as first 7 are exact same as V2 and we already went over them mostly.
Andrey
On 2022-01-25 17:37, Andrey Grodzovsky wrote:
This patchset is based on earlier work by Boris[1] that allowed to have an
or
Applied. Thanks!
Alex
On Fri, Jan 28, 2022 at 12:59 PM Harry Wentland wrote:
>
>
>
> On 2022-01-28 12:35, Colin Ian King wrote:
> > There are quite a few spelling mistakes in various function names
> > and error messages. Fix these.
> >
> > Signed-off-by: Colin Ian King
>
> Reviewed-by: Harry
Applied. thanks!
Alex
On Fri, Jan 28, 2022 at 2:19 AM wrote:
>
> From: Changcheng Deng
>
> 'amdgpu_dpm.h' included in 'arcturus_ppt.c' is duplicated.
>
> Reported-by: Zeal Robot
> Signed-off-by: Changcheng Deng
> ---
> drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 -
> 1 file change
There are quite a few spelling mistakes in various function names
and error messages. Fix these.
Signed-off-by: Colin Ian King
---
.../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 32 +--
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/a
Applied. Thanks!
Alex
On Fri, Jan 28, 2022 at 2:05 AM wrote:
>
> From: Changcheng Deng
>
> 'linux/pci.h' included in 'amdgpu_device.c' is duplicated.
>
> Reported-by: Zeal Robot
> Signed-off-by: Changcheng Deng
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
> 1 file changed, 1 de
On 2022-01-28 12:35, Colin Ian King wrote:
> There are quite a few spelling mistakes in various function names
> and error messages. Fix these.
>
> Signed-off-by: Colin Ian King
Reviewed-by: Harry Wentland
Harry
> ---
> .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 32 +-
Thank you, Alex for your persistence with this patch series. Fee free to
add my Acked-by to all the patches that don't already have my R-b. I
have done pretty through reviews of previous versions of those patches,
but obviously missed a lot of issues pointed out by real MM experts.
Thank you A
Just a gentle ping.
Andrey
From: Grodzovsky, Andrey
Sent: 26 January 2022 10:52
To: Christian König ; Koenig, Christian
; Lazar, Lijo ;
dri-de...@lists.freedesktop.org ;
amd-gfx@lists.freedesktop.org ; Chen, JingWen
Cc: Chen, Horace ; Liu, Monk
Subject: Re: [
Am 2022-01-28 um 10:16 schrieb Christian König:
We ran into the problem that clearing really larger buffer (60GiB) caused an
SDMA timeout.
Restructure the function to use the dst window instead of mapping the whole
buffer into the GART and then fill only 2MiB chunks at a time.
Signed-off-by:
[Public]
Acked-by: Alex Deucher
From: Chen, Guchun
Sent: Friday, January 28, 2022 10:19 AM
To: amd-gfx@lists.freedesktop.org ; Deucher,
Alexander ; Koenig, Christian
; Pan, Xinhui ; Zhang, Hawking
Cc: Chen, Guchun
Subject: [PATCH] drm/amdgpu: drop flood prin
A lot of below message are outputed in SRIOV case.
amdgpu: indirect registers access through rlcg is not supported
Also drop redundant ret set, as it's initialized to be false already.
Fixes: d4cd09ca9bce("drm/amdgpu: add helper to query rlcg reg access flag")
Signed-off-by: Guchun Chen
---
dri
We probably never trigger this, but the logic inside the check is
inverted.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_
We ran into the problem that clearing really larger buffer (60GiB) caused an
SDMA timeout.
Restructure the function to use the dst window instead of mapping the whole
buffer into the GART and then fill only 2MiB chunks at a time.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amd
On 1/28/22 08:06, Aditya Garg wrote:
Hi Alex
On 27-Jan-2022, at 11:06 PM, Alex Deucher wrote:
C style comments please.
Shall be fixed in v2
I'll let one of the display guys comment on
the rest of the patch. Seems reasonable, we have a similar quirk for
the Apple MBP 2017 15" Retina p
[Public]
> -Original Message-
> From: Sierra Guiza, Alejandro (Alex)
> Sent: Thursday, January 27, 2022 6:21 PM
> To: Andrew Morton
> Cc: Kuehling, Felix ; linux...@kvack.org;
> rcampb...@nvidia.com; linux-e...@vger.kernel.org; linux-
> x...@vger.kernel.org; amd-gfx@lists.freedesktop.org
[Public]
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Friday, January 28, 2022 2:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Quan, Evan
Subject: [PATCH V3 7/7] drm/amd/pm: revise the implementation of
smu_cmn_disable_all
[Public]
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Friday, January 28, 2022 2:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Quan, Evan
Subject: [PATCH V3 6/7] drm/amd/pm: avoid consecutive retrieving for enabled
ppfeatu
[Public]
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Friday, January 28, 2022 2:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Quan, Evan
Subject: [PATCH V3 5/7] drm/amd/pm: drop the cache for enabled ppfeatures
The follow
[AMD Official Use Only]
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Friday, January 28, 2022 2:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Quan, Evan
Subject: [PATCH V3 4/7] drm/amd/pm: correct the usage for 'supported'
[Public]
Reviewed-by: Alex Deucher
From: Quan, Evan
Sent: Friday, January 28, 2022 2:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lazar, Lijo
; Quan, Evan
Subject: [PATCH V3 2/7] drm/amd/pm: unify the interface for retrieving enabled
ppfea
I see, thanks for clarifying. So this is happening because we unmap the
HIQ with direct MMIO register writes instead of using the KIQ.
I'm OK with this patch as a workaround, but as a proper fix, we should
probably add a hiq_hqd_destroy function that uses KIQ, similar to how we
have hiq_mqd_l
[Public]
Reviewed-by: Alex Deucher
From: Lazar, Lijo
Sent: Friday, January 28, 2022 1:40 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander
; kernel test robot
Subject: [PATCH] drm/amdgpu: Fix uninitialized variable use warning
Fix u
[AMD Official Use Only]
Reviewed-By: Harish Kasiviswanathan
-Original Message-
From: amd-gfx On Behalf Of Philip Yang
Sent: Friday, January 28, 2022 9:39 AM
To: amd-gfx@lists.freedesktop.org
Cc: Yang, Philip
Subject: [PATCH 1/1] drm/amdkfd: Fix variable set but not used warning
All wa
[Public]
Reviewed-by: Alex Deucher
From: RyanLin
Sent: Thursday, January 27, 2022 10:47 PM
To: Wentland, Harry ; Li, Sun peng (Leo)
; Deucher, Alexander ; Koenig,
Christian ; david1.z...@amd.com
; airl...@linux.ie ; dan...@ffwll.ch
; seanp...@chromium.org ;
All warnings (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c: In function
'svm_range_deferred_list_work':
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.c:2067:22: warning:
variable 'p' set but not used [-Wunused-but-set-variable]
2067 | struct kfd_process *p;
On Thu, 27 Jan 2022 at 14:11, Arunpravin
wrote:
>
> - Remove drm_mm references and replace with drm buddy functionalities
> - Add res cursor support for drm buddy
>
> v2(Matthew Auld):
> - replace spinlock with mutex as we call kmem_cache_zalloc
> (..., GFP_KERNEL) in drm_buddy_alloc() funct
From: Aric Cyr
This version brings along following fixes:
- DC refactor and bug fixes for DP links
- Bug fixes for DP2
- Fix regressions causing display not light up
- Improved debug trace
- Improved DP AUX transfer
- Updated watermark latencies to fix underflows in some modes
Acked-by: Stylon W
From: Fangzhi Zuo
[Why]
configure_dp_hpo_throttled_vcp_size() was missing promotion before, but it was
covered by
not calling the missing function hook in the old interface
hpo_dp_link_encoder->funcs.
Recent refactor replaces with new caller link_hwss->set_throttled_vcp_size
which needs that h
From: Fangzhi Zuo
DP2 sequence is triggered only if VESA certified cable is detected.
Force DP2 sequence with uncertified cable for testing purpose.
Reviewed-by: Wenjing Liu
Acked-by: Stylon Wang
Signed-off-by: Fangzhi Zuo
---
.../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 26 +
From: Anthony Koo
- Correct number of reserved bits in cmd_lock_hw
- Extend bits of hw_lock_client to allow for more clients
Acked-by: Stylon Wang
Signed-off-by: Anthony Koo
---
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
di
From: Wenjing Liu
[why]
Move link_hwss to its own folder as part of DC LIB and break it down
to separate file one for each type of backend for code isolation.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/Makefile | 4 +-
...
From: Wenjing Liu
[why]
Isolate the way to obtain link_hwss from the actual implemenation
of link_hwss. So the caller can call link_hwss without knowing
the implementation detail of link_hwss.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
.../drm/amd/display/dc/co
From: Wenjing Liu
[why]
Clean up dc_link_hwss file in the preparation of breaking it down to file for
each encoder type. We temporarly move the original dp link functions in
link_hwss
back to dc_link_dp. We will break dc_link_dp down after link_hwss is in good
shape.
Reviewed-by: Jun Lei
Acke
From: Wenjing Liu
[why]
Factor set dp lane settings to link_hwss.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
.../drm/amd/display/dc/core/dc_link_hwss.c| 40 ++-
.../drm/amd/display/dc/dce/dce_link_encoder.c | 17
.../drm/amd/display
From: Wenjing Liu
[why]
Factor set dp link test pattern to link_hwss.
Reviewed-by: Jun Lei
Acked-by: Stylon Wang
Signed-off-by: Wenjing Liu
---
.../drm/amd/display/dc/core/dc_link_hwss.c| 46 +++
.../gpu/drm/amd/display/dc/inc/link_hwss.h| 3 ++
2 files changed, 29 i
From: Wenjing Liu
[why]
Factor enable/disable dp link output to link hwss.
Acked-by: Wayne Lin
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-
.../drm/amd/display/dc/core/dc_link_hwss.c| 256 +-
.../gpu/drm/amd/display/dc/inc/link_hws
From: Wenjing Liu
[how]
1. move decide det link training link resource before each link training.
2. move disable link for handling vbios case into set all streams
dpms off for link sequence.
3. extract usbc hotplug workaround into its own wa function.
4. Minor syntax changes to improve code read
From: Wenjing Liu
[why]
Factor setup/reset stream encoder to link hwss.
Acked-by: Wayne Lin
Signed-off-by: Wenjing Liu
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 64 +++
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 23 +--
.../drm/amd/display/dc/core/dc_link_hwss.c| 170
From: Zhan Liu
[Why]
This change causes regression, that prevents some systems
from lighting up internal displays.
[How]
Revert this patch until a new solution is ready.
Reviewed-by: Charlene Liu
Acked-by: Stylon Wang
Signed-off-by: Zhan Liu
---
.../amd/display/dc/dce110/dce110_hw_sequencer
From: "Leo (Hanghong) Ma"
[Why]
We find some of the driver sequence debug trace for infoframe
update is missing so add it.
[How]
Add the missing sequence debug trace for infoframe update.
Reviewed-by: Martin Leung
Acked-by: Stylon Wang
Signed-off-by: Leo (Hanghong) Ma
---
drivers/gpu/drm/am
From: Paul Hsieh
[Why]
The original latencies were causing underflow in some modes.
Resolution: 2880x1620@60p when HDR enable
[How]
1. Replace with the up-to-date watermark values based on new measurments
2. Correct the ddr_wm_table name to DDR5 on DCN31
Reviewed-by: Aric Cyr
Acked-by: Stylon
From: Wyatt Wood
[Why + How]
Payload reply is unknown and not handled in switch statement.
Reviewed-by: Anthony Koo
Acked-by: Stylon Wang
Signed-off-by: Wyatt Wood
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu
From: "Shen, George"
[Why]
Certain configurations will result in link encoder
to not be assigned to the link at the time we apply
cable ID logic. We should skip it in those cases.
[How]
Check if link_enc is not null before applying
cable ID.
Reviewed-by: Wenjing Liu
Acked-by: Stylon Wang
Sign
This DC patchset brings improvements in multiple areas. In summary, we have:
- DC refactor and bug fixes for DP links
- Bug fixes for DP2
- Fix regressions causing display not light up
- Improved debug trace
- Improved DP AUX transfer
- Updated watermark latencies to fix underflows in some modes
On Tue, Jan 25, 2022 at 12:57:29AM +0800, Zhou Qingyang wrote:
> In amdgpu_dm_connector_add_common_modes(), amdgpu_dm_create_common_mode()
> is assigned to mode and is passed to drm_mode_probed_add() directly after
> that. drm_mode_probed_add() passes &mode->head to list_add_tail(), and
> there is
On Tue, Jan 25, 2022 at 12:55:51AM +0800, Zhou Qingyang wrote:
> In calculate_bandwidth(), the tag free_sclk and free_yclk are reversed,
> which could lead to a memory leak of yclk.
>
> Fix this bug by changing the location of free_sclk and free_yclk.
>
> This bug was found by a static analyzer.
Hi Alex
> On 27-Jan-2022, at 11:06 PM, Alex Deucher wrote:
>
> C style comments please.
Shall be fixed in v2
> I'll let one of the display guys comment on
> the rest of the patch. Seems reasonable, we have a similar quirk for
> the Apple MBP 2017 15" Retina panel later in this function. Cou
There are two spelling mistakes in dev_err messages. Fix them.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
i
On 1/27/2022 10:36 PM, Chen, Guchun wrote:
> [AMD Official Use Only]
>
> Hi Jun,
>
> In RAS code, we have this special handling for Vega10. Can you elaborate it
> please? Any problem you have observed?
Ok, thanks for review. I'll confirm this.
>
> Regards,
> Guchun
>
> -Original Messag
On 1/28/2022 4:13 PM, Lang Yu wrote:
We observed a GPU hang when querying GMC CG state(i.e.,
cat amdgpu_pm_info) on cyan skillfish. Acctually, cyan
skillfish doesn't support any CG features.
Just prevent cyan skillfish from accessing GMC CG registers.
Signed-off-by: Lang Yu
Reviewed-by: L
We observed a GPU hang when querying GMC CG state(i.e.,
cat amdgpu_pm_info) on cyan skillfish. Acctually, cyan
skillfish doesn't support any CG features.
Just prevent cyan skillfish from accessing GMC CG registers.
Signed-off-by: Lang Yu
---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 +++
1 fil
On 1/28/2022 2:46 PM, Lang Yu wrote:
On 01/28/ , Lazar, Lijo wrote:
On 1/28/2022 2:22 PM, Lang Yu wrote:
On 01/28/ , Lazar, Lijo wrote:
On 1/28/2022 12:24 PM, Lang Yu wrote:
We observed a GPU hang when querying GMC CG state(i.e.,
cat amdgpu_pm_info) on cyan skillfish. Acctually, cyan
s
On 01/28/ , Lazar, Lijo wrote:
>
>
> On 1/28/2022 2:22 PM, Lang Yu wrote:
> > On 01/28/ , Lazar, Lijo wrote:
> > >
> > >
> > > On 1/28/2022 12:24 PM, Lang Yu wrote:
> > > > We observed a GPU hang when querying GMC CG state(i.e.,
> > > > cat amdgpu_pm_info) on cyan skillfish. Acctually, cyan
> >
On 1/28/2022 2:22 PM, Lang Yu wrote:
On 01/28/ , Lazar, Lijo wrote:
On 1/28/2022 12:24 PM, Lang Yu wrote:
We observed a GPU hang when querying GMC CG state(i.e.,
cat amdgpu_pm_info) on cyan skillfish. Acctually, cyan
skillfish doesn't support any CG features.
Only allow ASICs which suppor
On Thursday, 27 January 2022 2:09:41 PM AEDT Alex Sierra wrote:
[...]
> diff --git a/mm/migrate.c b/mm/migrate.c
> index 277562cd4cf5..2b3375e165b1 100644
> --- a/mm/migrate.c
> +++ b/mm/migrate.c
> @@ -2340,8 +2340,6 @@ static int migrate_vma_collect_pmd(pmd_t *pmdp,
> if (
Reviewed-by: Alistair Popple
On Thursday, 27 January 2022 2:09:45 PM AEDT Alex Sierra wrote:
> new ioctl cmd added to query zone device type. This will be
> used once the test_hmm adds zone device coherent type.
>
> Signed-off-by: Alex Sierra
> ---
> lib/test_hmm.c | 23 ++
Thanks for the updates, looks good now.
Reviewed-by: Alistair Popple
On Thursday, 27 January 2022 2:09:46 PM AEDT Alex Sierra wrote:
> In order to configure device coherent in test_hmm, two module parameters
> should be passed, which correspond to the SP start address of each
> device (2) spm_ad
On Thu, 27 Jan 2022 17:20:40 -0600 "Sierra Guiza, Alejandro (Alex)"
wrote:
> Andrew,
> We're somehow new on this procedure. Are you referring to rebase this
> patch series to
> git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
> <5.17-rc1 tag>?
No, against current Linus mainli
On Thursday, 27 January 2022 2:09:40 PM AEDT Alex Sierra wrote:
[...]
> diff --git a/mm/migrate.c b/mm/migrate.c
> index 1852d787e6ab..277562cd4cf5 100644
> --- a/mm/migrate.c
> +++ b/mm/migrate.c
> @@ -362,7 +362,7 @@ static int expected_page_refs(struct address_space
> *mapping, struct page *pa
On Thursday, 27 January 2022 2:09:43 PM AEDT Alex Sierra wrote:
[...]
> @@ -984,3 +990,4 @@ int svm_migrate_init(struct amdgpu_device *adev)
>
> return 0;
> }
> +
>
git-am complained about this when I applied the series. Given you have to
rebase anyway it would be worth fixing this.
On Thursday, 27 January 2022 2:09:42 PM AEDT Alex Sierra wrote:
> Avoid long term pinning for Coherent device type pages. This could
> interfere with their own device memory manager. For now, we are just
> returning error for PIN_LONGTERM Coherent device type pages. Eventually,
> these type of page
From: Changcheng Deng
'linux/pci.h' included in 'amdgpu_device.c' is duplicated.
Reported-by: Zeal Robot
Signed-off-by: Changcheng Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/d
I haven't tested the change which checks that pages migrated back to sysmem,
but it looks ok so:
Reviewed-by: Alistair Popple
On Thursday, 27 January 2022 2:09:47 PM AEDT Alex Sierra wrote:
> Device Coherent type uses device memory that is coherently accesible by
> the CPU. This could be shown a
From: Changcheng Deng
'amdgpu_dpm.h' included in 'arcturus_ppt.c' is duplicated.
Reported-by: Zeal Robot
Signed-off-by: Changcheng Deng
---
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
b
On 01/28/ , Lazar, Lijo wrote:
>
>
> On 1/28/2022 12:24 PM, Lang Yu wrote:
> > We observed a GPU hang when querying GMC CG state(i.e.,
> > cat amdgpu_pm_info) on cyan skillfish. Acctually, cyan
> > skillfish doesn't support any CG features.
> >
> > Only allow ASICs which support GMC CG features
On 1/28/2022 12:24 PM, Lang Yu wrote:
We observed a GPU hang when querying GMC CG state(i.e.,
cat amdgpu_pm_info) on cyan skillfish. Acctually, cyan
skillfish doesn't support any CG features.
Only allow ASICs which support GMC CG features accessing
related registers. As some ASICs support GMC
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