John,
I think the shortcomings of xlUpdateModel are what made the transition
from 7.1 to 10.1 so painful. Dynamically drawn blocks like the vacc
will not be handled correctly in general. Therefore, I think it will
be much easier and reliable to simply redraw the diagram block for
block in 10.1.
Gle
Hi all. I'm trying to port a rather complex model to 10.1, and I had
hoped that xlUpdateModel would allow me to do it rather easily, but when I
run it Matlab crashes. It seems to choke on the gavrt library's vacc
module. Has anyone gotten this to work, or should I forget it and just
redraw the
Hi Jason:
I guess the latest CPLD is quite important for us.
But for Uboot, I am not sure. Will all PPC registers be re-initialized again in
the linux core? Or the linux core use default value initialized by Uboot? Will
Uboot load OS into Dram before set the program pointer to the OS start addr
Hi Jason:
Thanks for you help.
But I could not find the tut4 in workshop. Could you please provide me the
exact link? Thanks.
As I know, the KATCP only provide data in ASCII. Is this right? And for KATCP,
all command and data are transferred by network. But we expeirence some network
failure w
Hi Jason:
As Kjetil mentioned, we are only working on OS. The OS crash and network
problem appears without our program running.
Cheers
Wan
-Original Message-
From: Jason Manley [mailto:jasonman...@gmail.com]
Sent: Wednesday, 4 November 2009 7:22 PM
To: Wormnes, Kjetil (ATNF, Marsfiel
> Hi Jason,
Hi all.
I think it would be very cool if someone who knows could make a wiki page
to tell us what the suggested set of cpld/uboot/linux codes are, and if
the suggested versions are different for different purposes. There's
getting to be quite a few choices in the archive.
We are fir
Hi Jason,
Thanks for your pointers; I am currently not actually using the FPGA.
Just focusing on being able to talk to the powerpc reliably at the moment.
The system does also crash when using NFS, but as I said and you noted;
it is more difficult to trace them directly back to EMACS related
Hi all,
I'm trying to retire an old 7.1 virtual machine to the digital grave that it
deserves. I ported a BEE2 design to 10.1, and successfully compiled the
relevant bof files for the BEE.
Unfortunately, when I run the boffile, the BEE hangs. If I run the process
in the background, I can see the
If you already have a bitstream, simply plug a JTAG programmer into P2
(labelled "Xilinx JTAG"), and use IMPACT.
But if I read your email correctly, you haven't configured clocks or
anything so I'm not sure what the point of this exercise is. I agree
with Suraj, easiest would be to start wi
Also, make sure you're running newwer versions of uboot and the CPLD
image. Bus settings changed some months back and improved stability
significantly.
Uboot will report the versions, and I recommend:
U-Boot 2008.10-svn2226 (Aug 7 2009 - 16:06:44)
...
Monitor Revision: 8.3.1698
CPLD Revisio
Hello Suraj
Thanks for you explanation.
Maybe I don't describe clearly.
I mean if I want program the FPAG on ROACH over JTAG.
Also, the bit file is generated by Xilinx ISE not CASPER toolflow.
In this moment, the ucf file of my design is only included the IO pins of my
design.
But a lot of pins
As you say, NFS mounts work correctly which would indicate that the
network is operating as expected. WRT other errors, are you certain
that all reads/writes on FPGA are on 32-bit boundaries? Byte-sized and
16-bit reads are supposed to work, but we have found that for some
reason they somet
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