https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/77153
>From 1a86a03fdc9d6eee08830ff2f113c39e6096d564 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Fri, 5 Jan 2024 14:40:26 -0800
Subject: [PATCH 1/5] [llvm-exegesis] Replace --num-repetitions with
--min-
https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/79276
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https://github.com/sdesmalen-arm edited
https://github.com/llvm/llvm-project/pull/79276
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@@ -10702,6 +10702,14 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
parseConstraintCode(Constraint) != AArch64CC::Invalid)
return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
+ if (StringRef("{za}").equals_insensitive(Constraint)) {
+
@@ -507,6 +507,10 @@ bool AArch64RegisterInfo::isAsmClobberable(const
MachineFunction &MF,
MCRegisterInfo::regsOverlap(PhysReg, AArch64::X16))
return true;
+ // ZA/ZT0 registers are reserved but may be permitted in the clobber list.
+ if (PhysReg.id() == AArch64
@@ -10702,6 +10702,14 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
parseConstraintCode(Constraint) != AArch64CC::Invalid)
return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
+ if (StringRef("{za}").equals_insensitive(Constraint)) {
github-actions[bot] wrote:
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
You can test this locally with the following command:
``bash
git-clang-format --diff 90e68086d8fdbfb32dfc7e7e3498f44365274ce8
6a81778059d72a4e4d236d0d6777a621a5bc965b --
boomanaiden154 wrote:
@legrosbuffle This is ready for review when you have a chance. Thanks!
https://github.com/llvm/llvm-project/pull/77153
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https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/77153
>From 1a86a03fdc9d6eee08830ff2f113c39e6096d564 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Fri, 5 Jan 2024 14:40:26 -0800
Subject: [PATCH 1/4] [llvm-exegesis] Replace --num-repetitions with
--min-
https://github.com/boomanaiden154 updated
https://github.com/llvm/llvm-project/pull/77153
>From 1a86a03fdc9d6eee08830ff2f113c39e6096d564 Mon Sep 17 00:00:00 2001
From: Aiden Grossman
Date: Fri, 5 Jan 2024 14:40:26 -0800
Subject: [PATCH 1/3] [llvm-exegesis] Replace --num-repetitions with
--min-
https://github.com/apolloww closed
https://github.com/llvm/llvm-project/pull/80253
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Author: Wei Wang
Date: 2024-02-01T00:29:59-08:00
New Revision: ae931b470319ade31fcc0797b6051eb8b96f9a8a
URL:
https://github.com/llvm/llvm-project/commit/ae931b470319ade31fcc0797b6051eb8b96f9a8a
DIFF:
https://github.com/llvm/llvm-project/commit/ae931b470319ade31fcc0797b6051eb8b96f9a8a.diff
LOG:
https://github.com/MDevereau updated
https://github.com/llvm/llvm-project/pull/79276
>From e98987ebb48839ea652d63dfaa62ed841b426e46 Mon Sep 17 00:00:00 2001
From: Matt Devereau
Date: Thu, 18 Jan 2024 15:41:25 +
Subject: [PATCH 1/3] [AArch64][SME] Implement inline-asm clobbers for za/zt0
Th
https://github.com/Pierre-vh updated
https://github.com/llvm/llvm-project/pull/76954
>From 7ad88453f5e89fd4643afa486e52a123138433f4 Mon Sep 17 00:00:00 2001
From: pvanhout
Date: Thu, 4 Jan 2024 14:12:00 +0100
Subject: [PATCH 1/2] [AMDGPU] Introduce Code Object V6
Introduce Code Object V6 in Cl
davemgreen wrote:
I think this is probably OK for Arm & AArch64. In the long run we should
ideally be adding better extract subvector costs, but this patch moves the cost
in that direction.
https://github.com/llvm/llvm-project/pull/79837
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kito-cheng wrote:
Also I guess most of RVV intrinsic could add `const` too, that could help some
generic optimization work better like CSE.
https://github.com/llvm/llvm-project/pull/79975
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https:/
kito-cheng wrote:
I guess we need add that at RVVEmitter::createbuilt...@riscvvemitter.cpp?
[1]
https://github.com/llvm/llvm-project/blob/main/clang/utils/TableGen/RISCVVEmitter.cpp#L418
[2]
https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/Builtins.h#L122-L124
[3]
http
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