mehnadnerd wrote:
It has been approved to be pursued as a fast track extension
(https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698).
It has not yet been approved by the chairs.
https://github.com/llvm/llvm-project/pull/79911
https://github.com/mehnadnerd updated
https://github.com/llvm/llvm-project/pull/79911
>From 3344e42d05875269b680b9626cd6cd093e88d81e Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH] [RISCV][MC] MC layer support for the experimental zalasr
extension
---
https://github.com/mehnadnerd updated
https://github.com/llvm/llvm-project/pull/79911
>From bfa9b7043d89de78e66f5073c3b34b66defdc2f4 Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH] [RISCV][MC] MC layer support for the experimental zalasr
extension
---
@@ -0,0 +1,66 @@
+//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*-
tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Ident
@@ -145,6 +145,7 @@
// CHECK-NOT: __riscv_zacas {{.*$}}
// CHECK-NOT: __riscv_zalrsc {{.*$}}
// CHECK-NOT: __riscv_zcmop {{.*$}}
+// CHECK-NOT: __riscv_zalasr {{.*$}}
mehnadnerd wrote:
Done, there was another place in the same file I fixed
https://github.com/
https://github.com/mehnadnerd updated
https://github.com/llvm/llvm-project/pull/79911
>From 1612df14bf52085ed1dd1a1c815a0515930c9d6e Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH] [RISCV][MC] MC layer support for the experimental zalasr
extension
---
https://github.com/mehnadnerd updated
https://github.com/llvm/llvm-project/pull/79911
>From 7f60b4aae0d75aabad7ecf159a7cd09420af6998 Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH] [RISCV][MC] MC layer support for the experimental zalasr
extension
---
@@ -0,0 +1,66 @@
+//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*-
tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Ident
@@ -0,0 +1,66 @@
+//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions ---*-
tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Ident
https://github.com/mehnadnerd closed
https://github.com/llvm/llvm-project/pull/69685
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
mehnadnerd wrote:
Closing because superseded by https://github.com/llvm/llvm-project/pull/79911.
https://github.com/llvm/llvm-project/pull/69685
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe
https://github.com/mehnadnerd created
https://github.com/llvm/llvm-project/pull/79911
This PR implements the RISC-V Atomic Load-Acquire and Store-Release Extension
(Zalasr).
See also https://github.com/mehnadnerd/riscv-zalasr.
This PR replaces https://github.com/llvm/llvm-project/pull/69685 be
@@ -105,22 +105,63 @@ defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011,
"amomaxu.d">,
// Pseudo-instructions and codegen patterns
//===--===//
+// An atomic load operation that does not need either acquire or r
@@ -105,22 +105,63 @@ defm AMOMAXU_D : AMO_rr_aq_rl<0b11100, 0b011,
"amomaxu.d">,
// Pseudo-instructions and codegen patterns
//===--===//
+// An atomic load operation that does not need either acquire or r
mehnadnerd wrote:
Still needs tests for the lowering.
https://github.com/llvm/llvm-project/pull/69685
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/mehnadnerd updated
https://github.com/llvm/llvm-project/pull/69685
>From c5ade18c2d22fb9913331b3339955bf56e8c38ad Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH 1/3] [RISCV][MC] MC layer support for the experimental zalasr
extension
https://github.com/mehnadnerd updated
https://github.com/llvm/llvm-project/pull/69685
>From c5ade18c2d22fb9913331b3339955bf56e8c38ad Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH 1/3] [RISCV][MC] MC layer support for the experimental zalasr
extension
https://github.com/mehnadnerd updated
https://github.com/llvm/llvm-project/pull/69685
>From c5ade18c2d22fb9913331b3339955bf56e8c38ad Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH 1/3] [RISCV][MC] MC layer support for the experimental zalasr
extension
https://github.com/mehnadnerd updated
https://github.com/llvm/llvm-project/pull/69685
>From 56081a5bfe14605a692c3b49dd5c37625673aadf Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH 1/2] [RISCV][MC] MC layer support for the experimental zalasr
extension
mehnadnerd wrote:
I've updated it to add regression tests.
https://github.com/llvm/llvm-project/pull/69685
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/mehnadnerd updated
https://github.com/llvm/llvm-project/pull/69685
>From d412fa8018ff4788c3ed8a1c8018c293be20040f Mon Sep 17 00:00:00 2001
From: brs
Date: Thu, 19 Oct 2023 17:16:45 -0500
Subject: [PATCH] [RISCV][MC] MC layer support for the experimental zalasr
extension
---
21 matches
Mail list logo
