OK, with 3073, something went worse.
Last night, I was flashing just fine. As of today, it's not id'ing it
and it is reading 0xff back for that pass. I am attaching a failed
(first) and successfull on the 4mbit part (second half) of the file.
I'm trying to get to the point of trying to figure out
Hello!
Extremely.
And yes I agree with you Ron regarding your unit. Incidentally one of its
problems happens to be heat management.
I also agree with Peter regarding the unit, (see earlier messages.)
--
Gregg C Levine [EMAIL PROTECTED]
"The Force will be with you always." Obi-Wan Kenobi
> ---
Quoting Carl-Daniel Hailfinger <[EMAIL PROTECTED]>:
> On 23.01.2008 02:24, [EMAIL PROTECTED] wrote:
>> Quoting Carl-Daniel Hailfinger <[EMAIL PROTECTED]>:
>>
>>
>>> On 23.01.2008 01:41, [EMAIL PROTECTED] wrote:
>>>
Arugh!!! When I tested the patch eveerything worked ok but now with
the n
It fails on ubuntu. I just did an svn up and:
nput/output = 130304/53382 = 2.441
cp coreboot_ram.nrv2b coreboot_ram.rom
echo '/*ldoptions*/' > ldscript.ld; cat ldoptions >> ldscript.ld ; for
file in /home/rminnich/src/bios/coreboot-v2/src/arch/i386/init/ldscript.lb
/home/rminnich/src/bios/coreboo
On 23.01.2008 02:24, [EMAIL PROTECTED] wrote:
> Quoting Carl-Daniel Hailfinger <[EMAIL PROTECTED]>:
>
>
>> On 23.01.2008 01:41, [EMAIL PROTECTED] wrote:
>>
>>> Arugh!!! When I tested the patch eveerything worked ok but now with
>>> the new svn version, when I try abuild it get this:
>>> ---
Besides the obvious stuff (storing the VSA as a file in the LAR) there
are two points to solve which are rather interesting:
- Entry point specification
- Load address specification
Both are not trivial because we get both specifications above from an
ELF header. The VSA is not an ELF file, so we h
Quoting Carl-Daniel Hailfinger <[EMAIL PROTECTED]>:
> On 23.01.2008 01:41, [EMAIL PROTECTED] wrote:
>> Arugh!!! When I tested the patch eveerything worked ok but now with
>> the new svn version, when I try abuild it get this:
>>
>>Creating builddir...ok
>>Compiling
On 23.01.2008 01:41, [EMAIL PROTECTED] wrote:
> Arugh!!! When I tested the patch eveerything worked ok but now with
> the new svn version, when I try abuild it get this:
>
>Creating builddir...ok
>Compiling image ..FAILED after 13s! Log excerpt:
> gcc -m32 -nostd
here's a positive note, it works fine for me on fc8.
[EMAIL PROTECTED] ga_2761gxdk]$ ld -v -v
GNU ld version 2.17.50.0.12-4 20070128
GNU ld version 2.17.50.0.12-4 20070128
[EMAIL PROTECTED] ga_2761gxdk]$ gcc -v -v
Using built-in specs.
Target: i386-redhat-linux
Configured with: ../configure --pref
Arugh!!! When I tested the patch eveerything worked ok but now with
the new svn version, when I try abuild it get this:
Creating builddir...ok
Compiling image ..FAILED after 13s! Log excerpt:
gcc -m32 -nostdlib -nostartfiles -static -o coreboot_ram -T
/home/joe/c
Don't try to register for the hotel just yet, as we are getting the
conf. rate extended to april 6.
But if people could start registering it would help us a great deal
with arrangements.
Also, potential sponsors, please contact me if you can help support
this meeting.
If you can buy a six-pack of
On Tue, Jan 22, 2008 at 09:43:35PM +0100, Patrick Georgi wrote:
> This patch adds a new record type for lbtable to provide information
> about a serial port. If a port is defined in the board configuration,
> add it to lbtable.
>
> Signed-off-by: Patrick Georgi <[EMAIL PROTECTED]>
Acked-by: Peter
* Florentin Demetrescu <[EMAIL PROTECTED]> [2008-01-22 21:59]:
> yes but they DO have access to datasheets..
> we don't...
> they are "trusted" bussiness partners..
> we aren't..
Well, data sheet or not:
bool error_handling(int error)
{
switch (error) {
ERR_KEYBOARD:
yes but they DO have access to datasheets..
we don't...
they are "trusted" bussiness partners..
we aren't..
:/
Quoting Peter Stuge <[EMAIL PROTECTED]>:
> On Tue, Jan 22, 2008 at 11:09:10AM -0800, ron minnich wrote:
> > brand new shuttle box
> >
> > phoenix-award bios
> >
> > "keyboard error or no
Am Tue, 22 Jan 2008 20:37:59 +0100 schrieb Peter Stuge:
> Some kind of recovery, management, whatever. I can't think of all uses
> either, but I certianly do not want to impose an arbitrary limit like
> "coreboot only tells you about serial ports that are the console" - I
> like the generic serial
On 22.01.2008 20:04, ron minnich wrote:
> On Jan 22, 2008 10:46 AM, Peter Stuge <[EMAIL PROTECTED]> wrote:
>
>
>> Small thing; I would prefer something else than a comma after the
>> type, so that it is separated from the real information. Maybe:
>> id="pci:vendor,device";
>>
>> I think that wou
On Tue, Jan 22, 2008 at 11:09:10AM -0800, ron minnich wrote:
> brand new shuttle box
>
> phoenix-award bios
>
> "keyboard error or no keyboard present"
>
> "Press F1 to continue"
Computer science at it's finest, anno 2008.
> It's just too funny.
I think it's sad actually.
> Imagine a beowu
On Tue, Jan 22, 2008 at 11:45:08AM +0100, Torsten Duwe wrote:
> I cannot think of a good use a payload can make of a serial port
> other than console
Some kind of recovery, management, whatever. I can't think of all
uses either, but I certianly do not want to impose an arbitrary limit
like "corebo
On Mon, Jan 21, 2008 at 01:30:36PM +0100, Patrick Georgi wrote:
> As you can see, my patch doesn't pretend that the serial port is
> the console
..yet..
> + /* Record our console */
> + lb_serial(head);
Change the comment and I'll ack.
//Peter
--
coreboot mailing list
coreboot@corebo
Tiago Marques wrote:
> Hi Marc.
> I'm new to the ML, but was very curious about Barcelona(Phenom) support.
> Will we be able to run Phenom CPUs with coreboot on a 4Mbit BIOS?
> There were some rumors about only 8Mbit BIOS being supported.
> I'm definetely interested since I have two AM2 boards wi
On Tue, Jan 22, 2008 at 10:29:17AM +0100, [EMAIL PROTECTED] wrote:
> I own a VIA EPIA EN15000 Motherboard
..
> Is there a chance to get my board working ?
Some, if you have time to hack a bit.
> Can anybody tell me what to do ?
Corey Osgood has posted a C7/CN700 patch to the list. It has been
t
brand new shuttle box
phoenix-award bios
"keyboard error or no keyboard present"
"Press F1 to continue"
It's just too funny. Imagine a beowulf of these!
ron
--
coreboot mailing list
coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
On Jan 22, 2008 10:46 AM, Peter Stuge <[EMAIL PROTECTED]> wrote:
> Small thing; I would prefer something else than a comma after the
> type, so that it is separated from the real information. Maybe:
> id="pci:vendor,device";
>
> I think that would make the syntax much more clear.
Thats fine with
On Jan 22, 2008 10:20 AM, Carl-Daniel Hailfinger
<[EMAIL PROTECTED]> wrote:
> I'd say we refuse to execute the ROM in v3. If the ROM is broken, we
> have no way to determine how broken it is. Unconditional execution may
> prevent booting the machine, thereby forcing an out-of-system flash of
> cor
On Tue, Jan 22, 2008 at 04:19:11PM +0100, Carl-Daniel Hailfinger wrote:
> > I am thinking of something like this:
> > id="pci,somevendorname,somedevicename";
>
> Makes sense if the coreboot code itself does not have to perform
> any string parsing.
Small thing; I would prefer something else than
Hi Marc.
I'm new to the ML, but was very curious about Barcelona(Phenom) support.
Will we be able to run Phenom CPUs with coreboot on a 4Mbit BIOS?
There were some rumors about only 8Mbit BIOS being supported.
I'm definetely interested since I have two AM2 boards with 4Mbit BIOS chips.
Either way,
> On 22.01.2008 18:59, Myles Watson wrote:
> > Coreboot v3 refuses to initialize the VGA in QEMU because the PCI device
> > ID's are mismatched.
> >
> > It turns out that the header has been overwritten by a copyright string,
> so
> > that v3 is following a bad pointer into the ROM looking for the
On 22.01.2008 18:59, Myles Watson wrote:
> Coreboot v3 refuses to initialize the VGA in QEMU because the PCI device
> ID's are mismatched.
>
> It turns out that the header has been overwritten by a copyright string, so
> that v3 is following a bad pointer into the ROM looking for the PCI device
> I
Carl-Daniel Hailfinger wrote:
>Harald: This patch should fix your problems writing to the chip. Use
>either "patch -l" or remove the // before
>//while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
>
>Ronald: I need an ack to commit this.
>
>On 20.01.2008 11:59, Ronald Hoogenboom wrote
Coreboot v3 refuses to initialize the VGA in QEMU because the PCI device
ID's are mismatched.
It turns out that the header has been overwritten by a copyright string, so
that v3 is following a bad pointer into the ROM looking for the PCI device
IDs and not finding it. Coreboot v2 still successful
Darmawan Salihun wrote:
> Hi Marc,
>
>
> On Jan 22, 2008 1:21 AM, Marc Jones <[EMAIL PROTECTED]> wrote:
>> The 690/600 support should be available in the first half of this year.
>> We moved it out a few months to bring in the Barcelona support.
>> I don't have specific dates but we will announ
On 21.01.2008 17:42, Ed Swierk wrote:
> On Dec 27, 2007 4:25 PM, Carl-Daniel Hailfinger
> <[EMAIL PROTECTED]> wrote:
>
>> I'm currently reviewing the rest of the patch. Looks nice so far.
>>
>
> There's no urgency, but I'm wondering if there's anything I can do to help.
>
I'm sorry, but
On 22.01.2008 17:37, ron minnich wrote:
> On Jan 22, 2008 8:27 AM, Carl-Daniel Hailfinger
> <[EMAIL PROTECTED]> wrote:
>
>> Ron?
>>
>
> See my other note, this works but verify did not, which I think you
> also just fixed.
>
Yes, but status register printing for your chips was in that p
On Jan 22, 2008 8:27 AM, Carl-Daniel Hailfinger
<[EMAIL PROTECTED]> wrote:
> Ron?
See my other note, this works but verify did not, which I think you
also just fixed.
The board still does not boot or even POST for me. I am wishing I had
some 512kB parts.
ron
--
coreboot mailing list
coreboot@c
Ron?
On 10.01.2008 13:32, Carl-Daniel Hailfinger wrote:
> Btw, the block lock bits are all set, so even if you manage to convince
> the SPI translation to map more than 512 KByte and even if you use
> enable LPC-to-SPI writes, you will still flash nothing. Try this for
> better lock bit printing:
On 22.01.2008 16:47, Marc Karasek wrote:
> Been away for the weekend. Sun was closed on Monday.
>
> Signed of by Marc Karasek <[EMAIL PROTECTED]>
>
>
> Carl-Daniel Hailfinger wrote:
>
>> On 09.01.2008 16:13, Marc Karasek wrote:
>>
>>
>>> Attached is the latest.
>>>
>>> It uses -ge inst
Author: hailfinger
Date: 2008-01-22 17:09:36 +0100 (Tue, 22 Jan 2008)
New Revision: 3073
Modified:
trunk/coreboot-v2/src/config/Config.lb
trunk/coreboot-v2/targets/buildtarget
Log:
Use "--build-id=none" as linker flags if build-id is supported.
That fixes a compilation failure.
Signed-off-b
Author: hailfinger
Date: 2008-01-22 17:09:36 +0100 (Tue, 22 Jan 2008)
New Revision: 3073
Modified:
trunk/coreboot-v2/src/config/Config.lb
trunk/coreboot-v2/targets/buildtarget
Log:
Use "--build-id=none" as linker flags if build-id is supported.
That fixes a compilation failure.
Signed-off-b
On 22.01.2008 16:59, Uwe Hermann wrote:
> On Tue, Jan 22, 2008 at 03:59:28PM +0100, Carl-Daniel Hailfinger wrote:
>
>> Flashrom did not use the read function for verifying, it used direct memory
>> access instead. That fails if the flash chip is not mapped completely.
>> If the read function is
On Tue, Jan 22, 2008 at 10:17:23PM +0800, bxshi wrote:
> when I check out the code by : svn co
> https://coreboot.org/svn/trunk/coreboot-v2
> it begin to download,
>
> ..
> Acoreboot-v2/util/resetcf
> Acoreboot-v2/util/resetcf/resetcf.c
> Acoreboot-v2/util/buildrom
> Acoreboot
On 22.01.2008 16:34, Harald Gutmann wrote:
> Here is just a little and simple patch to get the MX25L3205D working.
> I've tested and verified the chip myself, and it seems to work everything
> like
> supposted, since Carl has patched flashrom to use the read funktion on
> verifying.
>
> "benchv
Author: hailfinger
Date: 2008-01-22 17:03:19 +0100 (Tue, 22 Jan 2008)
New Revision: 3072
Modified:
trunk/util/flashrom/flashchips.c
Log:
Here is just a little and simple patch to get the MX25L3205D working.
I've tested and verified the chip myself, and it seems to work
everything like supposted
Author: hailfinger
Date: 2008-01-22 17:03:19 +0100 (Tue, 22 Jan 2008)
New Revision: 3072
Modified:
trunk/util/flashrom/flashchips.c
Log:
Here is just a little and simple patch to get the MX25L3205D working.
I've tested and verified the chip myself, and it seems to work
everything like supposted
Author: uwe
Date: 2008-01-22 17:00:46 +0100 (Tue, 22 Jan 2008)
New Revision: 3071
Modified:
trunk/coreboot-v2/util/
Log:
Change svn:externals to use new coreboot.org domain (trivial).
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>
Property changes
Author: uwe
Date: 2008-01-22 17:00:46 +0100 (Tue, 22 Jan 2008)
New Revision: 3071
Modified:
trunk/coreboot-v2/util/
Log:
Change svn:externals to use new coreboot.org domain (trivial).
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>
Property changes
On Tue, Jan 22, 2008 at 03:59:28PM +0100, Carl-Daniel Hailfinger wrote:
> Flashrom did not use the read function for verifying, it used direct memory
> access instead. That fails if the flash chip is not mapped completely.
> If the read function is set in struct flashchip, use it for verification
>
Been away for the weekend. Sun was closed on Monday.
Signed of by Marc Karasek <[EMAIL PROTECTED]>
/*
Marc Karasek
MTS
Sun Microsystems
mailto:[EMAIL PROTECTED]
ph:770.360.6415
*/
Carl-Daniel Hailfinger wrote:
> Hi!
>
> To bring this issue to an end, I
Here is just a little and simple patch to get the MX25L3205D working.
I've tested and verified the chip myself, and it seems to work everything like
supposted, since Carl has patched flashrom to use the read funktion on
verifying.
"benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb
On 22.01.2008 16:10, Harald Gutmann wrote:
> Am Dienstag, 22. Januar 2008 15:59:28 schrieb Carl-Daniel Hailfinger:
>
>> Flashrom did not use the read function for verifying, it used direct memory
>> access instead. That fails if the flash chip is not mapped completely.
>> If the read function is
Author: hailfinger
Date: 2008-01-22 16:19:01 +0100 (Tue, 22 Jan 2008)
New Revision: 3070
Modified:
trunk/util/flashrom/flashrom.c
Log:
Flashrom did not use the read function for verifying, it used direct memory
access instead. That fails if the flash chip is not mapped completely.
If the read f
Author: hailfinger
Date: 2008-01-22 16:19:01 +0100 (Tue, 22 Jan 2008)
New Revision: 3070
Modified:
trunk/util/flashrom/flashrom.c
Log:
Flashrom did not use the read function for verifying, it used direct memory
access instead. That fails if the flash chip is not mapped completely.
If the read f
On 19.01.2008 07:35, ron minnich wrote:
> On Jan 18, 2008 4:27 PM, Carl-Daniel Hailfinger
> <[EMAIL PROTECTED]> wrote:
>
>
>> Is this same situation as before or is it worse? If it is worse, please
>> try to fix before you commit.
>>
>
> The fix is going to be a bit harder, so I am committi
Am Dienstag, 22. Januar 2008 15:59:28 schrieb Carl-Daniel Hailfinger:
> Flashrom did not use the read function for verifying, it used direct memory
> access instead. That fails if the flash chip is not mapped completely.
> If the read function is set in struct flashchip, use it for verification
> a
On 22.01.2008 03:53, ron minnich wrote:
> Just FYI, some luck writing this chip on the sis board ...
>
> The write had no errors. The -v failed. But on using the -r to read to
> a file, I find
> no differences between the file used for -w and the file used for -v!
>
Yes, very old lingering bug
Flashrom did not use the read function for verifying, it used direct memory
access instead. That fails if the flash chip is not mapped completely.
If the read function is set in struct flashchip, use it for verification
as well.
This fixes verification of all SPI flash chips >512 kByte behind an
I
Hi Tiago,
On Tue, Jan 22, 2008 at 03:21:38AM +, Tiago Marques wrote:
> Hi!
> I have recently tried the flashrom software and it ended up saving my day.
> I had a dead board, but with flashrom I managed to hotflash without
> having to take that crap from proprietary flash software that it
> doe
On 22.01.2008 12:08, Harald Gutmann wrote:
> Am Dienstag, 22. Januar 2008 01:09:09 schrieben Sie:
>
>> Harald: This patch should fix your problems writing to the chip. Use
>> either "patch -l" or remove the // before
>> //while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
>>
>
Author: hailfinger
Date: 2008-01-22 15:37:31 +0100 (Tue, 22 Jan 2008)
New Revision: 3069
Modified:
trunk/util/flashrom/spi.c
Log:
Make sure we delay writing the next byte long enough in SPI byte
programming.
Minor formatting changes.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Ac
Author: hailfinger
Date: 2008-01-22 15:37:31 +0100 (Tue, 22 Jan 2008)
New Revision: 3069
Modified:
trunk/util/flashrom/spi.c
Log:
Make sure we delay writing the next byte long enough in SPI byte
programming.
Minor formatting changes.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Ac
when I check out the code by : svn co
https://coreboot.org/svn/trunk/coreboot-v2
it begin to download,
..
Acoreboot-v2/util/resetcf
Acoreboot-v2/util/resetcf/resetcf.c
Acoreboot-v2/util/buildrom
Acoreboot-v2/util/buildrom/buildrom.c
U coreboot-v2
Fetching external item int
Hi Marc,
On Jan 22, 2008 1:21 AM, Marc Jones <[EMAIL PROTECTED]> wrote:
> The 690/600 support should be available in the first half of this year.
> We moved it out a few months to bring in the Barcelona support.
> I don't have specific dates but we will announce the code to the list as
> soon as
On Mon, Jan 21, 2008 at 04:01:57PM -0700, Marc Jones wrote:
> >> -/* smbus functions */
> >> -int smbus_read_byte(unsigned device, unsigned address);
> >
> > hmm. So where does the prototype live then?
There's include/device/smbus.h with
int smbus_read_byte(struct device *dev, u8 addr);
and als
Am Dienstag, 22. Januar 2008 01:09:09 schrieben Sie:
> Harald: This patch should fix your problems writing to the chip. Use
> either "patch -l" or remove the // before
> //while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
I've updated my flashrom tree to revision 3068 and commented th
Am Dienstag, 22. Januar 2008 00:48:30 schrieben Sie:
> On 21.01.2008 17:15, Harald Gutmann wrote:
> > Hello!
> >
> > As in the thread "Re: [coreboot] SST25VF016B (2MB) flash on m57sli
> > (IT8716F)" there was added support for writing/reading lager SPI chips
> > than 512kB i had a look on the curre
On Monday 21 January 2008, Patrick Georgi wrote:
> This record is intended to tell the payload about the existence and
> where-abouts of a serial port. A console would be a separate record with
> that number you propose (or something like that)
>
> If and where a serial port is to be found is an i
I own a VIA EPIA EN15000 Motherboard
see
http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=399
and I'd like to give LinuxBIOS a try.
Linux lspci output is:
00:00.0 Host bridge: VIA Technologies, Inc. CN700/VN800/P4M800CE/Pro Host
Bridge
00:00.1 Host bridge: VIA Technol
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