tions(+)
Cheers,
Brett Holman
PS: This is my first post on this mailing list. I believe that I've followed
the documented steps, but if I've missed anything please let me know.
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From: Brett Holman
The SMBIOS specification[1] includes RISC-V and mips, and some systems have
SMBIOS info. Attempt to read dmidecode and fall back to old behavior if that
fails.
[1]
https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.4.0.pdf
Signed-off-by: Brett Holman
This patch intends to add DMI support to libvirt for RISC-V and mips.
This is based on commit ec6ce6363, which added ARM support.
This is untested, as I've been unable to find hardware to test this on.
src/util/virsysinfo.c | 2 ++
1 file changed, 2 insertions(+)
Cheers,
Brett Holman
From: Brett Holman
The SMBIOS specification[1] includes RISC-V and mips, and some systems have
SMBIOS info. Attempt to read dmidecode and fall back to old behavior if that
fails.
[1]
https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.4.0.pdf
Signed-off-by: Brett Holman
tions(+)
Cheers,
Brett Holman
PS: This is my first post on this mailing list. I believe that I've followed
the documented steps, but if I've missed anything please let me know.
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From: Brett Holman
The SMBIOS specification[1] includes RISC-V and mips, and some systems have
SMBIOS info. Attempt to read dmidecode and fall back to old behavior if that
fails.
[1]
https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.4.0.pdf
Signed-off-by: Brett Holman
My apologies for this duplicate, please direct reviews to this thread ->
https://lists.libvirt.org/archives/list/devel@lists.libvirt.org/thread/G6GPDHYL7CT7MFRECAPL7ZDSXOWQUABG/
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My apologies for this duplicate, please direct reviews to this thread ->
https://lists.libvirt.org/archives/list/devel@lists.libvirt.org/thread/G6GPDHYL7CT7MFRECAPL7ZDSXOWQUABG/
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> As I do not have knowledge in this - did you possibly include mips, because
> the newest specification also includes LoongArch?
> If yes - could you amend the commit message to include the link to the
> newest version [2] and to explain the relationship between mips x
> LoongArch?
Thanks for th
tions(+)
V1->V2:
1. Update commit message to clarify Loongson->mips relationship.
2. Rebase onto recent LoongArch merge.
Cheers,
Brett Holman
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From: Brett Holman
Add DMI support for risc-v and mips. Attempt to read dmidecode and
fall back to old behavior if that fails.
The SMBIOS specification[1] officially supports both RISC-V and LoongArch.
Some mips-based Loongson-3 processors also have SMBIOS.
[1]
https://www.dmtf.org/sites
tions(+)
V1->V2:
1. Clarify commit message
2. Rebase onto recent LoongArch merge.
Cheers,
Brett Holman
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From: Brett Holman
Add DMI support for risc-v and mips. Attempt to read dmidecode and
fall back to old behavior if that fails.
The SMBIOS specification[1] officially supports both RISC-V and LoongArch.
Some mips-based Loongson-3 processors also have SMBIOS.
[1]
https://www.dmtf.org/sites
g wrote:
>
> On 3/26/24 13:38, brett.hol...@canonical.com wrote:
> > From: Brett Holman
> >
> > Add DMI support for risc-v and mips. Attempt to read dmidecode and
> > fall back to old behavior if that fails.
> >
> > The SMBIOS specification[1] offic
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