Thanks Brian,
That clears up a lot in my head.
My Verilog knowledge is pretty primitive at this point.
Tomas O'Maille
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On Wed, Jan 30, 2008 at 06:35:07AM -0800, TomasOMaille wrote:
>
> Hello,
>
> I have been trying to understand the tx and rx data paths through the AD9862
> and the FPGA (standard configuration).
>
Hi Tomas,
Take a look here
http://www.gnuradio.org/trac/wiki/UsrpRfxDiagrams
and ask again if
On Jan 30, 2008 9:35 AM, TomasOMaille <[EMAIL PROTECTED]> wrote:
>
> Hello,
>
> I have been trying to understand the tx and rx data paths through the AD9862
> and the FPGA (standard configuration).
>
> RX side:
>
> - The two ADCs of the AD9862 push data onto two 12 bit buses
>
> - After the FPGA
Hello,
I have been trying to understand the tx and rx data paths through the AD9862
and the FPGA (standard configuration).
RX side:
- The two ADCs of the AD9862 push data onto two 12 bit buses
- After the FPGA MUX the 16 bit I/Q signals pass into the assigned DDC
- Are four extra bits assi
