On 01/12/2017 05:36 AM, John Stultz wrote:
On Wed, Jan 11, 2017 at 12:48 AM, Archit Taneja wrote:
Hi,
On 01/04/2017 01:11 AM, John Stultz wrote:
Hope everyone had a good newyears!
Wanted to re-send out v3 of this patch set improving the EDID
probing on the adv7511 used on HiKey, for
would be appreciated!
Tested on DB410c on 4.10-rc3. Works well for me.
Thanks,
Archit
>
> thanks
> -john
>
> New in v3:
> * Addressed naming improvements and drm_kms_helper_hotplug_event
> usage corrections as suggested by Laurent.
>
> Cc: David Airlie
> Cc: Arc
Maintain a table of regulator names expected by ADV7511 and ADV7533.
Use regulator_bulk_* api to configure these.
Initialize and enable the regulators during probe itself. Controlling
these dynamically is left for later.
Reviewed-by: Laurent Pinchart
Signed-off-by: Archit Taneja
---
drivers
Add the regulator supply properties needed by ADV7511 and ADV7533.
Acked-by: Laurent Pinchart
Acked-by: Rob Herring
Signed-off-by: Archit Taneja
---
v5:
- Bring back supplies for individual pins
- In v2, we had a v3p3-supply for DVDD_3V on ADV7511 and V3P3 pin
on ADV7533. We don't r
n the binding docs.
- Update the driver to manage regulators for both ADV7511 and ADV7533.
- Have separate supply entries for AVDD, DVDD, PVDD, A2VDD pins.
- Use regulator_bulk_* API to configure regulators.
Archit Taneja (2):
dt-bindings: drm/bridge: adv7511: Add regulator bindings
drm/bridge: ad
set the encoder's bridge. That's now managed by the bridge
API.
Cc: Laurent Pinchart
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/d
On 01/05/2017 01:01 PM, Sean Paul wrote:
> On Fri, Dec 30, 2016 at 4:57 AM, Marek Szyprowski
> wrote:
>> Analogix_dp_bind() can be called from component framework, which doesn't
>> guarantee proper runtime PM state of the device during bind operation,
>> so ensure that device is runtime active b
ephen Boyd
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/Kconfig|7 +
drivers/gpu/drm/msm/Makefile |2 +
drivers/gpu/drm/msm/dsi/dsi.h |8 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c |2 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h |
From: Hai Li
The 14nm DSI PHY on 8x96 (called PHY v2 downstream) requires a different
set of calculations for computing D-PHY timing params. Create a
timing_calc_v2 func for the newer v2 PHYs.
Signed-off-by: Hai Li
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 117
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 252 ++
1 file changed, 252 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 4958594..234b3b3 100644
--- a/drivers/gpu/drm/msm/dsi
From: Hai Li
Since DSI PHY has been a separate platform device, it should not
depend on the resources in host to be functional. This change is
to trigger PHY operations in manager, instead of host, so that
host and PHY can be completely separated.
Signed-off-by: Hai Li
Signed-off-by: Archit
up
by Archit Taneja ]
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c| 25 +
drivers/gpu/drm/msm/dsi/dsi_manager.c | 32 +---
3 files changed, 43 insertions(+), 15 dele
From: Hai Li
For some new types of DSI PHY, more settings depend on
use cases controlled by DSI manager. This change allows
DSI manager to setup PHY with a use case.
Signed-off-by: Hai Li
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi.h | 8 +++
drivers/gpu/drm/msm
From: Hai Li
The DSI host is required to configure more timings calculated
in PHY. By introducing a shared structure, this change allows
more timing information passed from PHY to host.
Signed-off-by: Hai Li
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi.h | 13
Create an init() op for dsi_phy which sets up things specific to
a given DSI PHY.
The dsi_phy driver probe expects every DSI version to get a
"dsi_phy_regulator" mmio base. This isn't the case for 8x96.
Creating an init() op will allow us to accommodate such
differences.
Signed
rnings.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 25 +
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 +
2 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 63436d8..a5d75c9 10064
ng the DSI device
even if it doesn't have a bridge/panel connected to it.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi
(single DSI)
on DB820c.
Archit Taneja (6):
drm/msm/dsi: Don't error if a DSI host doesn't have a device connected
drm/msm/dsi: Add 8x96 info in dsi_cfg
drm/msm/dsi: Add a PHY op that initializes version specific stuff
drm/msm/dsi: Reset both PHYs before clock operation for dual
Add DSI PHY 14nm domains for DSI PHY common, DSI PHY lane and
DSI PLL registers. Used in MSM8996.
Signed-off-by: Archit Taneja
---
rnndb/dsi/dsi.xml | 128 ++
1 file changed, 128 insertions(+)
diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi
gt; Video output
>
> Cc: Martyn Welch
> Cc: Martin Donnelly
> Cc: Daniel Vetter
> Cc: Enric Balletbo i Serra
> Cc: Philipp Zabel
> Cc: Rob Herring
> Cc: Fabio Estevam
> CC: David Airlie
> CC: Thierry Reding
> CC: Thierry Reding
> CC: Archit Taneja
> Re
Hi Sekhar,
On 1/2/2017 4:38 PM, Sekhar Nori wrote:
> Hi Archit,
>
> On Wednesday 14 December 2016 10:35 AM, Archit Taneja wrote:
>>
>>
>> On 12/13/2016 03:39 PM, Bartosz Golaszewski wrote:
>>> THS8135 is a configurable video DAC, but no configuration is ac
ldoc tends to be long).
>
> Also some minor drive-by polish where it makes sense, I read a lot
> of docs ...
>
> Cc: Archit Taneja
> Cc: Jani Nikula
> Cc: Chris Wilson
> Signed-off-by: Daniel Vetter
> ---
> drivers/gpu/drm/drm_bridge.c | 27 +++
On 12/20/2016 07:10 PM, Maarten Lankhorst wrote:
> Op 20-12-16 om 07:23 schreef Archit Taneja:
>>
>>
>> On 12/19/2016 06:20 PM, Maarten Lankhorst wrote:
>>> Op 19-12-16 om 13:08 schreef Archit Taneja:
>>>> This code has been more or less picked up from
Update mdp5_pipe to incorporate SSPP_NONE and SSPP_CURSORx
pipes
Signed-off-by: Archit Taneja
---
rnndb/mdp/mdp5.xml | 25 ++---
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index 49aa207..a5ae1e3 100644
--- a/rnndb
Signed-off-by: Archit Taneja
---
rnndb/mdp/mdp5.xml | 4
1 file changed, 4 insertions(+)
diff --git a/rnndb/mdp/mdp5.xml b/rnndb/mdp/mdp5.xml
index de9560b..49aa207 100644
--- a/rnndb/mdp/mdp5.xml
+++ b/rnndb/mdp/mdp5.xml
@@ -451,6 +451,10 @@ xsi:schemaLocation="
Some cursor SSPP related updates.
Archit Taneja (2):
rnndb: mdp5: Add missing bitfields for MDP5_LM_BLEND_COLOR_OUT
rnndb: mdp5: Update mdp5_pipe
rnndb/mdp/mdp5.xml | 29 ++---
1 file changed, 18 insertions(+), 11 deletions(-)
--
The Qualcomm Innovation Center, Inc
On 12/19/2016 06:20 PM, Maarten Lankhorst wrote:
> Op 19-12-16 om 13:08 schreef Archit Taneja:
>> This code has been more or less picked up from the vc4 and intel
>> implementations of update_plane() funcs for cursor planes.
>>
>> The update_
ursor_updates flag.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 32 +---
drivers/gpu/drm/msm/msm_atomic.c| 5 -
2 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
b/drivers/gp
w path for every new fb. The slow path will ensure
that the fb is prepared/pinned etc.
Cc:
Signed-off-by: Archit Taneja
---
- Don't know what to do for locking here :/
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 7 ++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 +
drivers/gpu/d
, but crtc_state would need to
be derived differently.
Refactor mdp5_plane_atomic_check to mdp5_plane_atomic_check_with_state
such that the latter takes crtc_state as an argument.
This is similar to what the intel driver has done for async cursor
updates.
Signed-off-by: Archit Taneja
---
drivers/gpu/dr
pe in mdp5_plane_init instead of a bool telling
whether plane is primary or not.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 10 +
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 34 +++
drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
.
This is borrowed from downstream MDP5 kernel driver. Without this, we
don't see any cursor plane content.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/msm/mdp/m
he crtc (which would de-stage the plane), we would still see the
plane in its last 'visible' configuration.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c | 59 +++
drivers/gpu/drm/msm/msm_atomic.c | 21 +++
2 files ch
has to be staged at the topmost
blender of the LM, which can result in empty stages in between 2) In
the future, when we support multiple LMs per CRTC. We could have stages
which don't have any pipe assigned to them.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c | 2
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index 27d5371..6db1b8b 100644
--- a
Define the block in advance so that the generated mdp5.xml.h doesn't
break build.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
and it seems to
work okay. Are there any tests that mix up atomic commits and legacy
cursor updates a lot to identify issues?
Archit Taneja (9):
drm/msm/mdp5: cfg: Add pipe_cursor block
drm/msm/mdp5: Update generated headers
drm/msm/mdp5: Prepare CRTC/LM for empty stages
drm/msm/mdp5:
TCs we
have.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 39 -
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
index 646f160..84ec
Count can't be non-zero. Changing to uint will also prevent future
warnings.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h
b/drivers/gpu/drm/msm/mdp
rface type. It can use the
the kms func op set_encoder_mode to change the mode of operation, which
in turn would configure the interface type for the INTF.
In mdp5_cmd_encoder.c, we remove the redundant code, and make the commmand
mode funcs as helpers that are used in mdp5_encoder.c
Signed-off-
Rename the mdp5_encoder_* ops for active displays to
mdp5_vid_encoder_* ops.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 31 ++---
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 3 ++-
drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 4
at the DSI device's mode flags are.
Start with providing a way to set the mdp5_intf_mode using a kms
func.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi_manag
e that the
encoder is configured only in video mode. Later, the same encoder
would be usable in both modes.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi.c | 17 ++---
drivers/gpu/drm/msm/dsi/dsi.h | 4 ++--
drivers/gpu/drm/msm/dsi/dsi_manage
The MDP5 and DSI drivers created 2 drm_encoders for a DSI interface (one
for each mode of operation). This patch fixes that.
Now, with the # encoders equal to the # of displays, we can create the
right # of CRTCs. We previously created LM # of CRTCs, which ate up
too many primary planes.
Archit
On 12/14/2016 3:29 PM, Laurent Pinchart wrote:
> Hello,
>
> This patch series is a respin of the DRM bridge attach/detach cleanup patches
> that were previously part of "[PATCH v3 00/13] R-Car DU: Use drm bridge API".
> As patches 1/5 and 3/5 touch a large number of drivers and are thus painful t
On 12/10/2016 3:41 AM, Rob Herring wrote:
> On Mon, Dec 05, 2016 at 01:23:54PM +0530, Archit Taneja wrote:
>> Add the regulator supply properties needed by ADV7511 and ADV7533.
>>
>> Cc: devicetree at vger.kernel.org
>> Acked-by: Laurent Pinchart
>
Hi,
On 12/14/2016 03:29 PM, Laurent Pinchart wrote:
> Instead of linking encoders and bridges in every driver (and getting it
> wrong half of the time, as many drivers forget to set the drm_bridge
> encoder pointer), do so in core code. The drm_bridge_attach() function
> needs the encoder and opti
On 12/14/2016 03:30 PM, Sean Paul wrote:
> On Wed, Dec 14, 2016 at 12:03 AM, Archit Taneja
> wrote:
>> Hi,
>>
>> On 12/12/2016 08:28 PM, Sean Paul wrote:
>>>
>>> On Fri, Dec 9, 2016 at 9:49 PM, Caesar Wang wrote:
>>>>
>>>> L
On 12/13/2016 03:39 PM, Bartosz Golaszewski wrote:
> THS8135 is a configurable video DAC, but no configuration is actually
> necessary to make it work.
>
> For now use the dumb-vga-dac driver to support it.
Queued to drm-misc-next
Archit
>
> Signed-off-by: Bartosz Golaszewski
> Reviewed-by: L
Hi,
On 12/13/2016 03:39 PM, Bartosz Golaszewski wrote:
> THS8135 is a configurable video DAC. Add DT bindings for this chip.
Queued to drm-misc-next
>
> Signed-off-by: Bartosz Golaszewski
> Reviewed-by: Laurent Pinchart
> Acked-by: Rob Herring
> ---
> .../bindings/display/bridge/ti,ths8135.tx
ast link mode during enter and exit the psr,
>> this issue is gone if switching the fast link to main link mode.
>>
>
> Cc: Archit Taneja
Do we want this as a fix in 4.10? Or is it okay to get it in 4.11?
In other words, should this go to drm-misc-next or drm-misc-fixes?
Tha
On 12/13/2016 07:22 PM, Maarten Lankhorst wrote:
> Op 13-12-16 om 14:01 schreef Archit Taneja:
>> Hi,
>>
>> On 12/12/2016 4:04 PM, Maarten Lankhorst wrote:
>>> Do something similar to vc4, only allow updating the cursor state
>>> in-place through a fast
Hi,
On 12/12/2016 4:04 PM, Maarten Lankhorst wrote:
> Do something similar to vc4, only allow updating the cursor state
> in-place through a fastpath when the watermarks are unaffected. This
> will allow cursor movement to be smooth, but changing cursor size or
> showing/hiding cursor will still f
fine for ADV7511 too. Laurent, could we
get an Ack for the series from you?
Thanks,
Archit
>
> thanks
> -john
>
> Cc: David Airlie
> Cc: Archit Taneja
> Cc: Wolfram Sang
> Cc: Lars-Peter Clausen
> Cc: Laurent Pinchart
> Cc: dri-devel at lists.freedesktop.org
On 12/07/2016 06:27 AM, zain wang wrote:
> We will ignored PSR setting if panel not support it. So, in this case, we
> should
> return from analogix_dp_enable/disable_psr() without any error code.
> Let's retrun 0 instead of -EINVAL when panel not support PSR in
> analogix_dp_enable/disable_psr(
Maintain a table of regulator names expect by ADV7511 and ADV7533.
Use regulator_bulk_* api to configure these.
Initialize and enable the regulators during probe itself. Controlling
these dynamically is left for later.
Reviewed-by: Laurent Pinchart
Signed-off-by: Archit Taneja
---
drivers/gpu
Add the regulator supply properties needed by ADV7511 and ADV7533.
Cc: devicetree at vger.kernel.org
Acked-by: Laurent Pinchart
Signed-off-by: Archit Taneja
---
Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt | 8
1 file changed, 8 insertions(+)
diff --git a
Have separate supply entries for AVDD, DVDD, PVDD, A2VDD pins.
- Use regulator_bulk_* API to configure regulators.
Archit Taneja (2):
dt-bindings: drm/bridge: adv7511: Add regulator bindings
drm/bridge: adv7511: Initialize regulators
.../bindings/display/bridge/adi,adv7511.txt
On 12/02/2016 09:33 PM, Sean Paul wrote:
> On Thu, Dec 1, 2016 at 10:54 PM, Archit Taneja
> wrote:
>> Hi,
>>
>> On 12/02/2016 08:02 AM, zain wang wrote:
>>>
>>> We will ignored PSR setting if panel not support it. So, in this case, we
>>> sh
Hi,
On 12/02/2016 08:02 AM, zain wang wrote:
> We will ignored PSR setting if panel not support it. So, in this case, we
> should
> return from analogix_dp_enable/disable_psr() without any error code.
> Let's retrun 0 instead of -EINVAL when panel not support PSR in
> analogix_dp_enable/disable_p
On 11/30/2016 05:18 PM, Lucas Stach wrote:
> ASSR is an optional feature, so it's a valid operating condition for
> the display to reject ASSR enable. Demote the warning to the debug
> level.
Lgtm. Will pull it if Philipp or Andrey don't have any comments on it.
Thanks,
Archit
>
> Signed-off-b
On 11/30/2016 4:35 PM, Laurent Pinchart wrote:
> Hi Archit,
>
> On Wednesday 30 Nov 2016 16:30:53 Archit Taneja wrote:
>> On 11/30/2016 03:53 PM, Laurent Pinchart wrote:
>>> On Wednesday 30 Nov 2016 10:35:02 Archit Taneja wrote:
>>>> On 11/29/2016 11:27
On 11/30/2016 03:53 PM, Laurent Pinchart wrote:
> Hi Archit,
>
> On Wednesday 30 Nov 2016 10:35:02 Archit Taneja wrote:
>> On 11/29/2016 11:27 PM, Laurent Pinchart wrote:
>>> On Tuesday 29 Nov 2016 15:57:06 Archit Taneja wrote:
>>>> On 11/29/2016 02:34 PM, L
On 11/29/2016 11:27 PM, Laurent Pinchart wrote:
> Hi Archit,
>
> On Tuesday 29 Nov 2016 15:57:06 Archit Taneja wrote:
>> On 11/29/2016 02:34 PM, Laurent Pinchart wrote:
>>> Instead of linking encoders and bridges in every driver (and getting it
>>> wrong half of
getting lost. Using the logic
> in __adv7511_power_on/off() which syncs and dirtys the cache
> avoids this issue.
>
> Thus this patch changes the EDID probing logic so that we
> re-use the __adv7511_power_on/off() calls.
>
> Cc: David Airlie
> Cc: Archit Taneja
> Cc: Wol
On 11/29/2016 02:34 PM, Laurent Pinchart wrote:
> Most drivers that use bridges forgot to detach them at cleanup time.
> Instead of fixing them one by one, detach the bridge in the core
> drm_encoder_cleanup() function.
>
> Signed-off-by: Laurent Pinchart
> ---
> drivers/gpu/drm/drm_encoder.c |
On 11/29/2016 02:34 PM, Laurent Pinchart wrote:
> Instead of linking encoders and bridges in every driver (and getting it
> wrong half of the time, as many drivers forget to set the drm_bridge
> encoder pointer), do so in core code. The drm_bridge_attach() function
> needs the encoder and optiona
On 11/29/2016 12:03 PM, Laurent Pinchart wrote:
> Hi Archit,
>
> Thank you for the patch.
>
> On Tuesday 29 Nov 2016 11:37:41 Archit Taneja wrote:
>> Add the regulator supply properties needed by ADV7511 and ADV7533.
>>
>> The regulators are specified as optional
Maintain a table of regulator names expect by ADV7511 and ADV7533.
Use regulator_bulk_* api to configure these.
Initialize and enable the regulators during probe itself. Controlling
these dynamically is left for later.
Signed-off-by: Archit Taneja
---
v3:
- Drop the additional 1.8V supply names
: Rob Herring
Signed-off-by: Archit Taneja
---
v3:
- Revert back to having a common avdd-supply property for the 1.8V
supplies
Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt | 9 +
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/display
lator supply for ADV7511 too in the binding docs.
- Update the driver to manage regulators for both ADV7511 and ADV7533.
- Have separate supply entries for AVDD, DVDD, PVDD, A2VDD pins.
- Use regulator_bulk_* API to configure regulators.
Archit Taneja (2):
dt-bindings: drm/bridge: adv7511: Add regu
On 11/28/2016 06:37 AM, Kuninori Morimoto wrote:
>
> Hi
>
>> The newly added sound driver depends on SND_SOC_HDMI_CODEC, which in
>> turn only makes sense when ASoC is enabled, as shown by this warning:
>>
>> warning: (DRM_MSM && DRM_STI && DRM_MEDIATEK_HDMI && DRM_I2C_NXP_TDA998X &&
>> DRM_DW_H
Hi,
On 11/24/2016 10:43 AM, Kuninori Morimoto wrote:
>
> Hi Archit, David, and DRM ML
>
> I had heared that Archit is the maintainer of dw-hdmi driver, but am I wrong
> ??
> I'm posting this patch series since half year ago, but no response
> from him, and nothing happen (I got review from Russel
On 11/23/2016 01:16 AM, John Stultz wrote:
> On Tue, Nov 22, 2016 at 9:38 AM, Laurent Pinchart
> wrote:
>> Hi John,
>>
>> On Tuesday 22 Nov 2016 09:25:22 John Stultz wrote:
>>> On Tue, Nov 22, 2016 at 12:14 AM, Laurent Pinchart wrote:
On Monday 21 Nov 2016 16:37:30 John Stultz wrote:
>>> @
t;
> I typed this to give Manasi a place to add her new link status
> property documentation.
Reviewed-by: Archit Taneja
>
> v2: forgot to git add all the bits (Manasi).
>
> v3: Be more epxlicit about integrated tiled panels (Archit)
>
> Cc: Manasi Navare
&g
On 11/17/2016 01:25 PM, Chen-Yu Tsai wrote:
> On Thu, Nov 17, 2016 at 3:48 PM, Archit Taneja
> wrote:
>> Hi,
>>
>> Thanks for the patch.
>>
>>
>> On 11/16/2016 09:12 PM, Chen-Yu Tsai wrote:
>>>
>>> Some dumb VGA DACs are active
On 11/17/2016 01:08 PM, Daniel Vetter wrote:
> There's a really big pile of additional connector properties, a lot of
> them standardized. But they're all for specific outputs (panels, TV,
> scaling, ...) so I left them out for now since this is enough for a
> start.
>
> I typed this to give Mana
Hi,
Thanks for the patch.
On 11/16/2016 09:12 PM, Chen-Yu Tsai wrote:
> Some dumb VGA DACs are active components which require external power.
> Add support for specifying a regulator as its power supply.
>
> Signed-off-by: Chen-Yu Tsai
> Acked-by: Rob Herring
> ---
> .../bindings/display/brid
.
Remove the extra of_node_put calls. This fixes warnings seen when
we try to insert the driver as a module on IFC6410.
Reported-by: Ilia Mirkin
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/msm_drv.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm
On 11/16/2016 07:38 PM, Daniel Vetter wrote:
> Again something that's in the drm-misc fold.
Acked-by: Archit Taneja
>
> Cc: Archit Taneja
> Signed-off-by: Daniel Vetter
> ---
> MAINTAINERS | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/M
Hi,
On 11/15/2016 08:29 AM, Chen-Yu Tsai wrote:
> Hi,
>
> On Wed, Nov 2, 2016 at 9:33 AM, Chen-Yu Tsai wrote:
>> On Mon, Oct 31, 2016 at 2:28 PM, Rob Herring wrote:
>>> On Sat, Oct 29, 2016 at 07:06:10PM +0800, Chen-Yu Tsai wrote:
Some dumb VGA DACs are active components which require exter
On 11/15/2016 10:39 PM, Sean Paul wrote:
> On Thu, Nov 3, 2016 at 3:17 AM, Jianqun Xu wrote:
>> Reference from drm_dp_aux description (about transfer):
>> Upon success, the implementation should return the number of payload bytes
>> that were transferred, or a negative error-code on failure. Hel
Hi,
On 11/14/2016 07:11 PM, Jitao Shi wrote:
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Thanks for the incorporating the fixes. I have commented on one issue
below.
The only thing that seems to be left now is the firmware update bits, right?
Can we get the firmware
Hi Jitao,
I couldn't locate the original mail, so posting on this thread instead.
Some comments below.
On 11/10/2016 10:09 PM, Enric Balletbo Serra wrote:
> Hi Jitao,
>
> 2016-08-27 8:44 GMT+02:00 Jitao Shi :
>> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>>
>> Signed-off
On 11/7/2016 8:18 PM, Rob Clark wrote:
> On Mon, Nov 7, 2016 at 5:38 AM, Archit Taneja
> wrote:
>>
>>
>> On 11/05/2016 09:55 PM, Rob Clark wrote:
>>>
>>> Split out the hardware pipe specifics from mdp5_plane. To start, the hw
>>> pipes are
N layer-mixers (LM). The first N planes become primary
> + * planes for the CRTCs, with the remainder as overlay planes:
> + */
Jfyi, we might need to change this a bit in the future. It'll be better to
get the max number of displays connected on our platform via parsing D
Hi,
Minor comments below. LGTM otherwise.
On 11/05/2016 09:56 PM, Rob Clark wrote:
> (re)assign the hw pipes to planes based on required caps, and to handle
> situations where we could not modify an in-use plane (ie. SMP block
> reallocation).
>
> This means all planes advertise the superset of f
>pdev = pdev;
>
> + drm_modeset_lock_init(&mdp5_kms->state_lock);
> + mdp5_kms->state = kzalloc(sizeof(*mdp5_kms->state), GFP_KERNEL);
> + if (!mdp5_kms->state) {
> + ret = -ENOMEM;
> + goto fail;
> + }
> +
This would pro
;funcs is also
non-NULL. This is needed for MDP5, since during msm_drm_int(), priv->kms
becomes non-NULL early, but msm_kms_init() is called on it only later
in mdp5_kms_init().
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/msm_drv.c | 2 +-
drivers/gpu/drm/msm/msm_gem_sh
On 10/25/2016 02:29 PM, Chen-Yu Tsai wrote:
> On Tue, Oct 25, 2016 at 4:09 PM, Archit Taneja
> wrote:
>> Hi,
>>
>> On 10/20/2016 09:13 AM, Chen-Yu Tsai wrote:
>>>
>>> Some rgb-to-vga bridges have an enable GPIO, either directly tied to
>>
terface clocks/power domains beforehand.
We set the CLK_IGNORE_UNUSED flag for PLL clocks for now. This needs to be
revisited, since bootloaders can enable display, and we would want to
disable the PLL clocks if there isn't a display driver using them.
Cc: Stephen Boyd
Signed-off-by: Archit Taneja
On 10/10/2016 01:09 PM, Andrzej Hajda wrote:
> SiI8620 transmitter converts eTMDS/HDMI signal to MHL 3.0.
> It is controlled via I2C bus. Its interaction with other
> devices in video pipeline is performed mainly on HW level.
> The only interaction it does on device driver level is
> filtering-ou
On 10/07/2016 12:32 PM, Andrzej Hajda wrote:
> SiI8620 transmitter converts eTMDS/HDMI signal to MHL 3.0. It is controlled
> via I2C bus.
queued to drm-misc.
Thanks,
Archit
>
> Signed-off-by: Andrzej Hajda
> Acked-by: Rob Herring
> ---
> .../bindings/video/bridge/sil-sii8620.txt |
On 10/07/2016 12:32 PM, Andrzej Hajda wrote:
> This header adds definitions specific to MHL protocol.
queued to drm-misc.
Thanks,
Archit
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 10/26/2016 01:58 AM, Stephen Boyd wrote:
> On 10/25, Archit Taneja wrote:
>> The DSI/HDMI PLLs in MSM require resources like interface clocks, power
>> domains to be enabled before we can access their registers.
>>
>> The clock framework doesn't have a mech
Hi Andrzej,
On 10/10/2016 01:09 PM, Andrzej Hajda wrote:
> SiI8620 transmitter converts eTMDS/HDMI signal to MHL 3.0.
> It is controlled via I2C bus. Its interaction with other
> devices in video pipeline is performed mainly on HW level.
> The only interaction it does on device driver level is
> f
On 10/20/2016 09:13 AM, Chen-Yu Tsai wrote:
> The Hummingbird A31 board has a RGB-to-VGA bridge which converts RGB
> output from the LCD interface to VGA signals.
>
> Enable this part of the display pipeline.
I couldn't find the enable-gpios binding for the bridge that you
introduced in the prev
Hi,
On 10/20/2016 09:13 AM, Chen-Yu Tsai wrote:
> Some rgb-to-vga bridges have an enable GPIO, either directly tied to
> an enable pin on the bridge IC, or indirectly controlling a power
> switch.
>
> Add support for it.
Does the bridge on your platform have an active/passive DAC, or is it a
smar
terface clocks/power domains beforehand.
We remove the is_enabled clk_ops from the PLL clocks for now since they
aren't mandatory. This needs to be revisited, since bootloaders can enable
display, the enable count maintained by clock framework wouldn't work in
such cases.
Cc: Stephen Boyd
work instead.
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index f05ed0e..6f24002 100644
--- a/drivers/gpu/drm/ms
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