Same as rev 2, except for patch 3/3 v3 to apply Nicholas
latest feedback into account. Retested on DCN1 and DCE8.
thanks,
-mario
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ons
(low fps to high fps) < DCE-12 is a little bit improved,
although by far not as much as for up-sweeps and constant
fps.
v2: Fix some wrong locking, as pointed out by Nicholas.
Signed-off-by: Mario Kleiner
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 45 +--
1 file c
and prevents missed vblanks at the border
between non-BTR and BTR.
Testing on DCE-8, DCE-11 and DCN-1.0 shows that this more
often avoids skipped frames when moving across the BTR
boundary, especially on DCE-8 and DCE-11 with the followup
commit for dealing with pre-DCE-12 hw.
Signed-off-by: Mario Kleiner
The comparison of inserted_frame_duration_in_us against a
duration calculated from max_refresh_in_uhz is both wrong
in its math and not needed, as the min_duration_in_us value
is already cached in in_out_vrr for reuse. No need to
recalculate it wrongly at each invocation.
Signed-off-by: Mario
Updated series. The debug patch is dropped, a r-b by Nicholas is tacked
onto patch 1/3 and patch 3/3 has the locking fix that Nicholas proposed.
In terms of testing 3/3 didn't change anything for the better or worse,
observed behaviour on retested DCN-1 and DCE-8 is the same.
Patch 2/3 is
On Wed, Apr 24, 2019 at 4:34 PM Kazlauskas, Nicholas
wrote:
>
> On 4/17/19 11:51 PM, Mario Kleiner wrote:
> > Pre-DCE12 needs special treatment for BTR / low framerate
> > compensation for more stable behaviour:
> >
> > According to comments in the code and some t
behaviour present
in Linux 5.0/5.1.
Fixes: ab7a664f7a2d ("drm: Document variable refresh properties")
Link: https://patchwork.freedesktop.org/patch/285333/
Signed-off-by: Mario Kleiner
---
drivers/gpu/drm/drm_connector.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drive
ons
(low fps to high fps) < DCE-12 is a little bit improved,
although by far not as much as for up-sweeps and constant
fps.
Signed-off-by: Mario Kleiner
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/d
The comparison of inserted_frame_duration_in_us against a
duration calculated from max_refresh_in_uhz is both wrong
in its math and not needed, as the min_duration_in_us value
is already cached in in_out_vrr for reuse. No need to
recalculate it wrongly at each invocation.
Signed-off-by: Mario
Helps with debugging issues with low framerate compensation.
Signed-off-by: Mario Kleiner
---
.../amd/display/modules/freesync/freesync.c| 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c
b/drivers/gpu/drm/amd
Hi
This patch-series tries to improve amdgpu's below-the-range
behaviour with Freesync, hopefully not only for my use case,
but also for games etc.
Patch 1/4 adds a bit of debug output i found very useful, so maybe
worth adding?
Patch 2/4 fixes a bug i found when reading over the freesync code.
and prevents missed vblanks at the border
between non-BTR and BTR.
Testing on DCE-8, DCE-11 and DCN-1.0 shows that this more
often avoids skipped frames when moving across the BTR
boundary, especially on DCE-8 and DCE-11 with the followup
commit for dealing with pre-DCE-12 hw.
Signed-off-by: Mario Kleiner
if we are in case a) or b),
we check the current scanout position against the boundary of
front-porch. In non-VRR mode we just do what we did in the past.
Signed-off-by: Mario Kleiner
Reviewed-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 68 +++
1
-by: Mario Kleiner
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 36 +++
1 file changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6528258f8975..6c413bc012af 100644
--- a/drivers
.
v2: Implement feedback by Nicholas and Paul Menzel.
Signed-off-by: Mario Kleiner
Acked-by: Harry Wentland
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 128 +-
.../gpu/drm/amd
after it, without a negative impact on flip
throttling, so followup patches can shift the vblank core
handling trigger point wherever they need it.
Signed-off-by: Mario Kleiner
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +-
.../gpu/drm/amd/display
at the beginning of commit tail before the
vrr transition handling, and a late part that must run after
vrr transition handling inside the commit planes code for
enabled crtc's.
Suggested by Nicholas Kazlauskas.
Signed-off-by: Mario Kleiner
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 61
The hopefully final patch series, with feedback applied and
r-b / acked-by tags added. Rebased to current agd5f/drm-5.2-wip
branch.
Numbering has slightly changed. Patches 3-5 are identical to last
series. Patch 2/5 v3 (the former 1/4 v2) trivially rebased on top of
the new 1/5.
Patch 1/5 is new
.
v2: Implement feedback by Nicholas and Paul Menzel.
Signed-off-by: Mario Kleiner
Acked-by: Harry Wentland
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 128 +-
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 9
The current patch series, with feedback from Paul, Nicholas and Harry
applied and r-b / acked-by tags added. Thanks for the feedback.
Rebased to current drm-5.2-wip branch.
Patch 1/4 is still the same though. Don't know if i or Nicholas could
fix it in a followup patch, or this one needs more
refresh rate non-VRR mode.
v2: Make sure transition is also handled if vrr is
disabled and stream gets disabled in the same
atomic commit. Suggested by Nicholas.
Signed-off-by: Mario Kleiner
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 36 +++
1 file changed, 36
if we are in case a) or b),
we check the current scanout position against the boundary of
front-porch. In non-VRR mode we just do what we did in the past.
Signed-off-by: Mario Kleiner
Reviewed-by: Nicholas Kazlauskas
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 68 +++
1
after it, without a negative impact on flip
throttling, so followup patches can shift the vblank core
handling trigger point wherever they need it.
Signed-off-by: Mario Kleiner
Reviewed-by: Nicholas Kazlauskas
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +-
.../gpu/drm/amd/display
On Wed, Mar 20, 2019 at 1:53 PM Kazlauskas, Nicholas
wrote:
>
> On 3/20/19 3:51 AM, Mario Kleiner wrote:
> > Ok, fixed all the style issues and ran checkpatch over the patches. Thanks.
> >
> > On Tue, Mar 19, 2019 at 2:32 PM Kazlauskas, Nicholas
> > wrote
On Wed, Mar 20, 2019 at 2:11 PM Kazlauskas, Nicholas
wrote:
>
> On 3/20/19 4:12 AM, Mario Kleiner wrote:
> > During VRR mode we can not allow vblank irq dis-/enable
> > transitions, as an enable after a disable can happen at
> > an arbitrary time during the
On Mon, Mar 18, 2019 at 6:29 PM Kazlauskas, Nicholas
wrote:
>
> On 3/18/19 1:19 PM, Mario Kleiner wrote:
> > During VRR mode we can not allow vblank irq dis-/enable
> > transitions, as an enable after a disable can happen at
> > an arbitrary time during the
refresh rate non-VRR mode.
v2: Make sure transition is also handled if vrr is
disabled and stream gets disabled in the same
atomic commit. Suggested by Nicholas.
Signed-off-by: Mario Kleiner
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 36 +++
1 file changed
Ok, fixed all the style issues and ran checkpatch over the patches. Thanks.
On Tue, Mar 19, 2019 at 2:32 PM Kazlauskas, Nicholas
wrote:
>
> On 3/19/19 9:23 AM, Kazlauskas, Nicholas wrote:
> > On 3/18/19 1:19 PM, Mario Kleiner wrote:
> >> In VRR mode, proper vblank/pagefli
if we are in case a) or b),
we check the current scanout position against the boundary of
front-porch. In non-VRR mode we just do what we did in the past.
Signed-off-by: Mario Kleiner
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 68 ++-
1 file changed, 55 insertions
.
Signed-off-by: Mario Kleiner
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 1 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 129 -
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 9 ++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 22
after it, without a negative impact on flip
throttling, so followup patches can shift the vblank core
handling trigger point wherever they need it.
Signed-off-by: Mario Kleiner
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23
refresh rate non-VRR mode.
Signed-off-by: Mario Kleiner
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index
Hi
This series implements properly working vblank and pageflip completion
timestamping for amdgpu in VRR / FreeSync mode.
Now pageflip timestamps for pageflip events always carry the
vblank timestamp of the vblank in which the flip completed,
and the vblank timestamp is as accurate as in fixed
>
> > >> On 2/13/19 4:50 AM, Daniel Vetter wrote:
> > >>> On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
> > >>>> On Mon, Feb 11, 2019 at 6:04 PM Daniel Vetter wrote:
> > >>>>>
> > >>>>
On Wed, Feb 13, 2019 at 10:50 AM Daniel Vetter wrote:
>
> On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
> > On Mon, Feb 11, 2019 at 6:04 PM Daniel Vetter wrote:
> > >
> > > On Mon, Feb 11, 2019 at 4:01 PM Kazlauskas, Nicholas
> > > wr
On Wed, Feb 13, 2019 at 10:56 AM Chris Wilson wrote:
>
> Quoting Daniel Vetter (2019-02-13 09:50:55)
> > On Tue, Feb 12, 2019 at 10:32:31PM +0100, Mario Kleiner wrote:
> > > I think all kms drivers try to call drm_crtc_handle_vblank() at start
> > > of vbl
On Mon, Feb 11, 2019 at 6:04 PM Daniel Vetter wrote:
>
> On Mon, Feb 11, 2019 at 4:01 PM Kazlauskas, Nicholas
> wrote:
> >
> > On 2/11/19 3:35 AM, Daniel Vetter wrote:
> > > On Mon, Feb 11, 2019 at 04:22:24AM +0100, Mario Kleiner wrote:
> > >> The
On Mon, Feb 11, 2019 at 7:44 PM Kazlauskas, Nicholas
wrote:
>
> On 2/11/19 10:01 AM, Michel Dänzer wrote:
> > On 2019-02-09 7:52 a.m., Mario Kleiner wrote:
> >> In VRR mode, keep track of the vblank count of the last
> >> completed pageflip in amdgpu_crtc->l
Oops, dropped the mailing ist from my reply, so again...
On Mon, Feb 11, 2019 at 4:01 PM Michel Dänzer wrote:
>
> On 2019-02-09 7:52 a.m., Mario Kleiner wrote:
> > In VRR mode, keep track of the vblank count of the last
> > completed pageflip in amdgpu_crtc->last_flip_vb
e stable
timestamp for future improvements of the pageflip timestamping under
vrr.
Fixes: 520f08df45fb ("drm/amdgpu: Correct get_crtc_scanoutpos behavior
when vpos >= vtotal")
Signed-off-by: Mario Kleiner
Cc:
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Alex Deucher
These fix the currently broken vblank timestamping in VRR
mode and broken pageflip timestamping in VRR mode. The unfixed
implementation can provide timestamps that are off by dozens
of milliseconds and thereby make VRR unusable for any application
that needs at least millisecond precision in
potentially dozens of milliseconds
to probably less than 2 msecs in the common case, given the fixed
and short back-porch duration and the usually low interrupt dispatch
delay from pageflip interrupt.
Signed-off-by: Mario Kleiner
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Alex Deucher
he exact end time of vblank.
Signed-off-by: Mario Kleiner
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Alex Deucher
---
drivers/gpu/drm/drm_vblank.c | 49 +++-
include/drm/drm_vblank.h | 8 ++
2 files changed, 56 insertions(+), 1 deletion(-)
diff --git
ate.
Fixes: bb47de736661 ("drm/amdgpu: Set FreeSync state using drm VRR
properties")
Signed-off-by: Mario Kleiner
Cc:
Cc: Nicholas Kazlauskas
Cc: Harry Wentland
Cc: Alex Deucher
Cc: Michel Dänzer
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 1 +
.../gpu/drm/amd/display/amdgpu_d
Cc'ing mesa-dev, which was left out.
On 03/05/2018 01:40 PM, Ilia Mirkin wrote:
On Mon, Mar 5, 2018 at 2:25 AM, Mario Kleiner
<mario.kleiner...@gmail.com> wrote:
On 02/05/2018 12:50 AM, Ilia Mirkin wrote:
In case anyone's curious about 30bpp framebuffer support, here's the
current
On 02/05/2018 12:50 AM, Ilia Mirkin wrote:
In case anyone's curious about 30bpp framebuffer support, here's the
current status:
Kernel:
Ben and I have switched the code to using a 256-based LUT for Kepler+,
and I've also written a patch to cause the addfb ioctl to use the
proper format. You
"AEO", 0, EDID_QUIRK_FORCE_6BPC },
+ /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
+ { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
+
/* Belinea 10 15 55 */
{ "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
{ "MAX&qu
On 09/26/2017 07:05 AM, Daniel Vetter wrote:
On Fri, Sep 15, 2017 at 05:48:25PM +0200, Mario Kleiner wrote:
The new module parameter enable_hw_color_correction defaults to
true, to retain the current behaviour. If set to false, it will
disable all hardware color correction, like gamma/degamma
, to have an override
for DE's which may not expose such properties via some standard
protocol in a user-controllable way, e.g., afaik all currently
existing Wayland compositors.
Tested on Ironlake, IvyBridge, Haswell, Skylake.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
---
d
ts the effective output precision to 8 bit, while an
auto-bypassed precision lut doesn't restrict precision.
Iow. this patch is needed even with XR30 fb's for actual 10
bit precision output, even though the hw seems to sort of ignore
the tested gamma tables for XR30 fb's.
Signed-off-b
Hi,
so these two patches add i915 module parameters to globally override
how the driver handles dithering and gamma/csc conversion.
They serve two purposes: First as debug aid and "airbag" for working
around potential precision problems in getting pixels from rendering
to the display outputs.
On 07/24/2017 03:45 PM, Florian Echtler wrote:
Hello Lukas,
On 17.07.2017 11:02, Lukas Wunner wrote:
On Fri, Jun 02, 2017 at 06:47:07PM +0200, Florian Echtler wrote:
Sorry for the delay Florian. Commit 564d8a2cf3ab by Mario Kleiner (+cc)
landed in Linus' tree last week and is included
eak other DCE3.2 systems. Use dmi_match() to
apply this special encoder assignment only for the
Apple iMac 10,1 from late 2009.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Cc: Alex Deucher <alexander.deuc...@amd.com>
Cc: Michel Dänzer <michel.daen...@amd.c
On 06/21/2017 06:19 PM, Eric Anholt wrote:
Mario Kleiner <mario.kleiner...@gmail.com> writes:
With instantaneous high precision vblank timestamping
that updates at leading edge of vblank, the emulated
"hw vblank counter" from vblank timestamping which
increments at leadin
offdelay=0
would keep vblank irqs on to approximate old behavior.
v2: Respin onto drm-misc-next, per Eric's suggestion.
Drop !vc4->firmware_kms check, as the firmware_kms
implementation does not exist in upstream.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
(or echo 0 > /sys/module/drm/parameters/vblankoffdelay)
would keep vblank irqs permanently on to approximate old
behavior.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Cc: Alex Deucher <alexander.deuc...@amd.com>
Cc: Michel Dänzer <michel.daen...@amd.com>
---
d
offdelay=0
would keep vblank irqs on to approximate old behavior.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Cc: Eric Anholt <e...@anholt.net>
---
drivers/gpu/drm/vc4/vc4_kms.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers
ith kernel cmdline option drm.vblankoffdelay=0
(or echo 0 > /sys/module/drm/parameters/vblankoffdelay)
would keep vblank irqs permanently on to approximate old
behavior.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Cc: Ben Skeggs <bske...@redhat.com>
---
drivers/gpu/drm/n
drm.vblankoffdelay=0
(or echo 0 > /sys/module/drm/parameters/vblankoffdelay)
would keep vblank irqs permanently on to approximate old
behavior.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Cc: Alex Deucher <alexander.deuc...@amd.com>
Cc: Michel Dänzer <michel.daen...@amd.com
This patch series sets dev->vblank_disable_immediate = true on
radeon/amdgpu-kms, nouveau-kms for nv50+, and vc4 for the real
kms driver (as opposed to dispmanx firmware backed kms).
All the drivers should be ready in theory, given their implementation,
for fast vblank disable/enable. In
and division.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Reported-by: Ben Hutchings <ben.hutchi...@codethink.co.uk>
Fixes: e6b9a6c84b93 ("drm/radeon: Make display watermark calculations more
accurate")
Cc: Ben Hutchings <ben.hutchi...@codethink.co.uk>
Cc
r u64 casting and division.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Reported-by: Ben Hutchings <ben.hutchi...@codethink.co.uk>
Fixes: d63c277dc672 ("drm/amdgpu: Make display watermark calculations more
accurate")
Cc: Ben Hutchings <ben.hutchi...@codethink.c
ed out that the problem had been introduced by commit
210a021dab639694600450c14b877bf3e3240adc
commit 210a021dab639694600450c14b877bf3e3240adc
Author: Mario Kleiner <mario.kleiner...@gmail.com>
Date: Wed Jul 6 12:05:48 2016 +0200
drm/edid: Set 8 bpc color depth for displays with "DFP 1.x com
On 05/05/2017 04:25 PM, Keith Packard wrote:
Pekka Paalanen writes:
I disagree on the details, more below.
Such a RandR request is something I would not like to have to replicate
on Wayland. The display server contains the policy, it should not just
expose everything
On 05/05/2017 09:35 PM, Daniel Vetter wrote:
On Mon, Jul 25, 2016 at 1:15 PM, Rainer Hochecker wrote:
Am 25.07.2016 08:38 schrieb "Michel Dänzer" :
On 13.07.2016 18:49, Rainer Hochecker wrote:
We have been using this for years now and did not observe
A missing u64 cast causes a 32-Bit wraparound from
4096 MiB to 0 MiB and therefore total 0 MiB VRAM detected
if card has 4096 Mib per FBP.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
---
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 2 +-
1 file changed, 1 insertion
ing or flip completion timestamps.
Tested on R9 380 Tonga.
v2: Add acked/r-b by Harry and Michel.
v3: Feedback from Andrey: Must not wait an extra frame for
DRM_MODE_PAGE_FLIP_ASYNC flips.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Acked-by: Harry Wentland <harry.went
off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
Reviewed-by: Michel Dänzer <michel.daen...@amd.com>
Cc: Harry Wentland <harry.wentl...@amd.com>
Cc: Alex Deucher <alexander.deuc...@amd.com>
Cc: Michel Dänzer <michel.d
agraph
about problem already fixed in 2nd patch of the series.
Add acked/r-b by Harry and Michel.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
Reviewed-by: Michel Dänzer <michel.daen...@amd.com>
Cc: Andrey Gro
of uptime in a hard
to reproduce manner.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Cc: Ben Skeggs <bske...@redhat.com>
---
drivers/gpu/drm/nouveau/nouveau_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_
ned-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Cc: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/radeon/cik.c | 10 +-
drivers/gpu/drm/radeon/evergreen.c | 10 +-
drivers/gpu/drm/radeon/si.c| 10 +-
3 files changed, 15 in
rom dce-8 and si from dce-6, with a slightly
simpler variant for evergreen dce-4/5.
Only tested on DCE-4 evergreen with a Radeon HD-5770.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Cc: Alex Deucher <alexander.deuc...@amd.com>
---
drivers/gpu/drm/radeon/c
Hi,
a direct port of the patches we already have in amdgpu,
for completeness.
These are tested on an old HD-5770, DCE4 only.
-mario
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This apparently got lost when implementing the new DCE-6 support
and would cause failures in pageflip scheduling and timestamping.
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Cc: Alex Deucher <alexander.deuc...@amd.com>
Cc: sta...@vger.kernel.org
---
drivers/gpu/dr
Hi
These two patches were written and tested against Harry's
hwentland amd-staging-dc-drm-next branch from a few days ago.
Not sure if that is the right one to base dal/dc patches against,
but it looks recent and active enough?
They fix pageflip scheduling to always flip at the right target
ank event, which itself gets
dispatched inside the vblank one frame before the target_msc vblank.
Testing with this patch does no longer show any problems with
OML_sync_control swap scheduling or flip completion timestamps.
Tested on R9 380 Tonga.
Signed-off-by: Mario Kleiner <mario.k
mdgpu_dm_do_flip().
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
Cc: Harry Wentland <harry.wentl...@amd.com>
Cc: Andrey Grodzovsky <andrey.grodzov...@amd.com>
Cc: Alex Deucher <alexander.deuc...@amd.com>
Cc: Michel Dänzer <michel.daen...@amd.com>
---
drivers
Signed-off-by: Mario Kleiner <mario.kleiner...@gmail.com>
---
drivers/gpu/drm/drm_edid.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index fad3d44..2e55599 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/g
On 04/10/2017 08:11 PM, Keith Packard wrote:
Mario Kleiner <mario.kleiner...@gmail.com> writes:
as input from a highly interested future user of such api's:
Thanks much for taking a look at this.
My use cases run about 98% of the time in fullscreen
exclusive mode and want as
On 04/04/2017 06:48 PM, Keith Packard wrote:
Daniel Vetter writes:
Yeah I think that's a pretty neat idea to reduce the lease complexity even
more. If the VR compositor is unhappy and wants a different mode, it can
simply nuke the lease and as for a new one. Forgot to say
Avoid big roundoff errors in scanline/hactive durations for
high pixel clocks, especially for >= 500 Mhz, and thereby
program more accurate display fifo watermarks.
Implemented here for DCE 6,8,10,11.
Successfully tested on DCE 10 with AMD R9 380 Tonga.
Signed-off-by: Mario Klei
happened, e.g., on AMD Tonga Pro under DCE-10,
on a Displayport panel when trying to set a video mode of 2560x1440
at 165 Hz vrefresh with a dot clock of 635.540 Mhz.
Refine calculations to avoid the overflows.
Tested for DCE-10 with R9 380 Tonga + ASUS ROG PG279 panel.
Signed-off-by: Mario
Hi,
attached two patches for amdgpu to improve the accuracy of display wm
calculations, and to avoid some overflow and divide-by-zero errors which
can cause the driver to die.
Both are tested for the DCE-10 code path with a AMD R9 380 Tonga Pro
on two different panels and their various modes.
ntel.com>
Cc: Daniel Vetter <dan...@ffwll.ch>
Cc: Michel Dänzer <mic...@daenzer.net>
Cc: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
Cc: Dave Airlie <airl...@redhat.com>,
Cc: Mario Kleiner <mario.kleiner...@gmail.com>
---
drivers/gpu/drm/drm_irq.c | 18
following the wait completion.
However, if the user is simply querying the current vblank counter and
timestamp, the interrupt will be disabled after every IRQ and the user
will enabled it again on the first query following the IRQ.
v2: Mario Kleiner -
After testing this, one more thing that would make
On 11/21/2016 05:50 PM, Hans de Goede wrote:
We need to call drm_helper_hpd_irq_event() on resume to properly detect
monitor connection / disconnection on some laptops, use hpd_work for
this to avoid deadlocks.
Hi,
this seems to introduce a hang of nouveau in 4.10-rc if the gpu is
runtime
-off-by: Mario Kleiner
Cc: Ben Skeggs
---
drivers/gpu/drm/nouveau/nv50_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c
b/drivers/gpu/drm/nouveau/nv50_display.c
index a9855a4..ad9aedb 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b
from our exported bo.
- Also switch to exclusive fence for prime imported bo's.
v5: - Drop lret, instead use int ret -> long ret, as proposed
by Christian.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95472
Tested-by: Mike Lothian (v1)
Signed-off-by: Mario Kleiner
Revie
from our exported bo.
- Also switch to exclusive fence for prime imported bo's.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95472
Tested-by: Mike Lothian (v1)
Signed-off-by: Mario Kleiner
Cc: Christian König
Cc: Michel Dänzer
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h
On 11/07/2016 08:55 AM, Christian König wrote:
> Am 07.11.2016 um 04:29 schrieb Michel Dänzer:
>> On 07/11/16 11:47 AM, Mario Kleiner wrote:
>>> External clients which import our bo's wait only
>>> for exclusive dmabuf-fences, not on shared ones,
>>>
://bugs.freedesktop.org/show_bug.cgi?id=95472
(v1) Tested-by: Mike Lothian
Signed-off-by: Mario Kleiner
Cc: Christian König
Cc: Michel Dänzer
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 14
On 11/05/2016 01:06 PM, Christian König wrote:
> Am 05.11.2016 um 01:56 schrieb Mario Kleiner:
>> External clients which import our bo's wait only
>> for exclusive dmabuf-fences, not on shared ones,
>> so attach fences on such exported buffers as
>> exclusive ones.
>
On 10/28/2016 07:48 PM, Christian König wrote:
> Am 28.10.2016 um 19:37 schrieb Mario Kleiner:
>>
>>
>> On 10/28/2016 03:34 AM, Michel Dänzer wrote:
>>> On 27/10/16 10:33 PM, Mike Lothian wrote:
>>>>
>>>> Just another gentle ping to see w
as DRI3/Present
Prime render offload, and with the Tonga standalone as
primary gpu.
v2: Add a wait for all shared fences before prime export,
as suggested by Christian Koenig.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95472
(v1) Tested-by: Mike Lothian
Signed-off-by: Mario
On 10/28/2016 03:34 AM, Michel Dänzer wrote:
> On 27/10/16 10:33 PM, Mike Lothian wrote:
>>
>> Just another gentle ping to see where you are with this?
>
> I haven't got a chance to look into this any further.
>
>
Fwiw., as a proof of concept, the attached experimental patch does work
as
unt;
> unsigned int seq;
>
> - if (WARN_ON(pipe >= dev->num_crtcs))
> + if (WARN_ON(pipe >= dev->num_crtcs)) {
> + *vblanktime = (struct timeval) { 0 };
> return 0;
> + }
>
> do {
> seq = read_seqbegin(>seqlock);
>
Looks good to me.
Reviewed-by: Mario Kleiner
-mario
Hi Michel,
all your patches, both the already merged kernel bits in radeon/amdgpu
and also all the userspace bits in libdrm/ati-ddx/amdgpu-ddx are all
Reviewed-and-tested-by: Mario Kleiner
I successfully tested with old/current userspace and the new userspace
patches from your own libdrm/ati
ere in vblank. Therefore delay
the actual flip programming until after vblank on pre-AVIVO.
Signed-off-by: Mario Kleiner
---
drivers/gpu/drm/radeon/atombios_crtc.c | 4 ++--
drivers/gpu/drm/radeon/radeon_display.c | 17 ++---
drivers/gpu/drm/radeon/rv515.c | 3 ++-
3 fi
threshold.
This completion path is still prone to some races in corner
cases, especially on pre-AVIVO hardware, so document them
a bit better in the code comments.
Signed-off-by: Mario Kleiner
---
drivers/gpu/drm/radeon/radeon_display.c | 30 ++
1 file changed, 22
Hi,
testing on "simulated" pre-DCE4 radeon hw (via setting the module
parameter radeon.use_pflipirq=0 to avoid use of pflip irqs) showed
we need some adjustments on top of Michel's page_flip_target patches
on these old asics.
Patch 2/2:
Essentially disabling the ability to flip anywhere in
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