On 09/14/2012 05:23 AM, Michel Catudal wrote:
I have written code for a cluster with a Micronas (ARM7TDMI) and
AVR32UC3C 144 pins and found a major reduction in code size and code
is a lot faster.
Did you use the Thumb ISA for the ARM ? Same is said to be more compact
than ARM32. With a
I have made a preliminary backend and RTL stub in branches/laksen/avr32new/
Some of the large problems is that the load instructions allow non-aligned
loads in the ld.w forms. This proves to introduce many strange problems, and I
don't have any debug equipment.
Regards, Jeppe
Am 13.09.2012 21:38, schrieb Jeppe Græsdal Johansen:
I have made a preliminary backend and RTL stub in
branches/laksen/avr32new/
Some of the large problems is that the load instructions allow
non-aligned loads in the ld.w forms.
This proves to introduce many
strange problems,
Why is this
Le 13/09/2012 15:38, Jeppe Græsdal Johansen a écrit :
I have made a preliminary backend and RTL stub in branches/laksen/avr32new/
Some of the large problems is that the load instructions allow non-aligned
loads in the ld.w forms. This proves to introduce many strange problems, and I
don't
On Friday 14 September 2012 05:23:50 Michel Catudal wrote:
I bought JTAGICE mkII, it works nicely with Scientific Linux 6.2. The
binaries from Fedora 12 and 13 work with Scientifc Linux. I will have no
problem with debugging AVR32 code. What I find with AVR32 is that it makes
nice compact
