[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 Robin Dapp changed: What|Removed |Added Last reconfirmed|2024-07-24 00:00:00 | Known to fail|14.0

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 Robin Dapp changed: What|Removed |Added Status|UNCONFIRMED |NEW Last reconfirmed|

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #8 from Patrick O'Neill --- Bisected to r14-3840-g88a0a883960 but that isn't the offending patch. Can't find a baseline with --param=riscv-autovec-preference=scalable so I guess this isn't bisectable.

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #7 from Patrick O'Neill --- Retested using r15-2217-ga3f03891065. It's changed slightly but is still reproducible on my machine :-/ > /scratch/tc-testing/tc-compiler-fuzz-trunk/build-gcv/bin/riscv64-unknown-linux-gnu-gcc >

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #6 from Patrick O'Neill --- Binutils: #binutils-2_42 (c7f28aad0c99d1d2fec4e52ebfa3735d90ceb8e9) QEMU_CPU=rv64,vlen=128,v=true,vext_spec=v1.0,zve32f=true,zve64f=true

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #5 from Robin Dapp --- Weird, I tried your exact qemu version and still can't reproduce the problem. My results are always FFB5. Binutils difference? Very unlikely. Could you post your QEMU_CPU settings just to be sure?

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #4 from Patrick O'Neill --- Reran as requested in pr114668. Still present with that fix. I'll triage some other testcases and file those as well. Hopefully one of them is a duplicate to this one that is easily reproducible. GCC:

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #3 from Patrick O'Neill --- Created attachment 57922 --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=57922=edit Generated assembly files Hmm doesn't look like it from my side - maybe there's some stack related weirdness going

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #2 from Robin Dapp --- Checked with the latest commit on a different machine but still cannot reproduce the error. PR114668 I can reproduce. Maybe a copy and paste problem?

[Bug target/114665] [14] RISC-V rv64gcv: miscompile at -O3

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114665 --- Comment #1 from Robin Dapp --- Hmm, my local version is a bit older and seems to give the same result for both -O2 and -O3. At least a good starting point for bisection then.