[gcc r15-4240] RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr116883]

https://gcc.gnu.org/g:fd8e590ff11266598d8f9b3d03d72ba7a6100512 commit r15-4240-gfd8e590ff11266598d8f9b3d03d72ba7a6100512 Author: Li Xu Date: Thu Oct 10 08:51:19 2024 -0600 RISC-V:Bugfix for C++ code compilation failure with rv32imafc_zve32f[pr116883] From: xuli Example

[gcc r15-4224] RISC-V: Optimize branches with shifted immediate operands

https://gcc.gnu.org/g:c8957c8779954c3b0bade1dde0a8987b4db157b4 commit r15-4224-gc8957c8779954c3b0bade1dde0a8987b4db157b4 Author: Jovan Vukic Date: Wed Oct 9 16:53:38 2024 -0600 RISC-V: Optimize branches with shifted immediate operands After the valuable feedback I received, it’s c

[gcc r15-4223] Revert "RISC-V: Add implication for M extension."

https://gcc.gnu.org/g:df3bda457be49b29c09944a0d639ce9ec0b7d282 commit r15-4223-gdf3bda457be49b29c09944a0d639ce9ec0b7d282 Author: Jeff Law Date: Wed Oct 9 16:22:06 2024 -0600 Revert "RISC-V: Add implication for M extension." This reverts commit 0a193466f2e87acef9b86e0d086bc6f601751

[gcc r15-4222] Revert "RISC-V: Enable builtin __riscv_mul with Zmmul extension."

https://gcc.gnu.org/g:e889235cb004b62f3004408283ce91eb20eb521a commit r15-4222-ge889235cb004b62f3004408283ce91eb20eb521a Author: Jeff Law Date: Wed Oct 9 16:21:56 2024 -0600 Revert "RISC-V: Enable builtin __riscv_mul with Zmmul extension." This reverts commit 2990f5802a727cbd71758

[gcc r15-4189] tree-optimization/116024 - simplify some cases of X +- C1 cmp C2

https://gcc.gnu.org/g:52fdf1e7eb89a148a9cdd1daade524f4540ab5fa commit r15-4189-g52fdf1e7eb89a148a9cdd1daade524f4540ab5fa Author: Artemiy Volkov Date: Tue Oct 8 18:06:23 2024 -0600 tree-optimization/116024 - simplify some cases of X +- C1 cmp C2 Whenever C1 and C2 are integer const

[gcc r15-4188] tree-optimization/116024 - simplify C1-X cmp C2 for wrapping signed types

https://gcc.gnu.org/g:e5f5cffb8c8243896a9d3bd0e2b8f14c70f8df1e commit r15-4188-ge5f5cffb8c8243896a9d3bd0e2b8f14c70f8df1e Author: Artemiy Volkov Date: Tue Oct 8 18:04:13 2024 -0600 tree-optimization/116024 - simplify C1-X cmp C2 for wrapping signed types Implement a match.pd transf

[gcc r15-4187] tree-optimization/116024 - simplify C1-X cmp C2 for unsigned types

https://gcc.gnu.org/g:65b33d43d29b148e127b1ba997f1bbc2c7028b94 commit r15-4187-g65b33d43d29b148e127b1ba997f1bbc2c7028b94 Author: Artemiy Volkov Date: Tue Oct 8 17:54:55 2024 -0600 tree-optimization/116024 - simplify C1-X cmp C2 for unsigned types Implement a match.pd transformatio

[gcc r15-4186] tree-optimization/116024 - simplify C1-X cmp C2 for UB-on-overflow types

https://gcc.gnu.org/g:0883c88664d48463dfc79335dccaf15a69230952 commit r15-4186-g0883c88664d48463dfc79335dccaf15a69230952 Author: Artemiy Volkov Date: Tue Oct 8 17:51:08 2024 -0600 tree-optimization/116024 - simplify C1-X cmp C2 for UB-on-overflow types Implement a match.pd pattern

[gcc r15-4185] RISC-V: Enable builtin __riscv_mul with Zmmul extension.

https://gcc.gnu.org/g:2990f5802a727cbd717587c3a345fa940193049f commit r15-4185-g2990f5802a727cbd717587c3a345fa940193049f Author: Tsung Chun Lin Date: Tue Oct 8 17:44:38 2024 -0600 RISC-V: Enable builtin __riscv_mul with Zmmul extension. From d5b254e19d1f37fe27c7e98a0160e5c22446cfe

[gcc r15-4184] RISC-V: Add implication for M extension.

https://gcc.gnu.org/g:0a193466f2e87acef9b86e0d086bc6f6017518b0 commit r15-4184-g0a193466f2e87acef9b86e0d086bc6f6017518b0 Author: Tsung Chun Lin Date: Tue Oct 8 17:40:59 2024 -0600 RISC-V: Add implication for M extension. That M implies Zmmul. gcc/ChangeLog:

[gcc r15-4183] RISC-V: Implement TARGET_CAN_INLINE_P

https://gcc.gnu.org/g:517d344e416c762a942a3633b6ec73a1d018016e commit r15-4183-g517d344e416c762a942a3633b6ec73a1d018016e Author: Yangyu Chen Date: Tue Oct 8 11:08:44 2024 -0600 RISC-V: Implement TARGET_CAN_INLINE_P Currently, we lack support for TARGET_CAN_INLINE_P on the RISC-V

[gcc r15-4173] [RISC-V][PR target/116615] RISC-V: Use default LOGICAL_OP_NON_SHORT_CIRCUIT

https://gcc.gnu.org/g:34ae3a992a0cc3240d07d69ff12a664cbb5c8be0 commit r15-4173-g34ae3a992a0cc3240d07d69ff12a664cbb5c8be0 Author: Palmer Dabbelt Date: Tue Oct 8 07:28:32 2024 -0600 [RISC-V][PR target/116615] RISC-V: Use default LOGICAL_OP_NON_SHORT_CIRCUIT > We have cheap logical o

[gcc r15-4123] [RISC-V] Add splitters to restore condops generation after recent phiopt changes

https://gcc.gnu.org/g:a2a956cf26e645bfddbc0b743b97472e298c7a8c commit r15-4123-ga2a956cf26e645bfddbc0b743b97472e298c7a8c Author: Jeff Law Date: Mon Oct 7 11:49:21 2024 -0600 [RISC-V] Add splitters to restore condops generation after recent phiopt changes V2: Fix typo in Cha

[gcc r15-4071] [PATCH] RISC-V/libgcc: Fix incorrect .cfi_offset for saving ra in __riscv_save_[0-3] on ilp32e.

https://gcc.gnu.org/g:78d2af1fa53fe232ae00673f53c8b168d099c70f commit r15-4071-g78d2af1fa53fe232ae00673f53c8b168d099c70f Author: Tsung Chun Lin Date: Fri Oct 4 08:02:07 2024 -0600 [PATCH] RISC-V/libgcc: Fix incorrect .cfi_offset for saving ra in __riscv_save_[0-3] on ilp32e. From

[gcc r15-3994] [PATCH] RISC-V/libgcc: Fix incorrect and missing .cfi_offset for __riscv_save_[0-3] on RV32.

https://gcc.gnu.org/g:97fd777248f3c22f6baa5a25f25f7dd510ca5e63 commit r15-3994-g97fd777248f3c22f6baa5a25f25f7dd510ca5e63 Author: Tsung Chun Lin Date: Tue Oct 1 09:10:29 2024 -0600 [PATCH] RISC-V/libgcc: Fix incorrect and missing .cfi_offset for __riscv_save_[0-3] on RV32. 0001-RI

[gcc r15-3948] [PATCH] SH: Document extended asm operand modifers

https://gcc.gnu.org/g:01a42a07e52811164787d98cd463fe79c17fc911 commit r15-3948-g01a42a07e52811164787d98cd463fe79c17fc911 Author: Pietro Monteiro Date: Sun Sep 29 10:39:05 2024 -0600 [PATCH] SH: Document extended asm operand modifers From: Pietro Monteiro SH: Document ext

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Cleanup debug code for SAT_* testcases [NFC]

https://gcc.gnu.org/g:e58bd4fed07f7b095d3a8d1c442efbdd6f4901cd commit e58bd4fed07f7b095d3a8d1c442efbdd6f4901cd Author: Pan Li Date: Wed Sep 25 16:00:27 2024 +0800 RISC-V: Cleanup debug code for SAT_* testcases [NFC] Some print code for debugging is committed by mistake, remove the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v2] RISC-V: Improve code generation for select of consecutive constants

https://gcc.gnu.org/g:68251c8c320a33ea36c4b16f50e67d12fa404908 commit 68251c8c320a33ea36c4b16f50e67d12fa404908 Author: Jovan Vukic Date: Sun Sep 29 10:06:43 2024 -0600 [PATCH v2] RISC-V: Improve code generation for select of consecutive constants Based on the valuable feedback I

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Fix FIXED_REGISTERS comment missing return address register

https://gcc.gnu.org/g:672292e319c3f73ce2c26c019e59cfa0a65ea8ec commit 672292e319c3f73ce2c26c019e59cfa0a65ea8ec Author: Yixuan Chen Date: Tue Sep 24 09:15:00 2024 -0600 [PATCH] RISC-V: Fix FIXED_REGISTERS comment missing return address register gcc/ChangeLog: * con

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 2 of signed vector SAT_ADD

https://gcc.gnu.org/g:3694b042a64488bf30c00f1daa0373d4bcc852c2 commit 3694b042a64488bf30c00f1daa0373d4bcc852c2 Author: Pan Li Date: Fri Sep 20 16:09:56 2024 +0800 RISC-V: Add testcases for form 2 of signed vector SAT_ADD Form 2: #define DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression.

https://gcc.gnu.org/g:ab7ab5ce05edb5e6dcf21925651cd9ebc2142291 commit ab7ab5ce05edb5e6dcf21925651cd9ebc2142291 Author: Xianmiao Qu Date: Wed Sep 18 07:35:12 2024 -0600 [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression. I think it is a typo. When c

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V/libgcc: Save/Restore routines for E goes with ABI.

https://gcc.gnu.org/g:c4446c881e52eb82d5a806f76adce75e71b1032a commit c4446c881e52eb82d5a806f76adce75e71b1032a Author: Jim Lin Date: Fri Sep 27 14:44:12 2024 +0800 RISC-V/libgcc: Save/Restore routines for E goes with ABI. That Save/Restore routines for E can be used for RVI with I

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 3 of signed vector SAT_ADD

https://gcc.gnu.org/g:95e5c07ea48f3ff482141fe7b435321c97e533da commit 95e5c07ea48f3ff482141fe7b435321c97e533da Author: Pan Li Date: Sat Sep 21 12:51:58 2024 +0800 RISC-V: Add testcases for form 3 of signed vector SAT_ADD Form 3: #define DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MA

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the testcase of vector SAT_TRUNC

https://gcc.gnu.org/g:36b00f64d01622439f62501ea4f6c6c7c50f13e4 commit 36b00f64d01622439f62501ea4f6c6c7c50f13e4 Author: Pan Li Date: Wed Sep 25 14:37:46 2024 +0800 RISC-V: Refine the testcase of vector SAT_TRUNC Take scan-assembler-times for vnclip insn check instead of function bo

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the testcase of vector SAT_SUB

https://gcc.gnu.org/g:3980fecc0eae20a4993bcba9afb455cdd58346cd commit 3980fecc0eae20a4993bcba9afb455cdd58346cd Author: Pan Li Date: Wed Sep 25 13:55:22 2024 +0800 RISC-V: Refine the testcase of vector SAT_SUB Take scan-assembler-times for vssub insn check instead of function body,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refine the testcase of vector SAT_ADD

https://gcc.gnu.org/g:52055ad7be1372f849f7ce04be91e3791591e1e8 commit 52055ad7be1372f849f7ce04be91e3791591e1e8 Author: Pan Li Date: Wed Sep 25 11:41:22 2024 +0800 RISC-V: Refine the testcase of vector SAT_ADD Take scan-assembler-times for vsadd insn check instead of function body,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: testsuite: Fix SELECT_VL SLP fallout.

https://gcc.gnu.org/g:931ef37a209ca3b6fd5dd7158d207df64adffddb commit 931ef37a209ca3b6fd5dd7158d207df64adffddb Author: Robin Dapp Date: Thu Sep 19 05:08:47 2024 -0700 RISC-V: testsuite: Fix SELECT_VL SLP fallout. This fixes asm-scan fallout from r15-3712-g5e3a4a01785e2d where we a

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add more vector-vector extract cases.

https://gcc.gnu.org/g:62ce984524ec7da729c3ea2c044a2fcc5403 commit 62ce984524ec7da729c3ea2c044a2fcc5403 Author: Robin Dapp Date: Tue Sep 3 17:53:34 2024 +0200 RISC-V: Add more vector-vector extract cases. This adds a V16SI -> V4SI and related i.e. "quartering" vector-vector

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix effective target check.

https://gcc.gnu.org/g:c9e63024a36590e2b84f446d0a0c27c95a9d4d56 commit c9e63024a36590e2b84f446d0a0c27c95a9d4d56 Author: Robin Dapp Date: Fri Aug 30 14:35:08 2024 +0200 RISC-V: Fix effective target check. The return value is inverted in check_effective_target_rvv_zvl256b_ok and

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

https://gcc.gnu.org/g:91be221f94c98df38bea08c27695e18da357c9f0 commit 91be221f94c98df38bea08c27695e18da357c9f0 Author: Bohan Lei Date: Wed Sep 18 07:20:23 2024 -0600 [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx The RISC-V vector machine description relies on the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.

https://gcc.gnu.org/g:81f5fff4ec670624603f1f687935d33f551abf25 commit 81f5fff4ec670624603f1f687935d33f551abf25 Author: Xianmiao Qu Date: Wed Sep 18 07:28:44 2024 -0600 [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32. The Combine Pass may generate zero_extract instruct

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 4 of signed scalar SAT_ADD

https://gcc.gnu.org/g:40a62c2f831051f7b7dd4c56c1056591ec2926bd commit 40a62c2f831051f7b7dd4c56c1056591ec2926bd Author: Pan Li Date: Fri Sep 20 10:15:37 2024 +0800 RISC-V: Add testcases for form 4 of signed scalar SAT_ADD Form 4: #define DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Implement SAT_ADD for signed integer vector

https://gcc.gnu.org/g:e284213dc880f678994a36b8f24f22d8c2444588 commit e284213dc880f678994a36b8f24f22d8c2444588 Author: Pan Li Date: Thu Sep 12 10:43:46 2024 +0800 RISC-V: Implement SAT_ADD for signed integer vector This patch would like to implement the ssadd for vector integer.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 3 of signed scalar SAT_ADD

https://gcc.gnu.org/g:7ec1234888e05ddb4a36877d2257ff6bf388c56d commit 7ec1234888e05ddb4a36877d2257ff6bf388c56d Author: Pan Li Date: Fri Sep 20 10:01:40 2024 +0800 RISC-V: Add testcases for form 3 of signed scalar SAT_ADD This patch would like to add testcases of the signed scalar

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 2 of signed scalar SAT_ADD

https://gcc.gnu.org/g:ab870d37a7d392d56872b7b56b58534495d16447 commit ab870d37a7d392d56872b7b56b58534495d16447 Author: Pan Li Date: Fri Sep 13 10:05:49 2024 +0800 RISC-V: Add testcases for form 2 of signed scalar SAT_ADD This patch would like to add testcases of the signed scalar

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vector SAT_ADD dump check due to middle-end change

https://gcc.gnu.org/g:a934530a3f78989461de6e0e4dd30d7ea90664ee commit a934530a3f78989461de6e0e4dd30d7ea90664ee Author: Pan Li Date: Wed Sep 11 14:17:30 2024 +0800 RISC-V: Fix vector SAT_ADD dump check due to middle-end change This patch would like fix the dump check times of vecto

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix signed SAT_ADD test case for int64_t

https://gcc.gnu.org/g:1e9292c84d6689c5dab618669dd050f5e1945f07 commit 1e9292c84d6689c5dab618669dd050f5e1945f07 Author: Pan Li Date: Fri Sep 13 09:16:48 2024 +0800 RISC-V: Fix signed SAT_ADD test case for int64_t The int8_t test for signed SAT_ADD is sat_s_add-1.c, the sat_s_add-4.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on

https://gcc.gnu.org/g:11234fb5acfc524f6c4e0095a568faec75480332 commit 11234fb5acfc524f6c4e0095a568faec75480332 Author: Jin Ma Date: Wed Sep 18 08:56:23 2024 -0600 [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32. gcc/ChangeL

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Eliminate latter vsetvl when fused

https://gcc.gnu.org/g:31b29d5c7d142bca046ebd16cb18867d2d2f6d43 commit 31b29d5c7d142bca046ebd16cb18867d2d2f6d43 Author: Bohan Lei Date: Thu Sep 12 10:28:03 2024 +0800 RISC-V: Eliminate latter vsetvl when fused Hi all, A simple assembly check has been added in this version.

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] riscv: Fix duplicate assmbler label in @tlsdesc insn

https://gcc.gnu.org/g:8d6d5ffef9e0718948a4273defca990cf616e915 commit 8d6d5ffef9e0718948a4273defca990cf616e915 Author: Andreas Schwab Date: Thu Sep 12 13:55:09 2024 +0200 riscv: Fix duplicate assmbler label in @tlsdesc insn Use %= instead of maintaining a sequence number manually,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix asm check for Vector SAT_* due to middle-end change

https://gcc.gnu.org/g:4f8885fd58ea8de22735b545205285c242b35c9f commit 4f8885fd58ea8de22735b545205285c242b35c9f Author: Pan Li Date: Wed Sep 11 07:00:13 2024 +0800 RISC-V: Fix asm check for Vector SAT_* due to middle-end change The middle-end change makes the effect on the layout o

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass

https://gcc.gnu.org/g:7a987a1f5d78e5bb5b8bf2f16421a033a2a012cb commit 7a987a1f5d78e5bb5b8bf2f16421a033a2a012cb Author: garthlei Date: Wed Sep 11 17:09:37 2024 +0800 RISC-V: Fix vl_used_by_non_rvv_insn logic of vsetvl pass This patch fixes a bug in the current vsetvl pass. The cur

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector

https://gcc.gnu.org/g:ef057b44071884b86979d82a469d7eac2ec442a1 commit ef057b44071884b86979d82a469d7eac2ec442a1 Author: Jin Ma Date: Sat Sep 7 10:29:02 2024 -0600 [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for XTheadVector Since the THeadVec

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler model

https://gcc.gnu.org/g:977f633aa659530748befad2dbba8bd3b5f68258 commit 977f633aa659530748befad2dbba8bd3b5f68258 Author: Zhao Dingyi Date: Sat Sep 7 10:48:46 2024 -0600 [PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler model This patch aims to add the missing inst

[gcc r15-3947] [PATCH] [PATCH] Avoid integer overflow in gcc.dg/cpp/charconst-3.c (PR testsuite/116806)

https://gcc.gnu.org/g:0cd24b06d130d99bd86e5e03a01c38047413a92e commit r15-3947-g0cd24b06d130d99bd86e5e03a01c38047413a92e Author: Mikael Pettersson Date: Sun Sep 29 10:15:55 2024 -0600 [PATCH] [PATCH] Avoid integer overflow in gcc.dg/cpp/charconst-3.c (PR testsuite/116806) The int

[gcc r15-3946] [PATCH v2] RISC-V: Improve code generation for select of consecutive constants

https://gcc.gnu.org/g:a0f1f504b2c49a3695b91d3323d2e2419ef970db commit r15-3946-ga0f1f504b2c49a3695b91d3323d2e2419ef970db Author: Jovan Vukic Date: Sun Sep 29 10:06:43 2024 -0600 [PATCH v2] RISC-V: Improve code generation for select of consecutive constants Based on the valuable f

[gcc r15-3835] [PATCH] RISC-V: Fix FIXED_REGISTERS comment missing return address register

https://gcc.gnu.org/g:79a3d3da8c8a5ad56547b7f7991577271ee5d1b2 commit r15-3835-g79a3d3da8c8a5ad56547b7f7991577271ee5d1b2 Author: Yixuan Chen Date: Tue Sep 24 09:15:00 2024 -0600 [PATCH] RISC-V: Fix FIXED_REGISTERS comment missing return address register gcc/ChangeLog:

[gcc r15-3695] [PATCH] configure: fix typos

https://gcc.gnu.org/g:cc62b2c3da118f08f71d2ae9c08bafb55b35767a commit r15-3695-gcc62b2c3da118f08f71d2ae9c08bafb55b35767a Author: Andrew Kreimer Date: Wed Sep 18 11:50:58 2024 -0600 [PATCH] configure: fix typos / * configure.ac: Fix typos. * configure: Rebui

[gcc r15-3691] [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on

https://gcc.gnu.org/g:85fcf740342e308da4776a45a4cd726987725a6a commit r15-3691-g85fcf740342e308da4776a45a4cd726987725a6a Author: Jin Ma Date: Wed Sep 18 08:56:23 2024 -0600 [PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32. g

[gcc r15-3688] [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression.

https://gcc.gnu.org/g:ad5bfc2b7044ba962396de0dabcad1cd54234689 commit r15-3688-gad5bfc2b7044ba962396de0dabcad1cd54234689 Author: Xianmiao Qu Date: Wed Sep 18 07:35:12 2024 -0600 [PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expression. I think it is a ty

[gcc r15-3687] [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.

https://gcc.gnu.org/g:ec34a4481b63bb5028b2a8c61322a7a3d362b27c commit r15-3687-gec34a4481b63bb5028b2a8c61322a7a3d362b27c Author: Xianmiao Qu Date: Wed Sep 18 07:28:44 2024 -0600 [PATCH] RISC-V: Fix th.extu operands exceeding range on rv32. The Combine Pass may generate zero_extrac

[gcc r15-3686] [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

https://gcc.gnu.org/g:0756f335fb6e455641850a76e68f892f1f82ada2 commit r15-3686-g0756f335fb6e455641850a76e68f892f1f82ada2 Author: Bohan Lei Date: Wed Sep 18 07:20:23 2024 -0600 [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx The RISC-V vector machine description rel

[gcc r15-3528] [PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler model

https://gcc.gnu.org/g:6749c69ae143ed808e0d0aa9097f0c9b7c6a785d commit r15-3528-g6749c69ae143ed808e0d0aa9097f0c9b7c6a785d Author: Zhao Dingyi Date: Sat Sep 7 10:48:46 2024 -0600 [PATCH] RISC-V: Add missing insn types for XiangShan Nanhu scheduler model This patch aims to add the mi

[gcc r15-3527] [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector

https://gcc.gnu.org/g:d620499b3a24f14cfb98529640584e63d7eca149 commit r15-3527-gd620499b3a24f14cfb98529640584e63d7eca149 Author: Jin Ma Date: Sat Sep 7 10:29:02 2024 -0600 [PATCH v4] [target/116592] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for XTheadVector Since th

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 2/2 v2] RISC-V: Constant synthesis of inverted halves

https://gcc.gnu.org/g:43677eed7d22953c677bcfc905acb830e6d33be6 commit 43677eed7d22953c677bcfc905acb830e6d33be6 Author: Raphael Moreira Zinsly Date: Thu Sep 5 22:14:32 2024 -0600 [PATCH 2/2 v2] RISC-V: Constant synthesis of inverted halves Changes since v1: - Fix synthe

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 1/2 v2] RISC-V: Additional large constant synthesis improvements

https://gcc.gnu.org/g:c9993e022343a20b9293d2852aa50ab7d90b1c06 commit c9993e022343a20b9293d2852aa50ab7d90b1c06 Author: Raphael Moreira Zinsly Date: Thu Sep 5 21:50:54 2024 -0600 [PATCH 1/2 v2] RISC-V: Additional large constant synthesis improvements Changes since v1: -

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Partial -- just the testsuite changes.

https://gcc.gnu.org/g:00d5bc4c546e9f256a8980de53265033fcac4bbb commit 00d5bc4c546e9f256a8980de53265033fcac4bbb Author: Pan Li Date: Mon Sep 2 11:33:08 2024 +0800 Partial -- just the testsuite changes. Match: Add int type fits check for form 2 of .SAT_SUB imm operand This

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Partial -- just the testsuite changes.

https://gcc.gnu.org/g:15880b511b5e04c9e47f07012fe95b43ffc6ae9b commit 15880b511b5e04c9e47f07012fe95b43ffc6ae9b Author: Pan Li Date: Mon Sep 2 09:48:46 2024 +0800 Partial -- just the testsuite changes. Match: Add int type fits check for form 1 of .SAT_SUB imm operand This

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix out of index in riscv_select_multilib_by_abi

https://gcc.gnu.org/g:36acd0cc9bbbab875238a7d186577f19964d471f commit 36acd0cc9bbbab875238a7d186577f19964d471f Author: YunQiang Su Date: Thu Sep 5 19:55:20 2024 +0800 RISC-V: Fix out of index in riscv_select_multilib_by_abi commit b5c2aae48723c9098a8a3dab1409b30fd87bbf56 Autho

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [V2][RISC-V] Avoid unnecessary extensions after sCC insns

https://gcc.gnu.org/g:2cc7dc042140083dee3a9459fd79e1eb0b4c1a71 commit 2cc7dc042140083dee3a9459fd79e1eb0b4c1a71 Author: Jeff Law Date: Thu Sep 5 15:45:25 2024 -0600 [V2][RISC-V] Avoid unnecessary extensions after sCC insns So the first patch failed the pre-commit CI; it didn't fail

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Lookup reversely in riscv_select_multilib_by_abi

https://gcc.gnu.org/g:e3dcc815e3d72d6e63503e6c72a70576c5108a6a commit e3dcc815e3d72d6e63503e6c72a70576c5108a6a Author: YunQiang Su Date: Thu Sep 5 15:14:43 2024 +0800 RISC-V: Lookup reversely in riscv_select_multilib_by_abi When use --print-multi-os-dir or -print-multi-directory,

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

https://gcc.gnu.org/g:ba4e0f2174b7b807e37255f5b6e5f2572338afc5 commit ba4e0f2174b7b807e37255f5b6e5f2572338afc5 Author: Palmer Dabbelt Date: Wed Sep 4 21:34:31 2024 -0600 [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection These tests were checking that the out

[gcc r15-3505] [PATCH 2/2 v2] RISC-V: Constant synthesis of inverted halves

https://gcc.gnu.org/g:1dd175a0ccdd0ff4e7cb6668164a4fe99e47015d commit r15-3505-g1dd175a0ccdd0ff4e7cb6668164a4fe99e47015d Author: Raphael Moreira Zinsly Date: Thu Sep 5 22:14:32 2024 -0600 [PATCH 2/2 v2] RISC-V: Constant synthesis of inverted halves Changes since v1: -

[gcc r15-3504] [PATCH 1/2 v2] RISC-V: Additional large constant synthesis improvements

https://gcc.gnu.org/g:ecdb9f59d0915f154a4c8fa56e11d81479f535eb commit r15-3504-gecdb9f59d0915f154a4c8fa56e11d81479f535eb Author: Raphael Moreira Zinsly Date: Thu Sep 5 21:50:54 2024 -0600 [PATCH 1/2 v2] RISC-V: Additional large constant synthesis improvements Changes since v1:

[gcc r15-3496] [V2][RISC-V] Avoid unnecessary extensions after sCC insns

https://gcc.gnu.org/g:b567e5ead5d54f022c57b48f31653f6ae6ece007 commit r15-3496-gb567e5ead5d54f022c57b48f31653f6ae6ece007 Author: Jeff Law Date: Thu Sep 5 15:45:25 2024 -0600 [V2][RISC-V] Avoid unnecessary extensions after sCC insns So the first patch failed the pre-commit CI; it d

[gcc r15-3465] [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection

https://gcc.gnu.org/g:de3ca363811a3974e4398ecdb1db2274efd61a1c commit r15-3465-gde3ca363811a3974e4398ecdb1db2274efd61a1c Author: Palmer Dabbelt Date: Wed Sep 4 21:34:31 2024 -0600 [PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection These tests were checking th

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Just the testsuite changes...

https://gcc.gnu.org/g:5c27d6ce4cc63259d12e77eeda671adbc0d11530 commit 5c27d6ce4cc63259d12e77eeda671adbc0d11530 Author: Pan Li Date: Sat Aug 24 10:16:28 2024 +0800 Just the testsuite changes... Match: Add int type fits check for .SAT_ADD imm operand This patch would like t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Fix sign/carry bit handling in ext-dce.

https://gcc.gnu.org/g:8754b967c81742fa33f65a75ed87834feeff95b9 commit 8754b967c81742fa33f65a75ed87834feeff95b9 Author: Jeff Law Date: Mon Jul 15 16:57:44 2024 -0600 Fix sign/carry bit handling in ext-dce. My change to fix a ubsan issue broke handling propagation of the carry/sign

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants

https://gcc.gnu.org/g:2d69f0e3a2e86b3d637cf2440d12ced120db31b7 commit 2d69f0e3a2e86b3d637cf2440d12ced120db31b7 Author: Raphael Moreira Zinsly Date: Wed Sep 4 17:21:24 2024 -0600 [PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants Improve handling of constant

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [RISC-V] Fix scan test output after recent path-splitting changes

https://gcc.gnu.org/g:80ad2d7bf8d40f8fb384855b06b8c97ed5371015 commit 80ad2d7bf8d40f8fb384855b06b8c97ed5371015 Author: Jeff Law Date: Wed Sep 4 12:07:09 2024 -0600 [RISC-V] Fix scan test output after recent path-splitting changes The recent path splitting changes from Andrew resul

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD

https://gcc.gnu.org/g:b856428ef3b05b8fd69b439ade1b0cb1bb6e185e commit b856428ef3b05b8fd69b439ade1b0cb1bb6e185e Author: Pan Li Date: Mon Sep 2 15:54:43 2024 +0800 RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD This patch would like to allow the IMM operand of the unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Drop file that should not have been committed.

https://gcc.gnu.org/g:98d6e0eefeaa53d6482ca1968d95a22455996af3 commit 98d6e0eefeaa53d6482ca1968d95a22455996af3 Author: Jeff Law Date: Tue Sep 3 09:30:35 2024 -0600 Drop file that should not have been committed. * J: Drop file that should not have been committed (c

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PR target/115921] Improve reassociation for rv64

https://gcc.gnu.org/g:0ff3a68e122baeafff5d58bad57ad0052dede067 commit 0ff3a68e122baeafff5d58bad57ad0052dede067 Author: Jeff Law Date: Tue Sep 3 06:45:30 2024 -0600 [PR target/115921] Improve reassociation for rv64 As Jovan pointed out in pr115921, we're not reassociating expressio

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Support form 1 of integer scalar .SAT_ADD

https://gcc.gnu.org/g:cb75d2d9eca78adc5a95884bdd19907c330ab5aa commit cb75d2d9eca78adc5a95884bdd19907c330ab5aa Author: Pan Li Date: Thu Aug 29 11:25:44 2024 +0800 RISC-V: Support form 1 of integer scalar .SAT_ADD This patch would like to support the scalar signed ssadd pattern

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.

https://gcc.gnu.org/g:82d58b78291d4108435da4411e8ebfa840ee4dc9 commit 82d58b78291d4108435da4411e8ebfa840ee4dc9 Author: Xianmiao Qu Date: Sun Sep 1 22:28:13 2024 -0600 [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32. Currently, in RV32, even with the D extens

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3

https://gcc.gnu.org/g:d4f551d4316a38ea8ad9a1fe740dca5d4cbbd77c commit d4f551d4316a38ea8ad9a1fe740dca5d4cbbd77c Author: Pan Li Date: Sun Aug 18 14:08:21 2024 +0800 RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3 This patch would like to add test cases for t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] [committed][PR rtl-optimization/116544] Fix test for promoted subregs

https://gcc.gnu.org/g:f35d49f0eb8ffc614cf233ad05b2fe86791c6719 commit f35d49f0eb8ffc614cf233ad05b2fe86791c6719 Author: Jeff Law Date: Sun Sep 1 22:16:04 2024 -0600 [committed][PR rtl-optimization/116544] Fix test for promoted subregs This is a small bug in the ext-dce code's handl

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2

https://gcc.gnu.org/g:94f4b718c181c9fe1f27a53c8babd38fa46c1640 commit 94f4b718c181c9fe1f27a53c8babd38fa46c1640 Author: Pan Li Date: Sun Aug 18 12:49:47 2024 +0800 RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2 This patch would like to add test cases for t

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Fix subreg of VLS modes larger than a vector [PR116086].

https://gcc.gnu.org/g:edba00e457e7677ffe66292090d60f8d50d70ee7 commit edba00e457e7677ffe66292090d60f8d50d70ee7 Author: Robin Dapp Date: Tue Aug 27 10:25:34 2024 +0200 RISC-V: Fix subreg of VLS modes larger than a vector [PR116086]. When the source mode is potentially larger than o

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM

https://gcc.gnu.org/g:b2887fd8a312b02e23d5e6ae0191f517e4c421a3 commit b2887fd8a312b02e23d5e6ae0191f517e4c421a3 Author: Pan Li Date: Fri Aug 30 11:01:37 2024 +0800 RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM This patch would like to add test cases for the unsig

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM

https://gcc.gnu.org/g:246b7bd9a16863ac8abb5fb55240eefbf1026006 commit 246b7bd9a16863ac8abb5fb55240eefbf1026006 Author: Pan Li Date: Fri Aug 30 08:36:45 2024 +0800 RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM This patch would like to add test cases for the unsig

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64

https://gcc.gnu.org/g:ef3f7e6aa699380b9925dabe7a1052a965622726 commit ef3f7e6aa699380b9925dabe7a1052a965622726 Author: Pan Li Date: Fri Aug 30 14:07:12 2024 +0800 RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64 In previous, we have some specially handling

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Test: Move pr116278 run test to dg/torture [NFC]

https://gcc.gnu.org/g:e9a4727900785a5a0a5fd0bf0df999ee69e3d6c9 commit e9a4727900785a5a0a5fd0bf0df999ee69e3d6c9 Author: Pan Li Date: Mon Aug 19 10:02:46 2024 +0800 Test: Move pr116278 run test to dg/torture [NFC] Move the run test of pr116278 to dg/torture and leave the risc-v the

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Partial: Just the testsuite bits.

https://gcc.gnu.org/g:a4b71f89a6e6090d775ab34e7ce365e8d8e8 commit a4b71f89a6e6090d775ab34e7ce365e8d8e8 Author: Pan Li Date: Tue Aug 27 15:01:02 2024 +0800 Partial: Just the testsuite bits. Vect: Reconcile the const_int operand type of unsigned .SAT_ADD The .SAT_AD

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add missing mode_idx for vrol and vror

https://gcc.gnu.org/g:1e62adc9cd6aa61948b106b1476fdf86eee7f3e0 commit 1e62adc9cd6aa61948b106b1476fdf86eee7f3e0 Author: Kito Cheng Date: Tue Aug 27 21:27:02 2024 +0800 RISC-V: Add missing mode_idx for vrol and vror We add pattern for vector rotate, but seems like we forgot adding

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4

https://gcc.gnu.org/g:51aee40c9d5d97b45d7d96781e1f43c9100702f6 commit 51aee40c9d5d97b45d7d96781e1f43c9100702f6 Author: Pan Li Date: Tue Aug 27 15:14:40 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4 This patch would like to add test cases for the unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3

https://gcc.gnu.org/g:019b3585afb077022b1463dd7e786bec472ada31 commit 019b3585afb077022b1463dd7e786bec472ada31 Author: Pan Li Date: Tue Aug 27 14:37:01 2024 +0800 RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3 This patch would like to add test cases for the unsigned

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] Fix mixed input kind permute optimization

https://gcc.gnu.org/g:ad83da212ba5a5e27484fe7a147a28294fab8829 commit ad83da212ba5a5e27484fe7a147a28294fab8829 Author: Richard Biener Date: Tue May 21 19:15:33 2024 +0200 Fix mixed input kind permute optimization When change_vec_perm_layout runs into a permute combining two no

[gcc r15-3459] [PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants

https://gcc.gnu.org/g:cbea72b265e4c9d1a595bd3ecd11b325021925d0 commit r15-3459-gcbea72b265e4c9d1a595bd3ecd11b325021925d0 Author: Raphael Moreira Zinsly Date: Wed Sep 4 17:21:24 2024 -0600 [PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants Improve handling o

[gcc r15-3457] [RISC-V] Fix scan test output after recent path-splitting changes

https://gcc.gnu.org/g:0455e85e4eda7d80bda967914d634fe5b71b7ffc commit r15-3457-g0455e85e4eda7d80bda967914d634fe5b71b7ffc Author: Jeff Law Date: Wed Sep 4 12:07:09 2024 -0600 [RISC-V] Fix scan test output after recent path-splitting changes The recent path splitting changes from An

[gcc r15-3426] Drop file that should not have been committed.

https://gcc.gnu.org/g:36f63000c6f869f4f5550780d77b381b1a8b1700 commit r15-3426-g36f63000c6f869f4f5550780d77b381b1a8b1700 Author: Jeff Law Date: Tue Sep 3 09:30:35 2024 -0600 Drop file that should not have been committed. * J: Drop file that should not have been committed

[gcc r15-3415] [PR target/115921] Improve reassociation for rv64

https://gcc.gnu.org/g:4371f656288f461335c47e98b8c038937a89764a commit r15-3415-g4371f656288f461335c47e98b8c038937a89764a Author: Jeff Law Date: Tue Sep 3 06:45:30 2024 -0600 [PR target/115921] Improve reassociation for rv64 As Jovan pointed out in pr115921, we're not reassociating

[gcc r13-9001] RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls

https://gcc.gnu.org/g:f364a431d5b44ebde2c20ebe5fff22291c7d12db commit r13-9001-gf364a431d5b44ebde2c20ebe5fff22291c7d12db Author: Vineet Gupta Date: Wed Nov 1 14:46:33 2023 -0700 RISC-V: fix TARGET_PROMOTE_FUNCTION_MODE hook for libcalls Fixes: 3496ca4e6566 ("RISC-V: Add runtime in

[gcc r15-3361] [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.

https://gcc.gnu.org/g:eca320bfe340beec9267bdb6021c7b387111 commit r15-3361-geca320bfe340beec9267bdb6021c7b387111 Author: Xianmiao Qu Date: Sun Sep 1 22:28:13 2024 -0600 [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32. Currently, in RV32, even with th

[gcc r15-3360] [committed][PR rtl-optimization/116544] Fix test for promoted subregs

https://gcc.gnu.org/g:0562976d62e095f3a00c799288dee4e5b20114e2 commit r15-3360-g0562976d62e095f3a00c799288dee4e5b20114e2 Author: Jeff Law Date: Sun Sep 1 22:16:04 2024 -0600 [committed][PR rtl-optimization/116544] Fix test for promoted subregs This is a small bug in the ext-dce co

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Allow non-duplicate bool patterns in expand_const_vector

https://gcc.gnu.org/g:a27d2ba5f655608dee585b6500bbdda17f488e91 commit a27d2ba5f655608dee585b6500bbdda17f488e91 Author: Patrick O'Neill Date: Tue Aug 20 12:50:51 2024 -0700 RISC-V: Allow non-duplicate bool patterns in expand_const_vector Currently we assert when encountering a non-

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander

https://gcc.gnu.org/g:f815c8f308c29271702255ec5690b77896ce71f3 commit f815c8f308c29271702255ec5690b77896ce71f3 Author: Patrick O'Neill Date: Tue Aug 20 12:01:22 2024 -0700 RISC-V: Handle 0.0 floating point pattern costing to match const_vector expander The comment previously here

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Handle case when constant vector construction target rtx is not a register

https://gcc.gnu.org/g:d812473dad74924f641325e3548333d93fa65b41 commit d812473dad74924f641325e3548333d93fa65b41 Author: Patrick O'Neill Date: Tue Aug 20 11:29:12 2024 -0700 RISC-V: Handle case when constant vector construction target rtx is not a register This manifests in RTL tha

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Emit costs for bool and stepped const vectors

https://gcc.gnu.org/g:1c7dfc57c1363ea7e387527a5919642308001b2f commit 1c7dfc57c1363ea7e387527a5919642308001b2f Author: Patrick O'Neill Date: Tue Aug 20 11:51:50 2024 -0700 RISC-V: Emit costs for bool and stepped const vectors These cases are handled in the expander (riscv-v.cc

[gcc(refs/vendors/riscv/heads/gcc-14-with-riscv-opts)] RISC-V: Reorder insn cost match order to match corresponding expander match order

https://gcc.gnu.org/g:77bdff2732045dfd049cb8ab91c948514f444fcb commit 77bdff2732045dfd049cb8ab91c948514f444fcb Author: Patrick O'Neill Date: Tue Aug 20 11:38:20 2024 -0700 RISC-V: Reorder insn cost match order to match corresponding expander match order The corresponding expander

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