[PATCH v6 02/10] x86: Avoid stack realignment when copying data

To avoid stack realignment, use SCRATCH_SSE_REG to copy data from one memory location to another. gcc/ * config/i386/i386-expand.c (ix86_expand_vector_move): Call ix86_gen_scratch_sse_rtx to get a scratch SSE register to copy data from one memory location to another. gcc/

[PATCH v6 04/10] x86: Add AVX2 tests for PR middle-end/90773

PR middle-end/90773 * gcc.target/i386/pr90773-20.c: New test. * gcc.target/i386/pr90773-21.c: Likewise. * gcc.target/i386/pr90773-22.c: Likewise. * gcc.target/i386/pr90773-23.c: Likewise. * gcc.target/i386/pr90773-26.c: Likewise. --- gcc/testsuite/gc

[PATCH v6 01/10] x86: Add TARGET_GEN_MEMSET_SCRATCH_RTX

Define TARGET_GEN_MEMSET_SCRATCH_RTX to ix86_gen_scratch_sse_rtx to return a scratch SSE register for memset. gcc/ PR middle-end/90773 * config/i386/i386.c (TARGET_GEN_MEMSET_SCRATCH_RTX): New. gcc/testsuite/ PR middle-end/90773 * gcc.target/i386/pr90773-5.c: Upd

[PATCH v5 00/10] Allow TImode/OImode/XImode in op_by_pieces operations

Changes in the v6 patches: 1. No need to add TARGET_GEN_MEMSET_SCRATCH_RTX nor change the memset expanders since they have been checked into master branch. Changes in the v5 patches: 1. Add TARGET_GEN_MEMSET_SCRATCH_RTX to allow the backend to use a hard scratch register to avoid stack realignme

[PATCH v6 07/10] x86: Also pass -mno-avx to cold-attribute-1.c

Also pass -mno-avx to pr72839.c to avoid copying data with YMM or ZMM registers. * gcc.target/i386/cold-attribute-1.c: Also pass -mno-avx. --- gcc/testsuite/gcc.target/i386/cold-attribute-1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/i386

[PATCH v6 06/10] x86: Also pass -mno-avx to pr72839.c

Also pass -mno-avx to pr72839.c to avoid copying data with YMM or ZMM registers. * gcc.target/i386/pr72839.c: Also pass -mno-avx. --- gcc/testsuite/gcc.target/i386/pr72839.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/i386/pr72839.c b/gcc/

[PATCH v6 03/10] x86: Update piecewise move and store

We can use TImode/OImode/XImode integers for piecewise move and store. 1. Define MAX_MOVE_MAX to 64, which is the constant maximum number of bytes that a single instruction can move quickly between memory and registers or between two memory locations. 2. Define MOVE_MAX to MOVE_MAX_PIECES, which i

[PATCH v6 08/10] x86: Also pass -mno-avx to sw-1.c for ia32

Also pass -mno-avx to sw-1.c for ia32 since copying data with YMM or ZMM registers disables shrink-wrapping when the second argument is passed on stack. * gcc.target/i386/sw-1.c: Also pass -mno-avx for ia32. --- gcc/testsuite/gcc.target/i386/sw-1.c | 1 + 1 file changed, 1 insertion(+) d

[PATCH v6 10/10] x86: Also pass -mno-sse to vect8-ret.c

Also pass -mno-sse to vect8-ret.c to disable XMM load/store when running GCC tests with "-march=x86-64 -m32". * gcc.target/i386/vect8-ret.c: Also pass -mno-sse. --- gcc/testsuite/gcc.target/i386/vect8-ret.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/

[PATCH v6 09/10] x86: Update gcc.target/i386/incoming-11.c

Expect no stack realignment since we no longer realign stack when copying data. * gcc.target/i386/incoming-11.c: Expect no stack realignment. --- gcc/testsuite/gcc.target/i386/incoming-11.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/i386/i

[PATCH v6 05/10] x86: Add tests for piecewise move and store

* gcc.target/i386/pieces-memcpy-10.c: New test. * gcc.target/i386/pieces-memcpy-11.c: Likewise. * gcc.target/i386/pieces-memcpy-12.c: Likewise. * gcc.target/i386/pieces-memcpy-13.c: Likewise. * gcc.target/i386/pieces-memcpy-14.c: Likewise. * gcc.targe

PING^1 [PATCH v5] : Add pragma GCC target("general-regs-only")

On Sat, Jul 17, 2021 at 6:45 PM H.J. Lu wrote: > > On Thu, Apr 22, 2021 at 7:30 AM Richard Biener via Gcc-patches > wrote: > > > > On Thu, Apr 22, 2021 at 2:52 PM Richard Biener > > wrote: > > > > > > On Thu, Apr 22, 2021 at 2:22 PM Jakub Jelinek wrote: > > > > > > > > On Thu, Apr 22, 2021 at 0

Re: [PATCH] i386: Improve extensions of __builtin_clz and constant - __builtin_clz for -mno-lzcnt [PR78103]

On Fri, Jul 30, 2021 at 6:27 AM Jakub Jelinek via Gcc-patches wrote: > > On Fri, Jul 30, 2021 at 12:27:39PM +0200, Uros Bizjak wrote: > > Please put some space here, e.g.: > ... > > Can you just name the relevant insn pattern and use > > > > emit_insn (gen_bsr_1)? > > Here is the updated patch. I

Re: [PATCH] i386: Improve extensions of __builtin_clz and constant - __builtin_clz for -mno-lzcnt [PR78103]

On Sat, Jul 31, 2021 at 12:38 PM H.J. Lu wrote: > > On Fri, Jul 30, 2021 at 6:27 AM Jakub Jelinek via Gcc-patches > wrote: > > > > On Fri, Jul 30, 2021 at 12:27:39PM +0200, Uros Bizjak wrote: > > > Please put some space here, e.g.: > > ... > > > Can you just name the relevant insn pattern and use

Re: [PATCH] i386: Improve extensions of __builtin_clz and constant - __builtin_clz for -mno-lzcnt [PR78103]

On Fri, Jul 30, 2021 at 6:27 AM Jakub Jelinek via Gcc-patches wrote: > > On Fri, Jul 30, 2021 at 12:27:39PM +0200, Uros Bizjak wrote: > > Please put some space here, e.g.: > ... > > Can you just name the relevant insn pattern and use > > > > emit_insn (gen_bsr_1)? > > Here is the updated patch. I

[PATCH] i386: Improve SImode constant - __builtin_clzll for -mno-lzcnt

On Sat, Jul 31, 2021 at 12:53:44PM -0700, H.J. Lu wrote: > On Fri, Jul 30, 2021 at 6:27 AM Jakub Jelinek via Gcc-patches > wrote: > > > > On Fri, Jul 30, 2021 at 12:27:39PM +0200, Uros Bizjak wrote: > > > Please put some space here, e.g.: > > ... > > > Can you just name the relevant insn pattern a

[PATCH v7 03/10] x86: Update piecewise move and store

On Mon, Aug 2, 2021 at 4:20 AM Uros Bizjak wrote: > > On Fri, Jul 30, 2021 at 11:32 PM H.J. Lu wrote: > > > > We can use TImode/OImode/XImode integers for piecewise move and store. > > > > 1. Define MAX_MOVE_MAX to 64, which is the constant maximum number of > > bytes that a single instruction ca

[PATCH] x86: Use XMM31 for scratch SSE register

In 64-bit mode, use XMM31 for scratch SSE register to avoid vzeroupper if possible. gcc/ * config/i386/i386.c (ix86_gen_scratch_sse_rtx): In 64-bit mode, try XMM31 to avoid vzeroupper. gcc/testsuite/ * gcc.target/i386/avx-vzeroupper-14.c: Pass -mno-avx512f to dis

[PATCH] x86: Add testcases for PR target/80566

PR target/80566 * g++.target/i386/pr80566-1.C: New test. * g++.target/i386/pr80566-2.C: Likewise. --- gcc/testsuite/g++.target/i386/pr80566-1.C | 15 +++ gcc/testsuite/g++.target/i386/pr80566-2.C | 14 ++ 2 files changed, 29 insertions(+) create mod

Re: [PATCH] x86: Use XMM31 for scratch SSE register

On Tue, Aug 3, 2021 at 1:43 AM Uros Bizjak wrote: > > On Tue, Aug 3, 2021 at 10:15 AM Hongtao Liu wrote: > > > > On Tue, Aug 3, 2021 at 4:03 PM Uros Bizjak via Gcc-patches > > wrote: > > > > > > On Mon, Aug 2, 2021 at 7:47 PM H.J. Lu wrote: > > > > > > > > In 64-bit mode, use XMM31 for scratch

Re: [PATCH] x86: Use XMM31 for scratch SSE register

On Tue, Aug 3, 2021 at 5:10 AM H.J. Lu wrote: > > On Tue, Aug 3, 2021 at 1:43 AM Uros Bizjak wrote: > > > > On Tue, Aug 3, 2021 at 10:15 AM Hongtao Liu wrote: > > > > > > On Tue, Aug 3, 2021 at 4:03 PM Uros Bizjak via Gcc-patches > > > wrote: > > > > > > > > On Mon, Aug 2, 2021 at 7:47 PM H.J.

[PATCH] by_pieces: Properly set m_max_size in op_by_pieces

1. Update x86 STORE_MAX_PIECES to use OImode and XImode only if inter-unit move is enabled since x86 uses vec_duplicate, which is enabled only when inter-unit move is enabled, to implement store_by_pieces. 2. Update op_by_pieces_d::op_by_pieces_d to set m_max_size to STORE_MAX_PIECES for store_by_p

[PATCH v6] : Add pragma GCC target("general-regs-only")

On Tue, Aug 3, 2021 at 4:47 AM Richard Biener wrote: > > On Sun, Jul 18, 2021 at 3:46 AM H.J. Lu wrote: > > > > On Thu, Apr 22, 2021 at 7:30 AM Richard Biener via Gcc-patches > > wrote: > > > > > > On Thu, Apr 22, 2021 at 2:52 PM Richard Biener > > > wrote: > > > > > > > > On Thu, Apr 22, 2021

Re: [PATCH] by_pieces: Properly set m_max_size in op_by_pieces

On Tue, Aug 3, 2021 at 6:56 AM H.J. Lu wrote: > > 1. Update x86 STORE_MAX_PIECES to use OImode and XImode only if inter-unit > move is enabled since x86 uses vec_duplicate, which is enabled only when > inter-unit move is enabled, to implement store_by_pieces. > 2. Update op_by_pieces_d::op_by_piec

[PATCH v2] by_pieces: Pass MAX_PIECES to op_by_pieces_d

On Wed, Aug 4, 2021 at 12:27 AM Richard Sandiford wrote: > > "H.J. Lu via Gcc-patches" writes: > > @@ -1122,8 +1122,8 @@ class op_by_pieces_d > > and its associated FROM_CFN_DATA can be used to replace loads with > > constant values. LEN des

[PATCH] x86: Avoid stack realignment when copying data with SSE register

To avoid stack realignment, call ix86_gen_scratch_sse_rtx to get a scratch SSE register to copy data with with SSE register from one memory location to another. gcc/ PR target/101772 * config/i386/i386-expand.c (ix86_expand_vector_move): Call ix86_gen_scratch_sse_rtx to ge

[PATCH v2] x86: Update STORE_MAX_PIECES

On Tue, Aug 3, 2021 at 6:56 AM H.J. Lu wrote: > > 1. Update x86 STORE_MAX_PIECES to use OImode and XImode only if inter-unit > move is enabled since x86 uses vec_duplicate, which is enabled only when > inter-unit move is enabled, to implement store_by_pieces. > 2. Update op_by_pieces_d::op_by_piec

[PATCH v3] x86: Update STORE_MAX_PIECES

On Wed, Aug 4, 2021 at 11:46 AM Uros Bizjak wrote: > > On Wed, Aug 4, 2021 at 3:34 PM H.J. Lu wrote: > > > > On Tue, Aug 3, 2021 at 6:56 AM H.J. Lu wrote: > > > > > > 1. Update x86 STORE_MAX_PIECES to use OImode and XImode only if inter-unit > > > move is enabled since x86 uses vec_duplicate, wh

PING^1 [PATCH v3 1/2] Add -f[no-]direct-extern-access

On Mon, Jul 12, 2021 at 5:13 AM H.J. Lu wrote: > > On Sun, Jul 11, 2021 at 11:13 PM Richard Biener > wrote: > > > > On Fri, Jul 9, 2021 at 4:50 PM H.J. Lu wrote: > > > > > > -fdirect-extern-access is the default. With -fno-direct-extern-access: > > > > > > 1. Always use GOT to access undefined

Re: [PATCH] [i386] Remove pass_cpb which is related to enable avx512 embedded broadcast from constant pool.

On Thu, Aug 5, 2021 at 11:21 PM Hongtao Liu wrote: > > On Wed, Jul 14, 2021 at 8:38 PM H.J. Lu wrote: > > > > On Tue, Jul 13, 2021 at 9:35 PM Hongtao Liu wrote: > > > > > > On Wed, Jul 14, 2021 at 10:34 AM liuhongt wrote: > > > > > > > > By optimizing vector movement to broadcast in ix86_expand

[PATCH] Add tests for PR tree-optimization/88531

PR tree-optimization/88531 * gcc.target/i386/pr88531-1a.c: New test. * gcc.target/i386/pr88531-1b.c: Likewise. * gcc.target/i386/pr88531-1c.c: Likewise. * gcc.target/i386/pr88531-2a.c: Likewise. * gcc.target/i386/pr88531-2b.c: Likewise. * gcc.

[PATCH] x86: Optimize load of const all 1s float vectors

Update vector_all_ones_operand to return true for const all 1s float vectors. gcc/ PR target/101804 * config/i386/predicates.md (vector_all_ones_operand): Return true for const all 1s float vectors. gcc/testsuite/ PR target/101804 * gcc.target/i386/avx2-g

[PATCH v2] x86: Optimize load of const all 1s float vectors

On Sun, Aug 8, 2021 at 1:23 PM Uros Bizjak wrote: > > On Sat, Aug 7, 2021 at 4:41 PM H.J. Lu wrote: > > > > Update vector_all_ones_operand to return true for const all 1s float > > vectors. > > > > gcc/ > > > > PR target/101804 > > * config/i386/predicates.md (vector_all_ones_oper

[PATCH v3] x86: Optimize load of const all 1s FP vectors

On Mon, Aug 9, 2021 at 8:27 AM Uros Bizjak wrote: > > On Mon, Aug 9, 2021 at 5:24 PM H.J. Lu wrote: > > > > On Sun, Aug 8, 2021 at 1:23 PM Uros Bizjak wrote: > > > > > > On Sat, Aug 7, 2021 at 4:41 PM H.J. Lu wrote: > > > > > > > > Update vector_all_ones_operand to return true for const all 1s

[PATCH v4] x86: Optimize load of const FP all bits set vectors

On Mon, Aug 9, 2021 at 11:53 AM Uros Bizjak wrote: > > On Mon, Aug 9, 2021 at 7:47 PM H.J. Lu wrote: > > > > On Mon, Aug 9, 2021 at 8:27 AM Uros Bizjak wrote: > > > > > > On Mon, Aug 9, 2021 at 5:24 PM H.J. Lu wrote: > > > > > > > > On Sun, Aug 8, 2021 at 1:23 PM Uros Bizjak wrote: > > > > > >

[PATCH] Enable gcc.target/i386/pr88531-1a.c for all targets

PR tree-optimization/101809 * gcc.target/i386/pr88531-1a.c: Enable for all targets. --- gcc/testsuite/gcc.target/i386/pr88531-1a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/i386/pr88531-1a.c b/gcc/testsuite/gcc.target/i386/pr88531

Re: [PATCH] i386: support micro-levels in target{, _clone} attrs [PR101696]

On Thu, Aug 12, 2021 at 7:12 AM Martin Liška wrote: > > Patch can bootstrap on x86_64-linux-gnu and survives regression tests. > I modified the H.J. patch draft. Please send out the v2 patch with the enclosed patch. I added some tests. > @H.J. Can you please verify the newly added 'feature_prio

Re: [PATCH] i386: support micro-levels in target{, _clone} attrs [PR101696]

On Thu, Aug 12, 2021 at 7:39 AM Martin Liška wrote: > > On 8/12/21 4:25 PM, H.J. Lu wrote: > > Please send out the v2 patch with the enclosed patch. I added some tests. > > Thanks, there's patch which includes your changes. > > Martin diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/

Re: [PATCH] i386: support micro-levels in target{, _clone} attrs [PR101696]

On Thu, Aug 12, 2021 at 8:22 AM Martin Liška wrote: > > On 8/12/21 4:51 PM, H.J. Lu wrote: > > On Thu, Aug 12, 2021 at 7:39 AM Martin Liška wrote: > >> > >> On 8/12/21 4:25 PM, H.J. Lu wrote: > >>> Please send out the v2 patch with the enclosed patch. I added some tests. > >> > >> Thanks, there'

Re: [PATCH] i386: support micro-levels in target{, _clone} attrs [PR101696]

On Thu, Aug 12, 2021 at 8:31 AM Martin Liška wrote: > > On 8/12/21 5:26 PM, H.J. Lu wrote: > > Will it hurt if they have proper feature_priorities you added? > > No. They are unused, by we should use the proper priorities. > > Martin + const char *arch_name = attrs_str + strlen ("arch="); +

Re: [PATCH] i386: support micro-levels in target{, _clone} attrs [PR101696]

On Fri, Aug 13, 2021 at 1:10 AM Martin Liška wrote: > > On 8/12/21 7:35 PM, H.J. Lu wrote: > > What happens for arch=x86-64-v5? > > pr101696.c:5:55: error: bad value (‘x86-64-v5’) for ‘target("arch=")’ > attribute > > 5 | __attribute__ ((target ("arch=x86-64-v5"))) void foo () { > __builti

[PATCH 3/5] x86: Remove OPTION_MASK_ISA_SSE4_2 from CRC32 _builtin functions

Since commit 39671f87b2df6a1894cc11a161e4a7949d1ddccd Author: H.J. Lu Date: Thu Apr 15 05:59:48 2021 -0700 x86: Use crc32 target option for CRC32 intrinsics enabled OPTION_MASK_ISA_CRC32 for -msse4 and removed TARGET_SSE4_2 check in sse4_2_crc32 pattens, remove OPTION_MASK_ISA_SSE4_2 from

[PATCH 2/5] x86: Use crc32 target option for CRC32 intrinsics

Use crc32 target option for CRC32 intrinsics to support CRC32 intrinsics without enabling SSE vector instructions. * config/i386/i386-c.c (ix86_target_macros_internal): Define __CRC32__ for -mcrc32. * config/i386/i386-options.c (ix86_option_override_internal): Enabl

[PATCH 4/5] x86: Enable the GPR only instructions for -mgeneral-regs-only

For -mgeneral-regs-only, enable the GPR only instructions which are enabled implicitly by SSE ISAs unless they have been disabled explicitly. gcc/ PR target/101492 * common/config/i386/i386-common.c (ix86_handle_option): For -mgeneral-regs-only, enable the GPR only instruc

[GCC-11] [PATCH 0/5] Finish and general-regs-only

and target("general-regs-only") function attribute were added to GCC 11. But their implementations are incomplete. I'd like to backport the following patches to GCC 11 branch to finish them. H.J. Lu (5): x86: Add -mmwait for -mgeneral-regs-only x86: Use crc32 target option for CRC32 intrins

[PATCH 1/5] x86: Add -mmwait for -mgeneral-regs-only

Add -mmwait so that the MWAIT and MONITOR intrinsics can be used with -mgeneral-regs-only and make -msse3 to imply -mmwait. gcc/ * config.gcc: Install mwaitintrin.h for i[34567]86-*-* and x86_64-*-* targets. * common/config/i386/i386-common.c (OPTION_MASK_ISA2_MWAIT_SET):

[PATCH 5/5] : Add pragma GCC target("general-regs-only")

1. Intrinsics in only require GPR ISAs. Add #if defined __MMX__ || defined __SSE__ #pragma GCC push_options #pragma GCC target("general-regs-only") #define __DISABLE_GENERAL_REGS_ONLY__ #endif and #ifdef __DISABLE_GENERAL_REGS_ONLY__ #undef __DISABLE_GENERAL_REGS_ONLY__ #pragma GCC pop

Re: [PATCH 1/5] x86: Add -mmwait for -mgeneral-regs-only

On Sun, Aug 15, 2021 at 11:11 PM Richard Biener wrote: > > On Fri, Aug 13, 2021 at 3:51 PM H.J. Lu wrote: > > > > Add -mmwait so that the MWAIT and MONITOR intrinsics can be used with > > -mgeneral-regs-only and make -msse3 to imply -mmwait. > > Adding new options requires to bump the LTO streami

Re: [PATCH 1/5] x86: Add -mmwait for -mgeneral-regs-only

On Mon, Aug 16, 2021 at 5:28 AM Richard Biener wrote: > > On Mon, Aug 16, 2021 at 2:25 PM H.J. Lu wrote: > > > > On Sun, Aug 15, 2021 at 11:11 PM Richard Biener > > wrote: > > > > > > On Fri, Aug 13, 2021 at 3:51 PM H.J. Lu wrote: > > > > > > > > Add -mmwait so that the MWAIT and MONITOR intrin

Re: [PATCH] Revert "Add the member integer_to_sse to processor_cost as a cost simulation for movd/pinsrd. It will be used to calculate the cost of vec_construct."

On Tue, Aug 17, 2021 at 5:43 AM liuhongt via Gcc-patches wrote: > > This reverts commit 872da9a6f664a06d73c987aa0cb2e5b830158a10. > > PR target/101936 > PR target/101929 > > Bootstrapped and regtested on x86_64-linux-gnu{-m32,} > Pushed to master. > I proposed a different approach earlier.

Re: [committed] Introduce selftest::locate_file (v5)

On Tue, Aug 17, 2021 at 12:01 AM Thomas Schwinge wrote: > > Hi! > > On 2016-12-14T21:31:05-0500, David Malcolm wrote: > > On Wed, 2016-12-14 at 15:02 +0100, Bernd Schmidt wrote: > >> On 12/09/2016 08:32 PM, David Malcolm wrote: > >> > Thanks. Unfortunately, applying the "locate_file" patch > >>

Re: [PATCH] PR fortran/100950 - ICE in output_constructor_regular_field, at varasm.c:5514

On Thu, Aug 19, 2021 at 12:12 PM Harald Anlauf via Gcc-patches wrote: > > Hi Tobias, > > > I am inclined to say that the Intel compiler has a bug by not > > accepting it – but as written before, I regard sub-string length > > (esp. with const expr) inquiries as an odd corner case which > > is unli

[PATCH] x86: Allow CONST_VECTOR for vector load in combine

In vetor move pattern, replace nonimmediate_or_sse_const_operand with nonimmediate_or_sse_const_vector_operand to allow vector load from non-uniform CONST_VECTOR. Non-uniform CONST_VECTOR is enabled only in the combine pass since other RTL optimizers work better with constant pool. gcc/

PING [PATCH] x86: Update memcpy/memset inline strategies for -mtune=generic

On Tue, Mar 23, 2021 at 09:19:38AM +0100, Richard Biener wrote: > On Tue, Mar 23, 2021 at 3:41 AM Hongyu Wang wrote: > > > > > Hongyue, please collect code size differences on SPEC CPU 2017 and > > > eembc. > > > > Here is code size difference for this patch > > Thanks, nothing too bad although s

Re: [PATCH] IPA: MODREF should skip EAF_* flags for indirect calls

On Sun, Aug 22, 2021 at 10:32 AM Jan Hubicka wrote: > > > Thanks for looking into this bug - it is interesting that ipa-pta > > requires !EAF_NOCLOBBER when function is called... > > > > I have some work done on teaching ipa-modref (and other propagation > > passes) to use ipa-devirt info when the

[PATCH v2] x86: Allow CONST_VECTOR for vector load in combine

On Mon, Aug 23, 2021 at 03:23:26PM +0800, Hongtao Liu wrote: > On Sun, Aug 22, 2021 at 8:54 PM H.J. Lu via Gcc-patches > wrote: > > > > In vetor move pattern, replace nonimmediate_or_sse_const_operand with > > nonimmediate_or_sse_const_vector_operand to allow vector l

[PATCH] x86: Broadcast from integer to a pseudo vector register

Broadcast from integer to a pseudo vector register instead of a hard vector register to allow LRA to remove redundant move instruction after broadcast. gcc/ PR target/102021 * config/i386/i386-expand.c (ix86_expand_vector_move): Broadcast from integer to a pseudo vector re

Re: [PATCH] x86: Broadcast from integer to a pseudo vector register

On Mon, Aug 23, 2021 at 6:17 PM Hongtao Liu wrote: > > On Tue, Aug 24, 2021 at 9:01 AM H.J. Lu via Gcc-patches > wrote: > > > > Broadcast from integer to a pseudo vector register instead of a hard > > vector register to allow LRA to remove redundant move inst

Re: [PATCH v2] x86: Allow CONST_VECTOR for vector load in combine

On Mon, Aug 23, 2021 at 6:52 PM Hongtao Liu wrote: > > On Mon, Aug 23, 2021 at 9:14 PM H.J. Lu wrote: > > > > On Mon, Aug 23, 2021 at 03:23:26PM +0800, Hongtao Liu wrote: > > > On Sun, Aug 22, 2021 at 8:54 PM H.J. Lu via Gcc-patches > > > wrote: > >

Re: [GCC-11] [PATCH 0/5] Finish and general-regs-only

On Sun, Aug 15, 2021 at 11:11 PM Richard Biener wrote: > > On Fri, Aug 13, 2021 at 3:51 PM H.J. Lu wrote: > > > > and target("general-regs-only") function attribute > > were added to GCC 11. But their implementations are incomplete. I'd > > like to backport the following patches to GCC 11 bran

Re: [PATCH v2] x86: Allow CONST_VECTOR for vector load in combine

On Tue, Aug 24, 2021 at 9:16 AM Segher Boessenkool wrote: > > On Tue, Aug 24, 2021 at 09:57:52AM +0800, Hongtao Liu wrote: > > Trying 5 -> 7: > > 5: r85:V4SF=[`*.LC0'] > > REG_EQUAL const_vector > > 7: r84:V4SF=vec_select(vec_concat(r85:V4SF,r85:V4SF),parallel) > > REG_DEAD r85

Re: [GCC-11] [PATCH 0/5] Finish and general-regs-only

On Wed, Aug 25, 2021 at 12:34 AM Uros Bizjak wrote: > > On Tue, Aug 24, 2021 at 4:57 PM H.J. Lu wrote: > > > > On Sun, Aug 15, 2021 at 11:11 PM Richard Biener > > wrote: > > > > > > On Fri, Aug 13, 2021 at 3:51 PM H.J. Lu wrote: > > > > > > > > and target("general-regs-only") function attribut

Re: [llvm-dev] [PATCH] Add optional _Float16 support

On Mon, Aug 23, 2021 at 10:55 PM John McCall wrote: > > On Thu, Jul 29, 2021 at 9:40 AM H.J. Lu wrote: >> >> On Tue, Jul 13, 2021 at 9:24 AM H.J. Lu wrote: >> > >> > On Tue, Jul 13, 2021 at 8:41 AM Joseph Myers >> > wrote: >> > > >> > > On Tue, 13 Jul 2021, H.J. Lu wrote: >> > > >> > > > On Mo

Re: [PATCH] configure: Allow a host makefile fragment to override PIE flag settings.

On Wed, Aug 25, 2021 at 10:42 AM Iain Sandoe wrote: > > Hi, > > > On 20 Aug 2021, at 11:29, Richard Sandiford > > wrote: > > > >>> Maybe it would be easier to have the makefile fragments determine > >>> something like CODE_MODEL_CFLAGS, which can be "-fPIC", > >>> "-mdynamic-no-pic", > >>> etc.

Re: [PATCH] configure: Allow a host makefile fragment to override PIE flag settings.

On Wed, Aug 25, 2021 at 10:51 AM H.J. Lu wrote: > > On Wed, Aug 25, 2021 at 10:42 AM Iain Sandoe wrote: > > > > Hi, > > > > > On 20 Aug 2021, at 11:29, Richard Sandiford > > > wrote: > > > > > >>> Maybe it would be easier to have the makefile fragments determine > > >>> something like CODE_MODE

Re: [PATCH] diagnostics: Fix sporadic test failure

On Sat, May 29, 2021 at 1:03 PM Jeff Law via Gcc-patches wrote: > > > > On 5/29/2021 1:55 PM, Bernd Edlinger wrote: > > > > On 5/29/21 9:31 PM, Jeff Law wrote: > >> > >> On 5/28/2021 6:38 AM, Bernd Edlinger wrote: > >>> Hi, > >>> > >>> it turns out to be reproducible this way: > >>> > >>> COLUMNS=

Re: [PATCH] configure: Allow a host makefile fragment to override PIE flag settings.

On Wed, Aug 25, 2021 at 11:10 AM Iain Sandoe wrote: > > > > > On 25 Aug 2021, at 18:56, H.J. Lu via Gcc-patches > > wrote: > > > > On Wed, Aug 25, 2021 at 10:51 AM H.J. Lu wrote: > >> > >> On Wed, Aug 25, 2021 at 10:42 AM Iain Sandoe >

Re: Merge stores/loads in modref summaries

On Thu, Aug 26, 2021 at 2:49 AM Jan Hubicka wrote: > > > On 8/26/21 10:33, Christophe Lyon via Gcc-patches wrote: > > > Can you have a look? > > > > Please create a PR for it. > I have fix, so perhaps there is no need for PR :) > I am testing the following - the problem was that try_merge_with mis

[PATCH] x86-64: Add ABI warning for 64-bit vectors

TYPE_MODE of record and union depends on whether vector_mode_supported_p returns true or not. x86-64 backend uses TYPE_MODE to decide how to pass a parameter and return a value in a function. 64-bit integer vectors were supported only by MMX and 64-bit float vector was supported only by 3DNOW. GC

Re: [PATCH] x86-64: Add ABI warning for 64-bit vectors

On Sun, Aug 29, 2021 at 8:34 AM Jakub Jelinek wrote: > > On Sun, Aug 29, 2021 at 08:24:10AM -0700, H.J. Lu via Gcc-patches wrote: > > + if (gcc_version) > > + { > > + if (in_return) > > + { > > + static bool warnedm64_ret

[wwwdocs] [PATCH] x86-64: Document ABI changes for structures with a 64-bit vector

TYPE_MODE of record and union depends on whether vector_mode_supported_p returns true or not. x86-64 backend uses TYPE_MODE to decide how to pass a parameter and return a value in a function. 64-bit integer vectors were supported only by MMX and 64-bit float vector was supported only by 3DNOW. G

[PATCH v2] x86-64: Add ABI warning for 64-bit vectors

TYPE_MODE of record and union depends on whether vector_mode_supported_p returns true or not. x86-64 backend uses TYPE_MODE to decide how to pass a parameter and return a value in a function. 64-bit integer vectors were supported only by MMX and 64-bit float vector was supported only by 3DNOW. G

Re: libgo patch committed: Update to Go1.17rc2 release

On Thu, Aug 12, 2021 at 8:24 PM Ian Lance Taylor via Gcc-patches wrote: > > This patch updates libgo from the Go1.16.5 release to the Go 1.17rc2 > release. As usual with these version updates, the patch itself is too > large to attach to this e-mail message. I've attached the changes to > files

[PATCH] gcc-12: Mention -mharden-sls= and -mindirect-branch-cs-prefix

--- htdocs/gcc-12/changes.html | 6 ++ 1 file changed, 6 insertions(+) diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html index 2719b9d5..479bd6c5 100644 --- a/htdocs/gcc-12/changes.html +++ b/htdocs/gcc-12/changes.html @@ -387,6 +387,12 @@ a work-in-progress. x86 sys

Re: [GCC 11 PATCH 0/5] x86: Backport straight-line-speculation mitigation

On Mon, Jan 31, 2022 at 11:21 PM Richard Biener wrote: > > On Mon, Jan 31, 2022 at 7:56 PM H.J. Lu via Gcc-patches > wrote: > > > > Backport -mindirect-branch-cs-prefix: > > LGTM in case a x86 maintainer also acks this. Can you amend > the 10.3 release gcc-11/

[PATCH] x86: Check each component of source operand for AVX_U128_DIRTY

commit 9775e465c1fbfc32656de77c618c61acf5bd905d Author: H.J. Lu Date: Tue Jul 27 07:46:04 2021 -0700 x86: Don't set AVX_U128_DIRTY when zeroing YMM/ZMM register called ix86_check_avx_upper_register to check mode on source operand. But ix86_check_avx_upper_register doesn't work on source op

Re: [PATCH v4] x86: Add -m[no-]direct-extern-access

On Tue, Feb 8, 2022 at 6:38 PM Hongtao Liu wrote: > > On Fri, Jan 28, 2022 at 5:53 AM H.J. Lu via Gcc-patches > wrote: > > > > The v3 patch was posted at > > > > https://gcc.gnu.org/pipermail/gcc-patches/2021-July/574847.html > > > > There is no pr

[COMMITED][PATCH] x86: Compile PR target/104441 tests with -march=x86-64

Compile PR target/104441 tests with -march=x86-64 to fix test failures when GCC is configured with --with-arch=native --with-cpu=native. PR target/104441 * gcc.target/i386/pr104441-1a.c: Compile with -march=x86-64. * gcc.target/i386/pr104441-1b.c: Likewise. --- gcc/testsui

[PATCH] x86: Update PR 35513 tests

1. Require linker with GNU_PROPERTY_1_NEEDED support for PR 35513 run-time tests. 2. Compile pr35513-8.c to scan assembly code. PR testsuite/104481 * g++.target/i386/pr35513-1.C: Require property_1_needed target. * g++.target/i386/pr35513-2.C: Likewise. * gcc.target

[PATCH] pr104458.c: Replace long with long long for -mx32

PR target/104458 * gcc.target/i386/pr104458.c: Replace long with long long. --- gcc/testsuite/gcc.target/i386/pr104458.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/testsuite/gcc.target/i386/pr104458.c b/gcc/testsuite/gcc.target/i386/pr104458.c index d1

Re: [PATCH] x86: Update PR 35513 tests

On Fri, Feb 11, 2022 at 9:43 PM Hongtao Liu wrote: > > On Thu, Feb 10, 2022 at 9:58 PM H.J. Lu via Gcc-patches > wrote: > > > > 1. Require linker with GNU_PROPERTY_1_NEEDED support for PR 35513 > > run-time tests. > > 2. Compile pr35513-8.c to scan assembly c

[wwwdocs PATCH] gcc-12: Mention -mno-direct-extern-access

--- htdocs/gcc-12/changes.html | 3 +++ 1 file changed, 3 insertions(+) diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html index b6341fda..897de8ef 100644 --- a/htdocs/gcc-12/changes.html +++ b/htdocs/gcc-12/changes.html @@ -399,6 +399,9 @@ a work-in-progress. Add CS prefix t

[wwwdocs PATCH v2] gcc-12: Mention -mno-direct-extern-access

--- htdocs/gcc-12/changes.html | 4 1 file changed, 4 insertions(+) diff --git a/htdocs/gcc-12/changes.html b/htdocs/gcc-12/changes.html index b6341fda..7d253f29 100644 --- a/htdocs/gcc-12/changes.html +++ b/htdocs/gcc-12/changes.html @@ -399,6 +399,10 @@ a work-in-progress. Add CS prefix

Re: [wwwdocs PATCH] gcc-12: Mention -mno-direct-extern-access

On Sat, Feb 12, 2022 at 2:27 PM Gerald Pfeifer wrote: > > On Sat, 12 Feb 2022, H.J. Lu via Gcc-patches wrote: > > + Always use GOT to access external data and function symbols via > > + -mno-direct-extern-access. > > Maybe say "global offset table (GOT)&qu

Re: [GCC 11 PATCH 0/5] x86: Backport straight-line-speculation mitigation

On Tue, Feb 15, 2022 at 10:52 PM Hongtao Liu wrote: > > On Tue, Feb 1, 2022 at 2:55 AM H.J. Lu via Gcc-patches > wrote: > > > > Backport -mindirect-branch-cs-prefix: > > > > commit 48a4ae26c225eb018ecb59f131e2c4fd4f3cf89a > > Author: H.J. Lu >

[wwwdocs PATCH] gcc-11.3: Mention -mharden-sls= and -mindirect-branch-cs-prefix

--- htdocs/gcc-11/changes.html | 7 +++ 1 file changed, 7 insertions(+) diff --git a/htdocs/gcc-11/changes.html b/htdocs/gcc-11/changes.html index fbd1b8ba..8e6d4ec8 100644 --- a/htdocs/gcc-11/changes.html +++ b/htdocs/gcc-11/changes.html @@ -1129,6 +1129,13 @@ are not listed here). no l

[PATCH] x86: Add TARGET_READ_ZERO_YMM_ZMM_NEED_VZEROUPPER

Reading YMM registers with all zero bits needs VZEROUPPER on Sandy Bride, Ivy Bridge, Haswell, Broadwell and Alder Lake to avoid SSE <-> AVX transition penalty. Add TARGET_READ_ZERO_YMM_ZMM_NEED_VZEROUPPER to generate vzeroupper instruction after loading all-zero YMM/YMM registers and enable it by

[PATCH v2] x86: Add TARGET_OMIT_VZEROUPPER_AFTER_AVX_READ_ZERO

On Thu, Feb 17, 2022 at 08:51:31AM +0100, Uros Bizjak wrote: > On Thu, Feb 17, 2022 at 6:25 AM Hongtao Liu via Gcc-patches > wrote: > > > > On Thu, Feb 17, 2022 at 12:26 PM H.J. Lu via Gcc-patches > > wrote: > > > > > > Reading YMM registers with all

Re: [PATCH] x86: Add TARGET_READ_ZERO_YMM_ZMM_NEED_VZEROUPPER

On Thu, Feb 17, 2022 at 10:49:48AM +0100, Richard Biener via Gcc-patches wrote: > On Thu, Feb 17, 2022 at 8:52 AM Uros Bizjak via Gcc-patches > wrote: > > > > On Thu, Feb 17, 2022 at 6:25 AM Hongtao Liu via Gcc-patches > > wrote: > > > > > > On Thu

[PATCH] pieces-memset-21.c: Expect vzeroupper for ia32

On Thu, Feb 17, 2022 at 6:32 PM Hongtao Liu via Gcc-patches wrote: > > On Thu, Feb 17, 2022 at 9:47 PM Richard Biener via Gcc-patches > wrote: > > > > The x86 backend piggy-backs on mode-switching for insertion of > > vzeroupper. A recent improvement there was implemented in a way > > to walk po

Re: [PATCH v2] x86: Add TARGET_OMIT_VZEROUPPER_AFTER_AVX_READ_ZERO

> > > > > > On Thu, Feb 17, 2022 at 12:26 PM H.J. Lu via Gcc-patches > > > > wrote: > > > > > > > > > > Reading YMM registers with all zero bits needs VZEROUPPER on Sandy > > > > > B

Re: [PATCH v2] x86: Add TARGET_OMIT_VZEROUPPER_AFTER_AVX_READ_ZERO

; > On Thu, Feb 17, 2022 at 08:51:31AM +0100, Uros Bizjak wrote: > > > > > On Thu, Feb 17, 2022 at 6:25 AM Hongtao Liu via Gcc-patches > > > > > wrote: > > > > > > > > > > > > On Thu, Feb 17, 2022 at 12:26 PM H.J. L

[PATCH] Add -fcf-check-attribute=[yes|no|none] for Linux kernel

When compiling Linux kernel with -fcf-protection=branch to enable x86 Indiret Branch Tracking (IBT), ENDBR is added to all global functions. This creates more "legal" forward edges than necessary. -mmanual-endbr provides a way to insert ENDBR instruction at function entry only via the 'cf_check' f

[PATCH] x86: Skip ENDBR when emitting direct call/jmp to local function

Skip the 4-byte ENDBR when emitting a direct call/jmp to a local function with ENDBR at function entry. This has been tested on Linux kernel. gcc/ PR target/102953 * config/i386/i386-features.cc (rest_of_insert_endbr_and_patchable_area): Set SYMBOL_FLAG_FUNCTION_E

Re: [PATCH] [i386] Replace ix86_gen_scratch_sse_rtx with gen_reg_rtx.

On Mon, Feb 28, 2022 at 6:03 PM liuhongt wrote: > > .. in ix86_expand_vector_move and > ix86_convert_const_wide_int_to_broadcast(called by the former). > > ix86_expand_vector_move is called by emit_move_insn which is used by > many pre_reload passes, ix86_gen_scratch_sse_rtx will break data flow >

Re: [PATCH] [i386] Replace ix86_gen_scratch_sse_rtx with gen_reg_rtx.

On Mon, Feb 28, 2022 at 6:26 PM H.J. Lu wrote: > > On Mon, Feb 28, 2022 at 6:03 PM liuhongt wrote: > > > > .. in ix86_expand_vector_move and > > ix86_convert_const_wide_int_to_broadcast(called by the former). > > > > ix86_expand_vector_move is called by emit_move_insn which is used by > > many pr

[PATCH] Clear currently_expanding_gimple_stmt properly

commit a5883ba0de68efad36db145e75c86394d8bd44ea Author: Michael Matz Date: Tue Nov 24 15:37:32 2009 + introduced currently_expanding_gimple_stmt, which was set and cleared in expand_gimple_basic_block when expanding gimple statement to RTL. But it isn't cleared when expand_gimple_basic_blo

Re: [PATCH] [i386] Replace ix86_gen_scratch_sse_rtx with gen_reg_rtx.

On Mon, Feb 28, 2022 at 9:36 PM Hongtao Liu wrote: > > On Tue, Mar 1, 2022 at 10:39 AM H.J. Lu via Gcc-patches > wrote: > > > > On Mon, Feb 28, 2022 at 6:26 PM H.J. Lu wrote: > > > > > > On Mon, Feb 28, 2022 at 6:03 PM liuhongt wrote: > >

[PATCH] x86: Limit PR 35513 tests to Linux

Limit PR 35513 tests to Linux since they fail on 32-bit Solaris/x86 with Solaris linker. PR testsuite/104725 * g++.target/i386/pr35513-1.C: Limit to Linux. * g++.target/i386/pr35513-2.C: Likewise. --- gcc/testsuite/g++.target/i386/pr35513-1.C | 2 +- gcc/testsuite/g++.targ

[PATCH] Use C++ RAII to clear currently_expanding_gimple_stmt

Use C++ RAII with make_temp_override in the C++ FE to automatically clear currently_expanding_gimple_stmt. gcc/ PR middle-end/104721 * cfgexpand.cc (expand_gimple_basic_block): Use make_temp_override to clear currently_expanding_gimple_stmt automatically. * tree.h

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