Hi Saurabh,
> On 6 Nov 2024, at 11:03, saurabh@arm.com wrote:
>
>
> The AArch64 FEAT_FP8 extension introduces instructions for conversion
> and scaling.
>
> This patch introduces the following intrinsics:
> 1. vcvt{1|2}_{bf16|high_bf16|low_bf16}_mf8_fpm.
> 2. vcvt{q}_mf8_f16_fpm.
> 3. vcvt_
Hi Victor,
> On 31 Oct 2024, at 22:40, Victor Do Nascimento
> wrote:
>
> Implement -mcpu options for:
>
> - Cortex-A520AE
> - Cortex-A720AE
> - Cortex-R82AE
>
> These all implement the same feature sets as their non-AE
> counterparts, using the same scheduler and costs and differing only i
Hi Vladimir,
Thanks for the patches!
> On 6 Nov 2024, at 08:50, vladimir.miloser...@arm.com wrote:
>
>
> The AArch64 FEAT_LUT extension is optional from Armv9.2-a and mandatory
> from Armv9.5-a. This extension introduces instructions for lookup table
> read with 2-bit indices.
>
> This patch ad
Forwarding to the correct ML...
> Begin forwarded message:
>
> From: Kyrylo Tkachov via Gcc
> Subject: [PATCH] PR target/117449: Restrict vector rotate match and split to
> pre-reload
> Date: 5 November 2024 at 17:57:40 GMT+1
> To: gcc mailing list
> Reply-To: Ky
> On 4 Nov 2024, at 16:03, Kyrylo Tkachov wrote:
>
>
>
>> On 4 Nov 2024, at 15:20, Jakub Jelinek wrote:
>>
>> On Mon, Nov 04, 2024 at 02:31:29PM +0100, Jakub Jelinek wrote:
>>> On Mon, Nov 04, 2024 at 01:07:33PM +, Kyrylo Tkachov wrote:
>>>&g
> On 4 Nov 2024, at 15:20, Jakub Jelinek wrote:
>
> On Mon, Nov 04, 2024 at 02:31:29PM +0100, Jakub Jelinek wrote:
>> On Mon, Nov 04, 2024 at 01:07:33PM +, Kyrylo Tkachov wrote:
>>>> This seems to have broken bootstrap on multiple targets and is caus
> On 4 Nov 2024, at 13:55, Richard Biener wrote:
>
> On Thu, Oct 31, 2024 at 4:30 PM Jeff Law wrote:
>>
>>
>>
>> On 10/27/24 10:21 AM, Kyrylo Tkachov wrote:
>>> Hi all,
>>>
>>> simplify-rtx can transform (X << C1) | (X &
> On 31 Oct 2024, at 18:06, Richard Sandiford wrote:
>
> Wilco Dijkstra writes:
>> The early scheduler takes up ~33% of the total build time, however it doesn't
>> provide a meaningful performance gain. This is partly because modern OoO
>> cores
>> need far less scheduling, partly because th
Hi Jeff,
> On 31 Oct 2024, at 16:25, Jeff Law wrote:
>
>
>
> On 10/27/24 10:22 AM, Kyrylo Tkachov wrote:
>> Hi all,
>> Some vector rotate operations can be implemented in a single instruction
>> rather than using the fallback SHL+USRA sequence.
>> In par
> On 31 Oct 2024, at 14:23, Yury Khrustalev wrote:
>
> From: Szabolcs Nagy
>
> Builtin for chkfeat: the input argument is used to initialize x16 then
> execute chkfeat and return the updated x16.
>
> Note: ACLE __chkfeat(x) plans to flip the bits to be more intuitive
> (xor the input to outp
Hi Yury,
> On 31 Oct 2024, at 14:23, Yury Khrustalev wrote:
>
> From: Szabolcs Nagy
>
> Add new builtins for GCS:
>
> void *__builtin_aarch64_gcspr (void)
> uint64_t __builtin_aarch64_gcspopm (void)
> void *__builtin_aarch64_gcsss (void *)
>
> The builtins are always enabled, but should b
> On 31 Oct 2024, at 11:50, Richard Sandiford wrote:
>
> "Yuta Mukai (Fujitsu)" writes:
>> Hello,
>>
>> This patch adds initial support for FUJITSU-MONAKA CPU, which we are
>> developing.
>> This is the slides for the CPU:
>> https://www.fujitsu.com/downloads/SUPER/topics/isc24/next-arm-bas
> On 27 Oct 2024, at 20:42, Jeff Law wrote:
>
>
>
> On 10/24/24 12:24 AM, Kyrylo Tkachov wrote:
>>> On 24 Oct 2024, at 07:36, Jeff Law wrote:
>>>
>>>
>>>
>>> On 10/22/24 2:26 PM, Kyrylo Tkachov wrote:
>>>> Hi all,
&g
Hi all,
Looks like this immediate variable was missed out when I last fixed the
namespace issues in arm_neon.h. Fixed in the obvious manner.
Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk.
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
* config/aarch64/arm_neon.h
> On 25 Oct 2024, at 15:25, Richard Sandiford wrote:
>
> Kyrylo Tkachov writes:
>>> On 25 Oct 2024, at 13:46, Richard Sandiford
>>> wrote:
>>>
>>> Kyrylo Tkachov writes:
>>>> Thank you for the suggestions! I’m trying them
This change is not enough to generate the
equivalent sequence in SVE, but that is something that should be tackled
separately.
Bootstrapped and tested on aarch64-none-linux-gnu.
Signed-off-by: Kyrylo Tkachov
gcc/
* simplify-rtx.cc (simplify_context::simplify_binary_operat
ensure the permute indices are not messed
up.
Bootstrapped and tested on aarch64-none-linux-gnu.
Richard had approved these changes in the previous iteration, but I’ll only push
this after the prerequisites in the series.
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
gcc/
* expmed.h
usrav31.4s, v0.4s, 23
mov v0.16b, v31.16b
ret
G2:
shl v31.8b, v0.8b, 3
usrav31.8b, v0.8b, 5
mov v0.8b, v31.8b
ret
Bootstrapped and tested on aarch64-none-linux-gnu.
Signed-off-by: Kyrylo Tkachov
gcc/
-none-linux-gnu.
I’ll push this if the prerequisites are approved.
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
gcc/
PR target/117048
* config/aarch64/aarch64-simd.md (*aarch64_simd_rotate_imm):
New define_insn_and_split.
gcc/testsuite/
PR target/117048
lf-tests in this
patch to validate the transformation.
Bootstrapped and tested on aarch64-none-linux-gnu.
Ok for mainline?
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
PR target/117048
* simplify-rtx.cc (extract_ashift_operands_p): Define.
(simplif
ed on aarch64-none-linux-gnu.
Ok for mainline?
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
gcc/
* config/aarch64/iterators.md (SVE_ASIMD_FULL_I): New mode iterator.
* config/aarch64/aarch64-sve2.md (@aarch64_sve2_xar):
Use SVE_ASIMD_FULL_I modes. Use ROTATE code for the r
> On 25 Oct 2024, at 13:46, Richard Sandiford wrote:
>
> Kyrylo Tkachov writes:
>> Thank you for the suggestions! I’m trying them out now.
>>
>>>> + if (rotamnt % BITS_PER_UNIT != 0)
>>>> +return NULL_RTX;
>>>> + machine_mo
Thank you for the suggestions! I’m trying them out now.
> On 24 Oct 2024, at 21:11, Richard Sandiford wrote:
>
> Kyrylo Tkachov writes:
>> Hi Richard,
>>
>>> On 23 Oct 2024, at 11:30, Richard Sandiford
>>> wrote:
>>>
>>> Kyrylo Tk
Hi Andrew,
> On 25 Oct 2024, at 01:10, Andrew Pinski wrote:
>
> On Mon, Jun 3, 2024 at 2:23 AM Andrew Pinski (QUIC)
> wrote:
>>
>>> -Original Message-
>>> From: Andrew Pinski (QUIC)
>>> Sent: Saturday, May 4, 2024 2:03 AM
>>> To: gcc-patches@gcc.gnu.org
>>> Cc: Andrew Pinski (QUIC)
>
Hi Richard,
> On 23 Oct 2024, at 11:30, Richard Sandiford wrote:
>
> Kyrylo Tkachov writes:
>> Hi all,
>>
>> Some vector rotate operations can be implemented in a single instruction
>> rather than using the fallback SHL+USRA sequence.
>> In particu
> On 24 Oct 2024, at 10:39, Soumya AR wrote:
>
> Hi Richard,
>
> > On 23 Oct 2024, at 5:58 PM, Richard Sandiford
> > wrote:
> >
> > External email: Use caution opening links or attachments
> >
> >
> > Soumya AR writes:
> >> diff --git a/gcc/config/aarch64/aarch64-sve-builtins.cc
> >> b/
> On 24 Oct 2024, at 07:36, Jeff Law wrote:
>
>
>
> On 10/22/24 2:26 PM, Kyrylo Tkachov wrote:
>> Hi all,
>> With recent patch to improve detection of vector rotates at RTL level
>> combine now tries matching a V8HImode rotate by 8 in the example in the
>
I’ve updated and extended this patch series at:
https://gcc.gnu.org/pipermail/gcc-patches/2024-October/666137.html
So please review that one instead.
Thanks,
Kyrill
> On 16 Oct 2024, at 15:56, Kyrylo Tkachov wrote:
>
> Hi all,
>
> The motivating testcase for this is in AAr
on aarch64-none-linux-gnu.
I’ll commit this if the prerequisites are approved.
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
gcc/
PR target/117048
* config/aarch64/aarch64-simd.md (*aarch64_simd_rotate_imm):
New define_insn_and_split.
gcc/testsuite/
P
This change is not enough to generate the
equivalent sequence in SVE, but that is something that should be tackled
separately.
Bootstrapped and tested on aarch64-none-linux-gnu.
Signed-off-by: Kyrylo Tkachov
gcc/
* simplify-rtx.cc (simplify_context::simplify_binary_operat
e, so restrict the
SVE2 pattern accordingly. Tests are added to confirm this.
Bootstrapped and tested on aarch64-none-linux-gnu.
Ok for mainline?
Signed-off-by: Kyrylo Tkachov
gcc/
* config/aarch64/iterators.md (SVE_ASIMD_FULL_I): New mode iterator.
* config/aarch64/aarch64-sv
:
shl v31.4s, v0.4s, 9
usrav31.4s, v0.4s, 23
mov v0.16b, v31.16b
ret
G2:
shl v31.8b, v0.8b, 3
usrav31.8b, v0.8b, 5
mov v0.8b, v31.8b
ret
Bootstrapped and tested on aarch64-none-linux-gnu.
Signed-off-
recently added splitter for vector
rotates.
Bootstrapped and tested on aarch64-none-linux-gnu.
Signed-off-by: Kyrylo Tkachov
gcc/
* config/aarch64/aarch64-protos.h (aarch64_emit_opt_vec_rotate):
Declare prototype.
* config/aarch64/aarch64.cc (aarch64_emit_opt_vec_rotate
lf-tests in this
patch to validate the transformation.
Bootstrapped and tested on aarch64-none-linux-gnu.
Ok for mainline?
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
PR target/117048
* simplify-rtx.cc (extract_ashift_operands_p): Define.
(simplif
> On 17 Oct 2024, at 22:32, Victor Do Nascimento
> wrote:
>
> FWIW, I definitely agree about the spuriousness of the V2DI mode check.
> While I can't approve, I can confirm it looks good.
Thanks for looking at it Victor.
The patch is ok.
Kyrill
>
> Thanks,
> Victor.
>
> On 10/17/24 16:10,
Hi Eikansh
> On 16 Oct 2024, at 18:23, Eikansh Gupta wrote:
>
> The pattern `a rrotate (32-b)` should be optimized to `a lrotate b`.
> The same is also true for `a lrotate (32-b)`. It can be optimized to
> `a rrotate b`.
>
> This patch adds following patterns:
> a rrotate (32-b) -> a lrotate b
Hi Soumya
> On 17 Oct 2024, at 06:10, Soumya AR wrote:
>
> Hi Richard,
>
> Thanks for the feedback. I’ve updated the patch with the suggested change.
> Ok for mainline?
>
> Best,
> Soumya
>
> > On 14 Oct 2024, at 6:40 PM, Richard Sandiford
> > wrote:
> >
> > External email: Use caution ope
d tested on aarch64-none-linux-gnu.
As with patch [2/3] interested in feedback on the approach.
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
gcc/
* config/aarch64/aarch64-protos.h (aarch64_emit_opt_vec_rotate):
Declare prototype.
* config/aarch64/aarch64.cc (a
on aarch64-none-linux-gnu.
Interested in feedback on the approach, but this needs patch [1/3] before this
has effect.
Signed-off-by: Kyrylo Tkachov
gcc/
PR target/117048
* config/aarch64/aarch64-simd.md (*aarch64_simd_rotate_imm):
New define_insn_and_split.
gcc/testsui
needs some extra AArch64 backend work, but I've added self-tests in this
patch to validate the transformation.
Bootstrapped and tested on aarch64-none-linux-gnu
Ok for mainline?
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
PR target/117048
* simplify-r
> On 14 Oct 2024, at 15:28, Ricardo Jesus wrote:
>
> External email: Use caution opening links or attachments
>
>
> This patch modifies the implementation of the vectorized mersenne
> twister random number generator to use __builtin_shufflevector instead
> of __builtin_shuffle. This makes it
Hi Tamar,
> On 14 Oct 2024, at 12:56, Tamar Christina wrote:
>
> External email: Use caution opening links or attachments
>
>
> Hi All,
>
> In this patch series I'm adding support for zero extending using permutes
> instead of requiring multi-step decomposition.
>
> This codegen has the bene
> On 11 Oct 2024, at 12:28, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Kyrylo Tkachov writes:
>> Hi all,
>>
>> In the testcase from patch [2/2] we want to match a vector rotate operation
>> from
>&
> On 11 Oct 2024, at 12:36, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Kyrylo Tkachov writes:
>> The pattern for the Advanced SIMD XAR instruction isn't very
>> optimization-friendly at the moment.
>>
Hi Jennifer,
> On 11 Oct 2024, at 10:00, Jennifer Schmitz wrote:
>
>
>
>> On 8 Oct 2024, at 10:44, Richard Biener wrote:
>>
>> External email: Use caution opening links or attachments
>>
>>
>> On Thu, 3 Oct 2024, Jennifer Schmitz wrote:
>>
>>>
>>>
On 1 Oct 2024, at 14:27, Richard B
t one XAR instruction.
Bootstrapped and tested on aarch64-none-linux-gnu.
I’ll push it after patch approval of [1/2] leaving some time for comments.
I’ll note that the SVE2 patterns for XAR should also be improved in a similar
but that is a separate patch.
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkac
x-gnu.
Ok for mainline?
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
PR target/117048
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
Handle vector constants in (x << C1) | (x >> C2) -> ROTATE
simplification.
0001-PR-117048-simp
> On 9 Oct 2024, at 17:35, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Tamar Christina writes:
>> Hi Richard,
>>
>>> -Original Message-
>>> From: Richard Sandiford
>>> Sent: Wednesday, October 9, 2024 12:58 PM
>>> To: gcc-patches@gcc
> On 8 Oct 2024, at 11:57, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Christophe Lyon writes:
>> On Fri, 4 Oct 2024 at 10:00, Kyrylo Tkachov wrote:
>>>
>>>
>>>
>>
Hi Richard,
> On 1 Oct 2024, at 13:35, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Kyrylo Tkachov writes:
>> Hi all,
>> I'd like to use a value of 64 bytes for the L1 cache size for Armv9-A
>
Hi Andre,
> On 2 Oct 2024, at 19:13, Andre Vieira wrote:
>
> External email: Use caution opening links or attachments
>
>
> As per the AArch64 ISA FEAT_SME does not require FEAT_SVE2, so we are removing
> that false dependency in GCC. However, we chose for now to not support this
> combinatio
Hi Andre,
> On 2 Oct 2024, at 19:13, Andre Vieira wrote:
>
> External email: Use caution opening links or attachments
>
>
> This patch series removes the requirement of SVE2 for SME, so when a user
> passes +sme, SVE2 is not enabled as a result of that.
> We do this to be compliant with the IS
> On 3 Oct 2024, at 21:44, Christophe Lyon wrote:
>
> External email: Use caution opening links or attachments
>
>
> When --enable-werror is enabled when running the top-level configure,
> it passes --enable-werror-always to subdirs. Some of them, like
> libgcc, ignore it.
>
> This patch ad
> On 3 Oct 2024, at 21:44, Christophe Lyon wrote:
>
> External email: Use caution opening links or attachments
>
>
> Add prototypes for __init_cpu_features_resolver and
> __init_cpu_features to avoid warnings due to -Wmissing-prototypes.
>
>libgcc/
>* config/aarch64/cpuinfo.
> On 3 Oct 2024, at 21:44, Christophe Lyon wrote:
>
> External email: Use caution opening links or attachments
>
>
> Since
> Commit c608ada288ced0268c1fd4136f56c34b24d4
> Author: Zac Walker
> CommitDate: 2024-01-23 15:32:30 +
>
> Ifdef `.hidden`, `.type`, and `.size` pseudo
> On 3 Oct 2024, at 16:41, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Soumya AR writes:
>> From 7fafcb5e0174c56205ec05406c9a412196ae93d3 Mon Sep 17 00:00:00 2001
>> From: Soumya AR
>> Date: Thu, 3 Oct 2024 11:53:07 +0530
>> Subject: [PATCH] a
uesday, October 1, 2024 12:20 PM
>>> To: Jennifer Schmitz
>>> Cc: gcc-patches@gcc.gnu.org; Kyrylo Tkachov
>>> Subject: Re: [PATCH] [PR113816] AArch64: Use SVE bit op reduction for vector
>>> reductions
>>>
>>> Jennifer Schmitz writes:
>
> On 12 Sep 2024, at 16:43, Eric Gallager wrote:
>
>
>
> On Wed, Sep 11, 2024 at 11:51 AM Srinath Parvathaneni
> wrote:
>>
>> This patch adds support for aarch64 gcs build attributes.
>
> Hi, just wondering if you could clarify what "GCS" stands for in this
> context? When I see it, my fir
> On 1 Oct 2024, at 09:48, Tamar Christina wrote:
>
> External email: Use caution opening links or attachments
>
>
> Hi Soumya,
>
> Nice patch!
>
>> -----Original Message-
>> From: Kyrylo Tkachov
>> Sent: Tuesday, October 1, 2024
Hi Soumya
> On 30 Sep 2024, at 18:26, Soumya AR wrote:
>
> External email: Use caution opening links or attachments
>
>
> This patch uses the FSCALE instruction provided by SVE to implement the
> standard ldexp family of functions.
>
> Currently, with '-Ofast -mcpu=neoverse-v2', GCC generates
Hi all,
I'd like to use a value of 64 bytes for the L1 cache size for Armv9-A
generic tuning.
As described in g:9a99559a478111f7fbeec29bd78344df7651c707 this value is used
to set the std::hardware_destructive_interference_size value which we want to
be not overly large when running concurrent appli
> On 19 Sep 2024, at 15:39, Claudio Bantaloukas
> wrote:
>
> External email: Use caution opening links or attachments
>
>
> On 9/19/2024 2:18 PM, Kyrylo Tkachov wrote:
>> Hi Claudio,
>>
>>> On 19 Sep 2024, at 15:09, Claudio Bantaloukas
>&
Hi Claudio,
> On 19 Sep 2024, at 15:09, Claudio Bantaloukas
> wrote:
>
> External email: Use caution opening links or attachments
>
>
> The ACLE defines a new scalar type, __mfp8. This is an opaque 8bit types that
> can only be used by fp8 intrinsics. Additionally, the mfloat8_t type is made
> On 17 Sep 2024, at 10:52, Richard Biener wrote:
>
> External email: Use caution opening links or attachments
>
>
> On Tue, Sep 17, 2024 at 9:57 AM Kyrylo Tkachov wrote:
>>
>>
>>
>>> On 16 Sep 2024, at 16:32, Richard Sandiford
>>&g
> On 16 Sep 2024, at 16:32, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> "Pengxuan Zheng (QUIC)" writes:
>>> On Thu, Sep 12, 2024 at 2:53 AM Pengxuan Zheng
>>> wrote:
SVE's INDEX instruction can be used to populate vectors by values
Hi Soumya,
> On 16 Sep 2024, at 10:51, Soumya AR wrote:
>
>
>
>> On 12 Sep 2024, at 7:22 PM, Richard Sandiford
>> wrote:
>>
>> External email: Use caution opening links or attachments
>>
>>
>> Richard Biener writes:
>>> On Thu, Sep 12, 2024 at 2:35 PM Richard Sandiford
>>> wrote:
l
Signed-off-by: Kyrylo Tkachov
* config/aarch64/tuning_models/neoversev2.h (neoversev2_prefetch_tune):
Define.
(neoversev2_tunings): Use it.
0001-aarch64-Define-l1_cache_line_size-for-mcpu-neoverse-.patch
Description: 0001-aarch64-Define-l1_cache_line_size-for-mcpu-neoverse-.patch
Hi Saurabh,
Not a full review, just something I noticed.
> On 13 Sep 2024, at 11:06, saurabh@arm.com wrote:
>
> External email: Use caution opening links or attachments
>
>
> The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and
> mandatory from Armv9.5-a. It introduces instru
Hi Saurabh,
> On 13 Sep 2024, at 11:06, saurabh@arm.com wrote:
>
> External email: Use caution opening links or attachments
>
>
> The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and
> mandatory from Armv9.5-a. It introduces instructions for computing the
> floating point abso
Hi Srinath,
Not a full review, just some things that popped out to me.
> On 11 Sep 2024, at 17:50, Srinath Parvathaneni
> wrote:
>
> External email: Use caution opening links or attachments
>
>
> This patch adds support for aarch64 gcs build attributes. This support
> includes generating two
> On 9 Sep 2024, at 11:06, Tamar Christina wrote:
>
> External email: Use caution opening links or attachments
>
>
>> -Original Message-
>> From: Richard Sandiford
>> Sent: Monday, September 9, 2024 9:29 AM
>> To: Tamar Christina
>> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnsha
> On 6 Sep 2024, at 16:00, Jakub Jelinek wrote:
>
> External email: Use caution opening links or attachments
>
>
> On Fri, Sep 06, 2024 at 01:46:01PM +, Jennifer Schmitz wrote:
>> In the pattern X - (X / Y) * Y to X % Y, this patch guards the
>> simplification for vector types by a check
Hi Tamar,
> On 6 Sep 2024, at 14:56, Tamar Christina wrote:
>
> External email: Use caution opening links or attachments
>
>
> Hi All,
>
> Because the vect_recog_bool_pattern can at the moment still transition
> out of GIMPLE and back into GENERIC the vect_recog_cond_store_pattern can
> end
Hi Andrew,
> On 3 Sep 2024, at 20:11, Andrew Pinski wrote:
>
> External email: Use caution opening links or attachments
>
>
> This moves the check for # of statements to copy in join to
> be the first check. This check is the cheapest check so it
> should be first. Plus add a print to the dump
Hi Evgeny,
> On 2 Sep 2024, at 15:03, Evgeny Karpov wrote:
>
> External email: Use caution opening links or attachments
>
>
> The patch resolves compilation issues for the C++ language. Previous
> patch series contributed to C++ as well, however, C++ could not be
> tested until we got a C++ co
Hi Saurabh,
> On 29 Aug 2024, at 09:51, saurabh@arm.com wrote:
>
> External email: Use caution opening links or attachments
>
>
> The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and
> mandatory from Armv9.5-a. It introduces instructions for computing the
> floating point abso
> On 28 Aug 2024, at 10:27, Tamar Christina wrote:
>
> External email: Use caution opening links or attachments
>
>
>> -Original Message-
>> From: Kyrylo Tkachov
>> Sent: Wednesday, August 28, 2024 8:55 AM
>> To: Tamar Christina
>> Cc:
> On 28 Aug 2024, at 11:22, saurabh@arm.com wrote:
>
> External email: Use caution opening links or attachments
>
>
> The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and
> mandatory from Armv9.5-a. It introduces instructions for computing the
> floating point absolute maxim
> On 28 Aug 2024, at 11:04, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Tamar Christina writes:
>>> The patch was bootstrapped and regtested on aarch64-linux-gnu:
>>> No problems bootstrapping, but several test files (in aarch64-sve.exp
d
>> Sent: Tuesday, August 27, 2024 11:46 AM
>> To: Tamar Christina
>> Cc: Jennifer Schmitz ; gcc-patches@gcc.gnu.org; Kyrylo
>> Tkachov
>> Subject: Re: [RFC][PATCH] AArch64: Remove
>> AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
>>
>> Tamar Christi
> On 28 Aug 2024, at 06:33, Andrew Pinski wrote:
>
> External email: Use caution opening links or attachments
>
>
> While looking into some popcount related I noticed that the popcount
> cost is not modeled at all. This adds both the vector and scalar (for CSSC)
> costs. For CSSC, we default
Hi Jennifer,
> On 22 Aug 2024, at 08:59, Jennifer Schmitz wrote:
>
> On 21 Aug 2024, at 16:03, Richard Sandiford wrote:
>>
>> External email: Use caution opening links or attachments
>>
>>
>> Kyrylo Tkachov writes:
>>>> On 20 Aug 2024,
> On 20 Aug 2024, at 17:44, saurabh@arm.com wrote:
>
> External email: Use caution opening links or attachments
>
>
> The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and
> mandatory from Armv9.5-a. It introduces instructions for computing the
> floating point absolute maxim
Hi Saurabh,
> On 20 Aug 2024, at 17:44, saurabh@arm.com wrote:
>
> External email: Use caution opening links or attachments
>
>
> The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and
> mandatory from Armv9.5-a. It introduces instructions for computing the
> floating point abso
> On 20 Aug 2024, at 20:10, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> The testcase contains a VNx2QImode pseudo that is live across a call
> and that cannot be allocated a call-preserved register. LRA quite
> reasonably tried to save it befo
> On 20 Aug 2024, at 19:11, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Jennifer Schmitz writes:
>> The param aarch64-autovec-preference=N is a useful tool for testing
>> auto-vectorisation in GCC as it allows the user to force a particular
>>
Hi Richard,
> On 19 Aug 2024, at 14:57, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Jennifer Schmitz writes:
>> This patch implements constant folding for svdiv. A new gimple_folder
>> method was added that uses const_binop to fold binary operat
> On 12 Aug 2024, at 17:24, Tamar Christina wrote:
>
> External email: Use caution opening links or attachments
>
>
>> -Original Message-
>> From: Kyrylo Tkachov
>> Sent: Monday, August 12, 2024 3:54 PM
>> To: Tamar Christina
>> Cc: G
> On 15 Aug 2024, at 18:48, Andrew Carlotti wrote:
>
> External email: Use caution opening links or attachments
>
>
> On Thu, Aug 15, 2024 at 05:15:03PM +0100, Richard Sandiford wrote:
>> Andrew Carlotti writes:
>>> This series of patches fixes issues with some intrinsics being incorrectly
>
t;> On 6 Aug 2024, at 4:14 PM, Richard Sandiford
>>> wro>> Kyrylo Tkachov writes:
>>>>> On 5 Aug 2024, at 18:00, Richard Sandiford
>>>>> wro>>>> Kyrylo Tkachov writes:
>>>>>>> On 5 Aug 2024,
Hi Tamar,
> On 12 Aug 2024, at 16:48, Tamar Christina wrote:
>
> External email: Use caution opening links or attachments
>
>
> Hi Kyrill,
>
>> -Original Message-----
>> From: Kyrylo Tkachov
>> Sent: Monday, August 12, 2024 3:07 PM
>> To:
meone else.
Tamar, Richard, does the reasoning above make sense to you?
I know that FMA reassociation is something we’ve gone back and forth on in the
backend…
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
gcc/ChangeLog:
* config/aarch64/tuning_models/neoversev2.h (fp_reassoc_
> On 9 Aug 2024, at 19:02, Vladimir Makarov wrote:
>
> External email: Use caution opening links or attachments
>
>
> On 8/9/24 08:58, Surya Kumari Jangala wrote:
>> I am looking into this failure.
>>
> Sorry for delay with this email. I was on vacation.
>
> I believe your should reverse t
> On 7 Aug 2024, at 17:11, saurabh@arm.com wrote:
>
> External email: Use caution opening links or attachments
>
>
> The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and
> mandatory from Armv9.5-a. It introduces instructions for computing the
> floating point absolute maximu
-none-linux-gnu.
I’ll leave it up for comments for a few days and commit next week if no
objections.
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md
(aarch64_simd_imm_shl): Rewrite to new
syntax. Add =w,w,vs1 altern
ll
Signed-off-by: Kyrylo Tkachov
gcc/ChangeLog:
* config/aarch64/constraints.md (Dm): Match CONSTM1_RTX rather
CONST1_RTX.
0001-aarch64-Check-CONSTM1_RTX-in-definition-of-Dm-constr.patch
Description: 0001-aarch64-Check-CONSTM1_RTX-in-definition-of-Dm-constr.patch
Hi Saurabh,
> On 7 Aug 2024, at 17:11, saurabh@arm.com wrote:
>
> External email: Use caution opening links or attachments
>
>
> The AArch64 FEAT_FAMINMAX extension is optional from Armv9.2-a and
> mandatory from Armv9.5-a. It introduces instructions for computing the
> floating point absolute
> On 6 Aug 2024, at 12:44, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Kyrylo Tkachov writes:
>>> On 5 Aug 2024, at 18:00, Richard Sandiford
>>> wrote:
>>>
>>> External email: Use cau
> On 5 Aug 2024, at 18:00, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Kyrylo Tkachov writes:
>>> On 5 Aug 2024, at 12:01, Richard Sandiford
>>> wrote:
>>>
>>> External email: Use cauti
> On 5 Aug 2024, at 18:00, Richard Sandiford wrote:
>
> External email: Use caution opening links or attachments
>
>
> Kyrylo Tkachov writes:
>>> On 5 Aug 2024, at 12:01, Richard Sandiford
>>> wrote:
>>>
>>> External email: Use cauti
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