On 2021/6/12 04:16, Segher Boessenkool wrote:
On Thu, Jun 10, 2021 at 03:11:08PM +0800, Xionghu Luo wrote:
On 2021/6/10 00:24, Segher Boessenkool wrote:
"!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed && !TARGET_P9_VECTOR
&& !altivec_indexed_or_indirect_operand (operands[0],
On Thu, Jun 10, 2021 at 03:11:08PM +0800, Xionghu Luo wrote:
> On 2021/6/10 00:24, Segher Boessenkool wrote:
> >>"!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed &&
> >> !TARGET_P9_VECTOR
> >> && !altivec_indexed_or_indirect_operand (operands[0], mode)"
> >>[(const_int 0)]
> >> {
On 2021/6/10 00:24, Segher Boessenkool wrote:
> On Wed, Jun 09, 2021 at 11:20:20AM +0800, Xionghu Luo wrote:
>> On 2021/6/9 04:11, Segher Boessenkool wrote:
>>> On Fri, Jun 04, 2021 at 09:40:58AM +0800, Xionghu Luo wrote:
>> rejecting combination of insns 6 and 7
>> original costs 4 + 4
On Wed, Jun 09, 2021 at 11:20:20AM +0800, Xionghu Luo wrote:
> On 2021/6/9 04:11, Segher Boessenkool wrote:
> > On Fri, Jun 04, 2021 at 09:40:58AM +0800, Xionghu Luo wrote:
> rejecting combination of insns 6 and 7
> original costs 4 + 4 = 8
> replacement cost 12
> >>>
> >>> So what
On 2021/6/9 04:11, Segher Boessenkool wrote:
> Hi!
>
> On Fri, Jun 04, 2021 at 09:40:58AM +0800, Xionghu Luo wrote:
Combine still fail to merge the two instructions:
Trying 6 -> 7:
6: r120:KF#0=r125:KF#0<-<0x40
REG_DEAD r125:KF
7:
Hi!
On Fri, Jun 04, 2021 at 09:40:58AM +0800, Xionghu Luo wrote:
> >> Combine still fail to merge the two instructions:
> >>
> >> Trying 6 -> 7:
> >> 6: r120:KF#0=r125:KF#0<-<0x40
> >>REG_DEAD r125:KF
> >> 7: [sfp:DI+r123:DI]=r120:KF#0<-<0x40
> >>REG_DEAD r120:KF
> >>
On 2021/6/4 04:16, Segher Boessenkool wrote:
> Hi!
>
> On Thu, Jun 03, 2021 at 08:46:46AM +0800, Xionghu Luo wrote:
>> On 2021/6/3 06:20, Segher Boessenkool wrote:
>>> On Wed, Jun 02, 2021 at 03:19:32AM -0500, Xionghu Luo wrote:
On P8LE, extra rot64+rot64 load or store instructions are
Hi,
On 2021/6/3 21:09, Bill Schmidt wrote:
> On 6/2/21 7:46 PM, Xionghu Luo wrote:
>> Hi,
>>
>> On 2021/6/3 06:20, Segher Boessenkool wrote:
>>> On Wed, Jun 02, 2021 at 03:19:32AM -0500, Xionghu Luo wrote:
On P8LE, extra rot64+rot64 load or store instructions are generated
in float128
On 2021/6/4 04:31, Segher Boessenkool wrote:
> On Thu, Jun 03, 2021 at 02:49:15PM +0800, Xionghu Luo wrote:
>> If remove the rotate in simplify-rtx like below:
>>
>> +++ b/gcc/simplify-rtx.c
>> @@ -3830,10 +3830,16 @@ simplify_context::simplify_binary_operation_1
>> (rtx_code code,
>>
On 6/3/21 3:19 PM, Segher Boessenkool wrote:
On Thu, Jun 03, 2021 at 08:09:36AM -0500, Bill Schmidt wrote:
Note also that swap optimization can handle more general cases than
simplify-rtx.
Do you have examples? That should be fixed (unless it is something
Power-specific?)
It is
On Thu, Jun 03, 2021 at 02:49:15PM +0800, Xionghu Luo wrote:
> If remove the rotate in simplify-rtx like below:
>
> +++ b/gcc/simplify-rtx.c
> @@ -3830,10 +3830,16 @@ simplify_context::simplify_binary_operation_1
> (rtx_code code,
> case ROTATE:
>if (trueop1 == CONST0_RTX (mode))
>
On Thu, Jun 03, 2021 at 08:09:36AM -0500, Bill Schmidt wrote:
> Note also that swap optimization can handle more general cases than
> simplify-rtx.
Do you have examples? That should be fixed (unless it is something
Power-specific?)
> In my view it's best to have it covered in both places.
Oh
Hi!
On Thu, Jun 03, 2021 at 08:46:46AM +0800, Xionghu Luo wrote:
> On 2021/6/3 06:20, Segher Boessenkool wrote:
> > On Wed, Jun 02, 2021 at 03:19:32AM -0500, Xionghu Luo wrote:
> >> On P8LE, extra rot64+rot64 load or store instructions are generated
> >> in float128 to vector __int128 conversion.
On 6/2/21 7:46 PM, Xionghu Luo wrote:
Hi,
On 2021/6/3 06:20, Segher Boessenkool wrote:
On Wed, Jun 02, 2021 at 03:19:32AM -0500, Xionghu Luo wrote:
On P8LE, extra rot64+rot64 load or store instructions are generated
in float128 to vector __int128 conversion.
This patch teaches pass swaps to
On 2021/6/3 08:46, Xionghu Luo via Gcc-patches wrote:
> Hi,
>
> On 2021/6/3 06:20, Segher Boessenkool wrote:
>> On Wed, Jun 02, 2021 at 03:19:32AM -0500, Xionghu Luo wrote:
>>> On P8LE, extra rot64+rot64 load or store instructions are generated
>>> in float128 to vector __int128 conversion.
Hi,
On 2021/6/3 06:20, Segher Boessenkool wrote:
> On Wed, Jun 02, 2021 at 03:19:32AM -0500, Xionghu Luo wrote:
>> On P8LE, extra rot64+rot64 load or store instructions are generated
>> in float128 to vector __int128 conversion.
>>
>> This patch teaches pass swaps to also handle such pattens to
On Wed, Jun 02, 2021 at 03:19:32AM -0500, Xionghu Luo wrote:
> On P8LE, extra rot64+rot64 load or store instructions are generated
> in float128 to vector __int128 conversion.
>
> This patch teaches pass swaps to also handle such pattens to remove
> extra swap instructions.
Did you check if this
On P8LE, extra rot64+rot64 load or store instructions are generated
in float128 to vector __int128 conversion.
This patch teaches pass swaps to also handle such pattens to remove
extra swap instructions.
(insn 7 6 8 2 (set (subreg:V1TI (reg:KF 123) 0)
(rotate:V1TI (mem/u/c:V1TI (reg/f:DI
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