Am Mittwoch, den 26.07.2006, 06:43 + schrieb Jim Strother:
> I've just started using geda, I actually gave it a shot once before
> but gave up when the install hit bumps. This time I pushed
> through these bumps and have something that sort of works.
> Anyway, I thought that I would share my e
I've just started using geda, I actually gave it a shot once before
but gave up when the install hit bumps. This time I pushed
through these bumps and have something that sort of works.
Anyway, I thought that I would share my experience and ask
if this was representative:
First, after digging ar
I added the ability to specify mouse actions in pcb-menu.res for the
lesstif HID. I copied the current mappings, which now look like this:
Mouse =
{
Left = {
Mode(Notify)
up = Mode(Release)
}
Right = {
}
Middle = {
Pan(1)
up = Pan(0)
ctrl = Pan(thumb,1)
ctrl-up
Ok, no changes needed. Here's a sample script that panelizes a
900x600 board, assuming you have a pre-existing board named
"panel.pcb" that's the right size and everything, and have removed the
Cursor line in the input files, this script panelizes seven copies of
smd-dil.pcb onto it:
---
> This time I am open to suggestions.
"Load layout data to paste-buffer"
Lets you paste whole boards onto other boards.
Now, if someone wanted to add a paste-at action, you could script the
whole panelization process. Although the load operation leaves the
cursor at the saved cursor position,
I need to take 6 small pcb's and create a single panel (I'm cheap).
Last time I used the brute force of:
1. load the pcb file
2. Create a symbol of the individual design
3. Cut, paste & rotate.
This time I am open to suggestions.
Thanks,
George
__
> Stuart Brorson wrote:
> > As the subject line says -- I am using Icarus Verilog 0.8.2. I am
> > getting bad results using the modulo operator for reals. Here's an
> > example:
[ snip! ]
>
> It turns out that *verilog* does not support % on reals. So
> the bug in 0.8 is to not give an error
Art Fore wrote:
Also, can you do cross-probing between the schematic and layout?
Cross-probing, if you don't know, is where you have both the schematic
and layout open on the screen and they are linked so if you highlight a
net or component on the schemtic, it is highlighted in the layout and
vi
[EMAIL PROTECTED] wrote:
>
> Works fine for me -- same gerbv, also on AMD64.
> I tried your test Gerber output, so it's not pcb's problem.
>
> $ ldd /usr/bin/gerbv | wc -l
> 32
>
> ... so it's probably something in there. This computer
> is Debian (sid), so its library infrastructure is probably
>
I cannot reproduce the tutorial pcb. Are the .pcb and .net files from
gsch2pcb available? If not, can someone post them?
tomdean
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On Tue, Jul 25, 2006 at 11:52:59AM +0200, Stefan Salewski wrote:
> I have the same problem, using geda shipped with gentoo-linux
> (AMD64):
> [EMAIL PROTECTED] ~ $ gerbv --version
> gerbv version 1.0.1
> (C) Stefan Petersen ([EMAIL PROTECTED])
Works fine for me -- same gerbv, also on AMD64.
I tr
Hi,
I am wondering why gnetlist gives warning if an output pintype is connected to
input/output pintype...
WARNING: Pin(s) with pintype 'output': U1:146 '
to pin(s) with pintype 'input/output': U22:12
Levente
--
http://web.interware.hu/lekovacs
pgpFenNCywqqu.pgp
Description: PGP sign
antonio bergnoli wrote:
# To: [EMAIL PROTECTED]
# Subject: gEDA-user: line thickness not shown in gerbv
# From: antonio bergnoli <[EMAIL PROTECTED]>
# Date: Tue, 07 Mar 2006 13:23:37 +0100
> i noticed that using gerbv to display gerber files (generated
>with pcb) the lines are shown without their
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