[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it

== Series Details == Series: series starting with [1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it URL : https://patchwork.freedesktop.org/series/38744/ State : warning == Summary == $ dim checkpatch origin/drm-tip b28837aa5cbe drm/i915: Add enum aux_ch and clean up the

[Intel-gfx] [PATCH igt v3] Iterate over physical engines

We current have a single for_each_engine() iterator which we use to generate both a set of uABI engines and a set of physical engines. Determining what uABI ring-id corresponds to an actual HW engine is tricky, so pull that out to a library function and introduce for_each_physical_engine() for

Re: [Intel-gfx] [PATCH 1/2] drm/i915/guc: Support engine busy stats

Quoting Tvrtko Ursulin (2018-02-22 06:07:32) > From: Tvrtko Ursulin > > Place context in/out hooks into the GuC backend, when contexts are > assigned to ports, and removed from them, in order to be able to > provide engine busy stats in GuC mode. > > Signed-off-by:

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: GuC test run (rev4)

== Series Details == Series: drm/i915: GuC test run (rev4) URL : https://patchwork.freedesktop.org/series/38615/ State : failure == Summary == Test kms_flip: Subgroup modeset-vs-vblank-race: fail -> PASS (shard-hsw) fdo#103060 +1 Test perf: Subgroup

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it

On Wed, 2018-02-21 at 23:28 -0800, Dhinakaran Pandiyan wrote: > From: Ville Syrjälä > > Since we no longer have a 1:1 correspondence between ports and AUX > channels, let's give AUX channels their own enum. Makes it easier > to tell the apples from the oranges, and

[Intel-gfx] [PATCH 2/2] drm/i915/cnl: New power domain for AUX IO.

PSR on CNL requires AUX IO wells to be kept on and the existing AUX domain for AUX-A enables DC_OFF well too. This is not required, so add a new AUX_IO_A domain for AUX-A to allow DC states to remain enabled. Other AUX channels re-use the existing AUX domains as they do need power well 2. v2: Add

[Intel-gfx] [PATCH 1/2] drm/i915: Add enum aux_ch and clean up the aux init to use it

From: Ville Syrjälä Since we no longer have a 1:1 correspondence between ports and AUX channels, let's give AUX channels their own enum. Makes it easier to tell the apples from the oranges, and we get rid of the port E AUX power domain FIXME since we now derive the

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

On Tue, 2018-02-20 at 11:31 -0800, Rodrigo Vivi wrote: > On Tue, Feb 20, 2018 at 07:05:22PM +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Since we no longer have a 1:1 correspondence between ports and AUX > > channels, let's give AUX channels their

Re: [Intel-gfx] [PULL] git-fixes for 4.16-rc2

Quoting Zhenyu Wang (2018-02-22 03:13:19) > On 2018.02.20 20:15:22 +, Chris Wilson wrote: > > Quoting Zhenyu Wang (2018-02-14 05:28:27) > > > > > > Hi, here's current gvt-fixes pull for 4.16-rc2, as it is close for > > > chinese new year, team would take one week off at least, so like to > >

Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Nuke aux regs from intel_dp

On Tue, 2018-02-20 at 21:00 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Just store function pointers that give us the correct register offsets > instead of storing the register offsets themselves. Slightly less > efficient perhaps but saves a few bytes

Re: [Intel-gfx] drm-intel-fixes issues on CI

Quoting Rodrigo Vivi (2018-02-22 04:26:29) > Hi guys, > > looking at gem_eio_flight* for gen9 on: > https://intel-gfx-ci.01.org/tree/drm-intel-fixes/shards.html > > run 246 x 247 > pure v4.16-rc2 x our fixes > > would any of 2 patches explain: > > drm/i915: Clear the in-use marker on execbuf

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2) URL : https://patchwork.freedesktop.org/series/38717/ State : success == Summary == Series 38717v2 series starting with [1/2] drm/i915/guc: Support engine busy stats

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/guc: Support engine busy stats (rev2) URL : https://patchwork.freedesktop.org/series/38717/ State : warning == Summary == $ dim checkpatch origin/drm-tip 690dfe054013 drm/i915/guc: Support engine busy stats -:33: WARNING: line

Re: [Intel-gfx] [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

Looks good to me. Few cosmetic changes suggested below. With those addressed: Reviewed-by: Sagar Arun Kamble On 2/22/2018 5:05 AM, Oscar Mateo wrote: In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the Video Enhancement engines (aka VEBOX, aka

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Add enum aux_ch and clean up the aux init to use it

On Tue, 2018-02-20 at 19:05 +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Since we no longer have a 1:1 correspondence between ports and AUX > channels, let's give AUX channels their own enum. Makes it easier > to tell the apples from the oranges, and we

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: GuC test run (rev4)

== Series Details == Series: drm/i915: GuC test run (rev4) URL : https://patchwork.freedesktop.org/series/38615/ State : success == Summary == Series 38615v4 drm/i915: GuC test run https://patchwork.freedesktop.org/api/1.0/series/38615/revisions/4/mbox/ Test kms_pipe_crc_basic:

[Intel-gfx] [PATCH 1/2] drm/i915/guc: Support engine busy stats

From: Tvrtko Ursulin Place context in/out hooks into the GuC backend, when contexts are assigned to ports, and removed from them, in order to be able to provide engine busy stats in GuC mode. Signed-off-by: Tvrtko Ursulin Testcase:

Re: [Intel-gfx] [PATCH 01/43] drm: hdcp2.2 authentication msg definitions

On Wednesday 14 February 2018 08:45 PM, Winkler, Tomas wrote: This patch defines the hdcp2.2 protocol messages for the HDCP2.2 authentication. Signed-off-by: Ramalingam C --- include/drm/drm_hdcp.h | 226 + 1 file

Re: [Intel-gfx] [PATCH 01/43] drm: hdcp2.2 authentication msg definitions

On Thursday 15 February 2018 01:10 AM, Jani Nikula wrote: On Wed, 14 Feb 2018, "Winkler, Tomas" wrote: This patch defines the hdcp2.2 protocol messages for the HDCP2.2 authentication. Signed-off-by: Ramalingam C --- include/drm/drm_hdcp.h

Re: [Intel-gfx] [PATCH 04/43] mei: me: add gemini lake devices ids

On Wednesday 14 February 2018 08:15 PM, Winkler, Tomas wrote: This one is already upstream Thanks for pointing that out. I will drop this patch. --Ram Thanks Tomas From: Tomas Winkler Signed-off-by: Tomas Winkler ---

[Intel-gfx] drm-intel-fixes issues on CI

Hi guys, looking at gem_eio_flight* for gen9 on: https://intel-gfx-ci.01.org/tree/drm-intel-fixes/shards.html run 246 x 247 pure v4.16-rc2 x our fixes would any of 2 patches explain: drm/i915: Clear the in-use marker on execbuf failure drm/i915: Fix rsvd2 mask when out-fence is returned

[Intel-gfx] ✗ Fi.CI.BAT: warning for ICL PLLs, DP/HDMI and misc display

== Series Details == Series: ICL PLLs, DP/HDMI and misc display URL : https://patchwork.freedesktop.org/series/38737/ State : warning == Summary == Series 38737v1 ICL PLLs, DP/HDMI and misc display https://patchwork.freedesktop.org/api/1.0/series/38737/revisions/1/mbox/ Test

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ICL PLLs, DP/HDMI and misc display

== Series Details == Series: ICL PLLs, DP/HDMI and misc display URL : https://patchwork.freedesktop.org/series/38737/ State : warning == Summary == $ dim checkpatch origin/drm-tip 176365bcdda2 drm/i915/icl: add definitions for the ICL PLL registers -:87: CHECK: Prefer using the BIT macro #87:

[Intel-gfx] [PATCH 16/17] drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes

And the DDI_A_4_LANES bit from DDI_BUF_CTL doesn't even exist anymore. This commit prevents us from auto picking a maximum of 2 lanes, which makes some panels useless by rejecting their only native mode. Thanks to Manasi for the help debugging this one. v2: Typo fix (Rodrigo). Cc: Manasi

[Intel-gfx] [PATCH 17/17] drm/i915/icl: Fix the DP Max Voltage for ICL

From: Manasi Navare On clock recovery this function is called to find out the max voltage swing level that we could go. However gen 9 functions use the old buffer translation tables to figure that out. ICL uses different set of tables for eDP and DP for both Combo and

[Intel-gfx] [PATCH 15/17] drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL

From: James Ausmus These fields have been deprecated and moved in ICL+. Stop setting the bits. They have moved to GAMMA_MODE and CSC_MODE, respectively. This patch is just to stop incorrectly setting bits in PLANE_COLOR_CTL while we're waiting for the new replacement

[Intel-gfx] [PATCH 05/17] drm/i915/icl: compute the MG PLL registers

This implements the "MG PLL Programming" sequence from our spec. The biggest problem was that the spec assumes real numbers, so we had to adjust some numbers and alculations due to the fact that the Kernel prefers to deal with integers. I recommend grabbing some coffee, a pen and paper before

[Intel-gfx] [PATCH 00/17] ICL PLLs, DP/HDMI and misc display

Hello Here are some more ICL patches, now with the Combo & MG PLLs, some DP/HDMI initialization code and a few misc fixes. Again, the R-B tags already present in some of the patches (including those form me) were given a long time ago, so they need to be re-issued due to the rebasing. Thanks,

[Intel-gfx] [PATCH 12/17] drm/i915/icl: HPD pin for port F

From: Dhinakaran Pandiyan Extend enum hpd_pin to port F so that we can start using this for ICL. v2: Rebase. Cc: Rodrigo Vivi Cc: Paulo Zanoni Signed-off-by: Dhinakaran Pandiyan

[Intel-gfx] [PATCH 14/17] drm/i915/icl: Calculate link clock using the new registers

From: Arkadiusz Hiler Start using the new registers for ICL and on. Cc: Manasi Navare Cc: Rodrigo Vivi Reviewed-by: Paulo Zanoni Signed-off-by: Arkadiusz Hiler

[Intel-gfx] [PATCH 11/17] drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI

From: Manasi Navare This sequence is used to setup voltage swing before enabling MG PHY DDI as well as for changing the voltage during DisplayPort Link training. For ICL, there are two types of DDIs. This sequence needs to be used for MG PHY DDI which is ports C-F.

[Intel-gfx] [PATCH 13/17] drm/i915/icl: Added 5k source scaling support for Gen11 platform

From: Nabendu Maiti Gen11 supports upto 5k source scaling v2: Re-factoring of code as per review v3: Corrected max Vertical size and indentation v4: Added max Vertical dst size in same patch Signed-off-by: Nabendu Maiti ---

[Intel-gfx] [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks

This commit introduces the definitions for the ICL clocks and adds the basic functions to the shared DPLL framework. It adds code for the Enable and Disable sequences for some PLLs, but it does not have the code to compute the actual PLL values, which are marked as TODO comments and should be

[Intel-gfx] [PATCH 03/17] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers

HDMI mode DPLL programming on ICL is the same as CNL, so just reuse the CNL code. v2: - Properly detect HDMI crtcs. - Rebase after changes to the cnl function (clock * 1000). Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 34

[Intel-gfx] [PATCH 08/17] drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI

From: Manasi Navare This is an important part of the DDI initalization as well as for changing the voltage during DisplayPort link training. The Voltage swing seqeuence is similar to Cannonlake. However it has different register definitions and hence it makes sense to

[Intel-gfx] [PATCH 01/17] drm/i915/icl: add definitions for the ICL PLL registers

There's a lot of code for the PLL enabling, so let's first only introduce the register definitions in order to make patch reviewing a little easier. v2: Coding style (Jani). v3: Preparation for upstreaming. Signed-off-by: Paulo Zanoni ---

[Intel-gfx] [PATCH 10/17] drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer

From: Manasi Navare This table is used for voltage swing programming sequence during DDI Buffer initialization for MG PHY DDI Buffers on Icelake. v2 (from Paulo): * Fix white space issues. Cc: Rodrigo Vivi Cc: Jani Nikula

[Intel-gfx] [PATCH 04/17] drm/i915/icl: compute the combo PHY (DPLL) DP registers

Just use the hardcoded tables provided by our spec. v2: Rebase. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 86 ++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git

[Intel-gfx] [PATCH 07/17] drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.

From: Manasi Navare These tables are used on voltage vswing sequence initialization on Icelake. The swing_sel on the spec's table is defined in a 4 bits binary like 1010. However the register bits are split in upper 1 bit swing_sel and lower 3 bits swing sel. In

[Intel-gfx] [PATCH 09/17] drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI

From: Manasi Navare On Icelake platform, MG PHY is used when operating in DP alternate mode or the legacy HDMI or DP modes. DDI Ports C, D, E, F are MG PHY DDI ports on ICL. This patch adds the necessary voltage swing programming related register definitions and

[Intel-gfx] [PATCH 06/17] drm/i915/icl: Add register definitions for Combo PHY vswing sequences.

From: Manasi Navare This patch defines register definitions required for ICL voltage vswing programming for Combo PHY DDI Ports. It uses the same bit definitions and macros as the CNL voltage swing sequences. v7: * Kill _MMIIO_PORT2_LN (Paulo) v6: * Replace some

Re: [Intel-gfx] [PULL] git-fixes for 4.16-rc2

On 2018.02.20 20:15:22 +, Chris Wilson wrote: > Quoting Zhenyu Wang (2018-02-14 05:28:27) > > > > Hi, here's current gvt-fixes pull for 4.16-rc2, as it is close for > > chinese new year, team would take one week off at least, so like to > > send this out before vacation. This has one to fix

Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane

> -Original Message- > From: Juha-Pekka Heikkila [mailto:juhapekka.heikk...@gmail.com] > Sent: Wednesday, February 21, 2018 7:52 PM > To: Srinivas, Vidya ; intel- > g...@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 13/16] drm/i915: Add NV12 as

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hsw: add missing disabled EUs registers reads (rev4)

== Series Details == Series: drm/i915/hsw: add missing disabled EUs registers reads (rev4) URL : https://patchwork.freedesktop.org/series/38441/ State : success == Summary == Test kms_flip: Subgroup 2x-dpms-vs-vblank-race: pass -> FAIL (shard-hsw)

Re: [Intel-gfx] [V4] drm/i915: Enable VBT based BL control for DP

Hi Ville, I already resubmit the patch https://patchwork.freedesktop.org/patch/205823/ diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 1868f73f730c..b9068bd1943f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -655,18

Re: [Intel-gfx] [PATCH 2/4] drm/i915/icl: Show interrupt registers in debugfs

On 20/02/18 07:37, Mika Kuoppala wrote: From: Tvrtko Ursulin Show GEN11 specific interrupt registers in debugfs v2: Update for POR changes. (Daniele Ceraolo Spurio) v3: get runtime pm ref. unify common parts with gen8 (Daniele) Cc: Ceraolo Spurio, Daniele

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Scanout fence fixes/cleanups (rev3)

== Series Details == Series: drm/i915: Scanout fence fixes/cleanups (rev3) URL : https://patchwork.freedesktop.org/series/38714/ State : success == Summary == Test drv_suspend: Subgroup fence-restore-untiled: skip -> PASS (shard-snb) Test kms_flip:

[Intel-gfx] ✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev6)

== Series Details == Series: ICL GEM enabling (v2) (rev6) URL : https://patchwork.freedesktop.org/series/38174/ State : failure == Summary == Applying: drm/i915/icl: Add the ICL PCI IDs Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/i915_pci.c M

Re: [Intel-gfx] [PATCH libdrm 1/2] intel: align reuse buffer's size on page size instead

On Wed, Feb 21, 2018 at 09:43:55PM +, Chris Wilson wrote: > Quoting James Xiong (2018-02-20 17:48:03) > > From: "Xiong, James" > > > > With gem_reuse enabled, when a buffer size is different than > > the sizes of buckets, it is aligned to the next bucket's size, > >

[Intel-gfx] [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also, each VDBOX and VEBOX has its own power well, which only exist if the related engine exists in the HW. Unfortunately, we have a Catch-22 situation

Re: [Intel-gfx] [PATCH] drm/i915: Check for I915_MODE_FLAG_INHERITED before drm_atomic_helper_check_modeset

Nice, this is a no-brainer Reviewed-by: Lyude Paul On Wed, 2018-02-21 at 10:28 +0100, Maarten Lankhorst wrote: > Moving the check upwards will mean we we no longer have to add planes > and connectors manually, because everything is handled correctly by >

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

On Wed, Feb 21, 2018 at 01:12:08PM -0800, Souza, Jose wrote: > On Wed, 2018-02-21 at 12:45 -0800, Rodrigo Vivi wrote: > > On Tue, Feb 20, 2018 at 06:23:47PM -0800, José Roberto de Souza > > wrote: > > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it > > > self, so lets use the

Re: [Intel-gfx] [PATCH 6/6] drm/i915: Add a FIXME about FBC vs. fence. 90/270 degree rotation

Quoting Ville Syrjala (2018-02-21 16:02:35) > From: Ville Syrjälä > > Currently the FBC code doesn't handle the 90/270 degree rotated case > correctly. We would need the GTT tracking to monitor the fence on the > normal GTT view (the rotated view doesn't even have

Re: [Intel-gfx] [PATCH 5/6] drm/i915: Extract intel_plane_{pin, unpin}_fb()

Quoting Ville Syrjala (2018-02-21 16:02:34) > From: Ville Syrjälä > > We've replicated the fb pin/unpin code in a few places. Pull it into > convenint helpers. > > Slight change in locking behaviour as intel_cleanup_plane_fb() now > grab struct_mutex

Re: [Intel-gfx] [PATCH 4/6] drm/i915: Require fence only for FBC capable planes

Quoting Ville Syrjala (2018-02-21 16:02:33) > From: Ville Syrjälä > > As only a subset of primary planes are FBC capable there's no need > to waste fences on all of them. So let's skip the fence if the plane > isn't even fbc capable. > > In the future we might

Re: [Intel-gfx] [PATCH v3 3/6] drm/i915: Clean up fbc vs. plane checks

Quoting Ville Syrjala (2018-02-21 17:31:01) > From: Ville Syrjälä > > Let's record the information whether a plane can do fbc or not under > struct inte_plane. > > v2: Rebase due to i9xx_plane_id > Handle BDW/HSW correctly > v3: Move inte_fbc_init() back since

[Intel-gfx] [PATCH v2 2/6] drm/i915: Only pin the fence for primary planes (and gen2/3)

From: Ville Syrjälä Currently we pin a fence on every plane doing tiled scanout. The number of planes we have available is fast apporaching the number of fences so we really should stop wasting them. Only FBC needs the fence on gen4+, so let's use fences only for

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Only pin the fence for primary planes (and gen2/3)

Quoting Ville Syrjala (2018-02-21 18:48:07) > From: Ville Syrjälä > > Currently we pin a fence on every plane doing tiled scanout. The > number of planes we have available is fast apporaching the number > of fences so we really should stop wasting them. Only FBC

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout

Quoting Ville Syrjala (2018-02-21 16:02:30) > From: Ville Syrjälä > > Gen2/3 display engine depends on the fence for tiled scanout. So if we > fail to get a fence fail the entire operation. > > Cc: Chris Wilson > Signed-off-by: Ville

Re: [Intel-gfx] [PATCH libdrm 1/2] intel: align reuse buffer's size on page size instead

Quoting James Xiong (2018-02-20 17:48:03) > From: "Xiong, James" > > With gem_reuse enabled, when a buffer size is different than > the sizes of buckets, it is aligned to the next bucket's size, > which means about 25% more memory than the requested is allocated > in the

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Remove the ring advancement under preemption

Quoting Michel Thierry (2018-02-21 17:25:54) > On 21/02/18 05:32, Chris Wilson wrote: > > Load an empty ringbuffer for preemption, ignoring the lite-restore > > workaround as we know the preempt context is always idle before preemption. > > > > True, injecting the preempt context shouldn't cause

Re: [Intel-gfx] [PATCH] drm/i915: Rename drm_i915_gem_request to i915_request

Quoting Joonas Lahtinen (2018-02-21 18:40:51) > Quoting Chris Wilson (2018-02-21 11:56:36) > > We want to de-emphasize the link between the request (dependency, > > execution and fence tracking) from GEM and so rename the struct from > > drm_i915_gem_request to i915_request. That is we may

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/hsw: add missing disabled EUs registers reads (rev4)

== Series Details == Series: drm/i915/hsw: add missing disabled EUs registers reads (rev4) URL : https://patchwork.freedesktop.org/series/38441/ State : success == Summary == Series 38441v4 drm/i915/hsw: add missing disabled EUs registers reads

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/execlists: Move the GEM_BUG_ON context matches CSB later

== Series Details == Series: drm/i915/execlists: Move the GEM_BUG_ON context matches CSB later URL : https://patchwork.freedesktop.org/series/38709/ State : failure == Summary == Test kms_plane_multiple: Subgroup legacy-pipe-b-tiling-none: skip -> PASS

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

On Wed, 2018-02-21 at 12:45 -0800, Rodrigo Vivi wrote: > On Tue, Feb 20, 2018 at 06:23:47PM -0800, José Roberto de Souza > wrote: > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it > > self, so lets use the mutex register that is available in gen9+ to > > avoid concurrent

[Intel-gfx] ✗ Fi.CI.IGT: warning for drm/atomic: Call ww_acquire_done after drm_modeset_lock_all

== Series Details == Series: drm/atomic: Call ww_acquire_done after drm_modeset_lock_all URL : https://patchwork.freedesktop.org/series/38711/ State : warning == Summary == Test kms_flip: Subgroup 2x-plain-flip-ts-check: pass -> FAIL (shard-hsw) fdo#100368

Re: [Intel-gfx] [PATCH igt 1/2] Iterate over physical engines

Quoting Tvrtko Ursulin (2018-02-21 16:25:34) > > On 21/02/2018 14:45, Chris Wilson wrote: > > We current have a single for_each_engine() iterator which we use to > > generate both a set of uABI engines and a set of physical engines. > > Determining what uABI ring-id corresponds to an actual HW

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

On Tue, Feb 20, 2018 at 06:23:47PM -0800, José Roberto de Souza wrote: > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it > self, so lets use the mutex register that is available in gen9+ to > avoid concurrent access by hardware and driver. > > Reference: >

[Intel-gfx] [PATCH v3] drm/i915/hsw: add missing disabled EUs registers reads

It turns out that HSW has a register that tells us how many EUs are disabled per half-slice (roughly a similar notion to subslice). We didn't read those registers so far as most userspace drivers didn't need those values prior to Gen8, but an internal library would like to have access to this.

[Intel-gfx] [PATCH igt v2] Iterate over physical engines

We current have a single for_each_engine() iterator which we use to generate both a set of uABI engines and a set of physical engines. Determining what uABI ring-id corresponds to an actual HW engine is tricky, so pull that out to a library function and introduce for_each_physical_engine() for

[Intel-gfx] [PATCH v4] drm/i915/hsw: add missing disabled EUs registers reads

It turns out that HSW has a register that tells us how many EUs are disabled per half-slice (roughly a similar notion to subslice). We didn't read those registers so far as most userspace drivers didn't need those values prior to Gen8, but an internal library would like to have access to this.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scanout fence fixes/cleanups (rev3)

== Series Details == Series: drm/i915: Scanout fence fixes/cleanups (rev3) URL : https://patchwork.freedesktop.org/series/38714/ State : warning == Summary == $ dim checkpatch origin/drm-tip ec43511e598e drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout a686f373992f drm/i915:

Re: [Intel-gfx] [PATCH v2 2/6] drm/i915: Only pin the fence for primary planes (and gen2/3)

On Wed, 21 Feb 2018 20:48:07 +0200 Ville Syrjala wrote: > From: Ville Syrjälä > > Currently we pin a fence on every plane doing tiled scanout. The > number of planes we have available is fast apporaching the number > of fences so we

[Intel-gfx] [PULL] drm-misc-next

Hi Dave, A delicious collection of fixes and features for you this week. The backlight helpers have been picked up by Lee Jones in the backlight tree, so hopefully no fireworks there. Everything else is business as usual. drm-misc-next-2018-02-21: drm-misc-next for 4.17: Cross-subsystem

Re: [Intel-gfx] [PATCH igt 1/2] Iterate over physical engines

Quoting Chris Wilson (2018-02-21 14:45:21) > diff --git a/tests/gem_sync.c b/tests/gem_sync.c > index d70515ea..788fafc3 100644 > --- a/tests/gem_sync.c > +++ b/tests/gem_sync.c > @@ -86,23 +86,9 @@ sync_ring(int fd, unsigned ring, int num_children, int > timeout) > int num_engines = 0; >

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Add a GEM_TRACE to show when the context is completed

== Series Details == Series: drm/i915/execlists: Add a GEM_TRACE to show when the context is completed URL : https://patchwork.freedesktop.org/series/38707/ State : success == Summary == Test kms_atomic_transition: Subgroup 1x-modeset-transitions-nonblocking-fencing:

Re: [Intel-gfx] [PATCH] drm/atomic: Call ww_acquire_done after drm_modeset_lock_all

On Wed, Feb 21, 2018 at 04:23:31PM +0100, Maarten Lankhorst wrote: > After we acquired all generic modeset locks in drm_modeset_lock_all, it's > unsafe acquire any other so just mark acquisition as done. > > Atomic drivers shouldn't use drm_modeset_lock_all. > > Signed-off-by: Maarten Lankhorst

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/guc: Support engine busy stats

== Series Details == Series: series starting with [1/2] drm/i915/guc: Support engine busy stats URL : https://patchwork.freedesktop.org/series/38717/ State : failure == Summary == Series 38717v1 series starting with [1/2] drm/i915/guc: Support engine busy stats

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Scanout fence fixes/cleanups (rev3)

== Series Details == Series: drm/i915: Scanout fence fixes/cleanups (rev3) URL : https://patchwork.freedesktop.org/series/38714/ State : success == Summary == Series 38714v3 drm/i915: Scanout fence fixes/cleanups https://patchwork.freedesktop.org/api/1.0/series/38714/revisions/3/mbox/ Test

Re: [Intel-gfx] [PATCH] drm/atomic: Call ww_acquire_done after drm_modeset_lock_all

On 2018-02-21 01:36 PM, Daniel Vetter wrote: > On Wed, Feb 21, 2018 at 04:23:31PM +0100, Maarten Lankhorst wrote: >> After we acquired all generic modeset locks in drm_modeset_lock_all, it's >> unsafe acquire any other so just mark acquisition as done. >> >> Atomic drivers shouldn't use

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: Support engine busy stats

== Series Details == Series: series starting with [1/2] drm/i915/guc: Support engine busy stats URL : https://patchwork.freedesktop.org/series/38717/ State : warning == Summary == $ dim checkpatch origin/drm-tip dc87ce86e08d drm/i915/guc: Support engine busy stats -:33: WARNING: line over 80

Re: [Intel-gfx] [PATCH] drm/i915: Rename drm_i915_gem_request to i915_request

Quoting Chris Wilson (2018-02-21 11:56:36) > We want to de-emphasize the link between the request (dependency, > execution and fence tracking) from GEM and so rename the struct from > drm_i915_gem_request to i915_request. That is we may implement the GEM > user interface on top of requests, but

Re: [Intel-gfx] [PATCH] drm/i915/hsw: add missing disabled EUs registers reads

Quoting Lionel Landwerlin (2018-02-16 17:31:01) > +static void haswell_sseu_info_init(struct drm_i915_private *dev_priv) > +{ > + struct intel_device_info *info = mkwrite_device_info(dev_priv); > + struct sseu_dev_info *sseu = >sseu; > + u32 fuse1; > + > + /* > +*

Re: [Intel-gfx] [PATCH] drm/doc: Fix documentation for _vblank_restore().

On Tue, Feb 20, 2018 at 11:39:08PM -0800, Dhinakaran Pandiyan wrote: > No code changes, fixes doc build warnings and polish some doc text. > > Reported-by: Daniel Vetter > Cc: Rodrigo Vivi > Cc: Daniel Vetter >

[Intel-gfx] ✗ Fi.CI.BAT: warning for lib: Skip aliased bsd ABI ring if bsd2 is available (rev2)

== Series Details == Series: lib: Skip aliased bsd ABI ring if bsd2 is available (rev2) URL : https://patchwork.freedesktop.org/series/38690/ State : warning == Summary == IGT patchset tested on top of latest successful build 960e55a87d7b7d7385063e37cc9f281df2be8037 igt/gem_ctx_isolation:

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Scanout fence fixes/cleanups (rev2)

== Series Details == Series: drm/i915: Scanout fence fixes/cleanups (rev2) URL : https://patchwork.freedesktop.org/series/38714/ State : failure == Summary == Series 38714v2 drm/i915: Scanout fence fixes/cleanups https://patchwork.freedesktop.org/api/1.0/series/38714/revisions/2/mbox/ Test

Re: [Intel-gfx] [PATCH 00/16] Adding NV12 support

Op 21-02-18 om 11:20 schreef Vidya Srinivas: > This patch series is adding NV12 support for Broxton display after rebasing on > latest drm-tip. > Initial series of the patches can be found here: > https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html > > Previous revision history:

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Remove the ring advancement under preemption

== Series Details == Series: drm/i915/execlists: Remove the ring advancement under preemption URL : https://patchwork.freedesktop.org/series/38698/ State : success == Summary == Test kms_pipe_crc_basic: Subgroup read-crc-pipe-c-frame-sequence: fail -> PASS

[Intel-gfx] Updated drm-intel-testing

Hi all, Mostly fixes in this tag. QA/testing could emphasis on CNL hardware as we're removing the alpha_support flag for it. Regards, Joonas --- The following changes tagged drm-intel-testing-2018-02-21: drm-intel-next-2018-02-21: Driver Changes: - Lift alpha_support protection from

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Scanout fence fixes/cleanups (rev2)

== Series Details == Series: drm/i915: Scanout fence fixes/cleanups (rev2) URL : https://patchwork.freedesktop.org/series/38714/ State : warning == Summary == $ dim checkpatch origin/drm-tip c4c108df218b drm/i915: Fail if we can't get a fence for gen2/3 tiled scanout b5042b8f97b3 drm/i915:

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/guc: Support engine busy stats

== Series Details == Series: series starting with [1/2] drm/i915/guc: Support engine busy stats URL : https://patchwork.freedesktop.org/series/38717/ State : failure == Summary == Series 38717v1 series starting with [1/2] drm/i915/guc: Support engine busy stats

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/guc: Support engine busy stats

== Series Details == Series: series starting with [1/2] drm/i915/guc: Support engine busy stats URL : https://patchwork.freedesktop.org/series/38717/ State : warning == Summary == $ dim checkpatch origin/drm-tip 661f5ef77993 drm/i915/guc: Support engine busy stats -:33: WARNING: line over 80

[Intel-gfx] [PATCH v3 3/6] drm/i915: Clean up fbc vs. plane checks

From: Ville Syrjälä Let's record the information whether a plane can do fbc or not under struct inte_plane. v2: Rebase due to i9xx_plane_id Handle BDW/HSW correctly v3: Move inte_fbc_init() back since we depend on it happening even with

Re: [Intel-gfx] [PATCH] drm/i915/execlists: Remove the ring advancement under preemption

On 21/02/18 05:32, Chris Wilson wrote: Load an empty ringbuffer for preemption, ignoring the lite-restore workaround as we know the preempt context is always idle before preemption. True, injecting the preempt context shouldn't cause a lite-restore. And the restriction was to always have

[Intel-gfx] [PATCH 2/2] drm/i915: GuC test run

From: Tvrtko Ursulin With disabled aggressive idling from IGT. To see how shard run fares. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_debugfs.c | 3 --- drivers/gpu/drm/i915/i915_params.h | 2 +-

[Intel-gfx] [PATCH 1/2] drm/i915/guc: Support engine busy stats

From: Tvrtko Ursulin Place context in/out hooks into the GuC backend, when contexts are assigned to ports, and removed from them, in order to be able to provide engine busy stats in GuC mode. Signed-off-by: Tvrtko Ursulin Testcase:

Re: [Intel-gfx] [PATCH v2 1/1] drm/i915: Add and enable DP AUX CH mutex

On Wed, 2018-02-21 at 00:59 -0800, Dhinakaran Pandiyan wrote: > On Tuesday, February 20, 2018 6:23:47 PM PST José Roberto de Souza > wrote: > > When PSR/PSR2/GTC is enabled hardware can do AUX transactions by it > > self, so lets use the mutex register that is available in gen9+ to > > avoid

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Use correct error code for GuC initialization failure

On 2/21/2018 5:50 PM, Michal Wajdeczko wrote: On Wed, 21 Feb 2018 09:08:08 +0100, Sagar Arun Kamble wrote: On 2/21/2018 4:27 AM, Michal Wajdeczko wrote: Since commit 6ca9a2beb54a ("drm/i915: Unwind i915_gem_init() failure") we believed that we correctly handle

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915/guc: Use correct error code for GuC initialization failure

diff --git a/drivers/gpu/drm/i915/intel_uc_fw.h b/drivers/gpu/drm/i915/intel_uc_fw.h index d5fd460..0e3b237 100644 --- a/drivers/gpu/drm/i915/intel_uc_fw.h +++ b/drivers/gpu/drm/i915/intel_uc_fw.h @@ -115,6 +115,11 @@ static inline bool intel_uc_fw_is_selected(struct intel_uc_fw *uc_fw)

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/hsw: add missing disabled EUs registers reads (rev2)

== Series Details == Series: drm/i915/hsw: add missing disabled EUs registers reads (rev2) URL : https://patchwork.freedesktop.org/series/38441/ State : success == Summary == Test kms_flip: Subgroup 2x-flip-vs-expired-vblank-interruptible: fail -> PASS

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