No problem! I will commit a patch for CNP later.
On Tue, 12 Sep 2017, "Lee, Shawn C" wrote:
> Min brightness value from vbt was missing for BXT platform.
> This setting have to refer backlight ic spec to restrict min backlight
> output. Without this restriction, driver would
Min brightness value from vbt was missing for BXT platform.
This setting have to refer backlight ic spec to restrict
min backlight output. Without this restriction, driver would
allow to configure lower brightness value and violate
backlight ic requirement.
Fixes: 0fb890c01349 ("drm/i915/bxt: BLC
From: "Lee, Shawn C"
LFP flicker with latest drm-nightly on customer board. After increase
latency value and this symptom can't be reproduced.
TEST=Reboot DUT and no flicking on LFP.
Cc: Kumar, Mahesh
Cc: Gary C Wang
Signed-off-by: Shawn Lee
---
drivers/gpu/drm/i915/intel
From: "Lee, Shawn C"
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status. If PSR exit and link trainign are ongoing at eDP
sink. And eDP source read these registers at the same time.
eDP sink will report EQ & symbol lock not done. Then caused eDP
di
On 28/04/2017 10:58, Lee, Shawn C wrote:
>> From: "Lee, Shawn C"
>>
>> Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
>> eDP sink status. If PSR exit is ongoing at eDP sink, and eDP source
>> read these registers at the same time
On Fri, Apr 28, 2017 at 03:08:53AM +, Lee, Shawn C wrote:
> > From: "Lee, Shawn C"
> >
> > Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
> > eDP sink status. If PSR exit is ongoing at eDP sink, and eDP source
> > read thes
From: "Lee, Shawn C"
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status. If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will cause panel display flicking.
-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Thursday, April 27, 2017 10:39 PM
To: Lee, Shawn C
Cc: intel-gfx@lists.freedesktop.org; Chiou, Cooper ;
Bride, Jim ; Nikula, Jani ; Vivi,
Rodrigo ; Lin, Ryan
Subject: Re: [Intel-gfx] [PATCH] drm/i915
From: "Lee, Shawn C"
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status. If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will cause panel display flicking.
From: "Lee, Shawn C"
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status.If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will cause panel display flicking.
Tr
From: "Lee, Shawn C"
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status.If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will cause panel display flicking.
Tr
From: "Lee, Shawn C"
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status.If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will cause panel display flicking.
Tr
From: "Lee, Shawn C"
Display driver read DPCD register 0x202, 0x203 and 0x204 to identify
eDP sink status.If PSR exit is ongoing at eDP sink, and eDP source
read these registers at the same time. Panel will report EQ & symbol
lock not done. It will cause panel display flicking.
Tr
From: "Lee, Shawn C"
Add the missing INTEL_OUTPUT_DP_MST case in bxt_get_dpll()
to correctly initialize the crtc_state and port plls when
link training a DP MST monitor on BXT/APL devices.
Fixes: a277ca7dc01d ("drm/i915: Split bxt_ddi_pll_select()")
Bugs: https://
From: "Lee, Shawn C"
When user space link status, display driver read DPCD register
0x202, 0x203 and 0x204 to identify sink status. When PSR exit
is ongoing before EQ done. Panel will report EQ & symbol lock
not done. Both of them are under progressing at the same time
to cause thi
From: "Lee, Shawn C"
Kernel oops was trigger by DP MST monitor/hub connected.
DP MST series patch already upstream and MST should
be support also. MST monitor will display normally with this
change on bxt platform.
Fixes: a277ca7dc01d ("drm/i915: Split bxt_ddi_pll_select()&qu
From: "Lee, Shawn C"
Kernel oops was trigger by DP MST monitor/hub connected.
DP MST series patch already upstream and MST should
be support also. MST monitor will display normally with this
change on bxt platform.
Cc: Jani Nikula
Reviewed-by: Cooper Chiou
Reviewed-by: Gary C Wang
Understood. Thanks!
-Original Message-
From: Nikula, Jani
Sent: Monday, September 19, 2016 5:43 PM
To: Lee, Shawn C ; intel-gfx@lists.freedesktop.org
Cc: Lee, Shawn C
Subject: Re: [PATCH] drm/i915 : Restore PWM_GRANULARITY after resume
On Mon, 19 Sep 2016, "Lee, Shawn C&qu
From: "Lee, Shawn C"
SPT_PWM_GRANULARITY (SOUTH_CHICKEN1, bit 0) controls the granularity
(minimum increment) of the PWM backlight control counter. PWM frequency
adjustment on 128 clock increments when this bit was 1. And 16 clock
increments when it was 0.
PWM frequency multiple oct
panel->backlight.max = get_backlight_max_vbt(connector);
-Original Message-
From: Nikula, Jani
Sent: Monday, September 19, 2016 4:24 PM
To: intel-gfx@lists.freedesktop.org
Cc: Nikula, Jani ; Lee, Shawn C
Subject: [PATCH v2 1/2] drm/i915/backlight: setup and cache pwm alternat
From: "Lee, Shawn C"
SPT_PWM_GRANULARITY (SOUTH_CHICKEN1, bit 0) controls the granularity
(minimum increment) of the PWM backlight control counter. PWM frequency
adjustment on 128 clock increments when this bit was 1. And 16 clock
increments when it was 0.
PWM frequency multiple oct
From: "Lee, Shawn C"
SPT_PWM_GRANULARITY (SOUTH_CHICKEN1, bit 0) controls the granularity
(minimum increment) of the PWM backlight control counter. PWM frequency
adjustment on 128 clock increments when this bit was 1. And 16 clock
increments when it was 0.
PWM frequency multiple oct
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