vers/gpu/drm/i915/intel_pch.c
> > @@ -184,6 +184,23 @@ intel_virt_detect_pch(const struct
> drm_i915_private *dev_priv)
> > return id;
> > }
> >
> > +static void intel_detect_pch_virt(struct drm_i915_private *dev_priv)
> > +{
> > + unsigned
Zhang, Xiong Y would like to recall the message, "[PATCH v2] drm/i915: Try to
guess PCH type even without ISA bridge".
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
vers/gpu/drm/i915/intel_pch.c
> > @@ -184,6 +184,23 @@ intel_virt_detect_pch(const struct
> drm_i915_private *dev_priv)
> > return id;
> > }
> >
> > +static void intel_detect_pch_virt(struct drm_i915_private *dev_priv)
> > +{
> > + unsigned short id;
if (drm_WARN_ON(_priv->drm,
> > - id && pch_type == PCH_NONE))
> > - id = 0;
> > -
> > - dev_priv->pch_type = pch_type;
> > - dev_priv-&
gt; physical/unemulated access to the host GPU and CPU?
[Zhang, Xiong Y] yes, both host and guest use the same kernel/driver.
>
> On a higher level, it would help if anyone had an idea from the logs below if
> I'm "close" to getting this to work? Or maybe its hard to say?
[Zhang,
> Quoting Zhang, Xiong Y (2018-10-19 11:11:23)
> > > Quoting Zhenyu Wang (2018-10-19 04:05:20)
> > > > On 2018.10.18 13:40:31 +0800, Xiong Zhang wrote:
> > > > > Currently the guest couldn't boot up under GVT-g environment as
> > > > > the fol
r to be merged by i915 directly, or do you like a gvt pull
> instead?
>
> You only needed ctx->ppgtt being set I thought, as you previously ignored
> the initial PD bits in the context image and overwrote the registers anyway.
>
> Do you want what appe
drm_mm_remove_node().
>
> I'm not sure how this slipped by in previous review, but is there an
> explanation why we have;
>
> static struct _balloon_info_ bl_info;
>
> ... and are not even initializing it?
>
> This should definitely find it's way into dev_priv and be
> Quoting Xiong Zhang (2018-03-29 11:58:41)
> > Four drm_mm_node are used to reserve guest ggtt space, but some of
> > them may aren't initialized and used in intel_vgt_balloon(), so these
> > unused
>
> may be skipped and not initialised due to space constrai
@ffwll.ch>
> >
> > Afaiui if this isn't true on a machine, someone used a solder iron to
> > build something that Intel doesn't sell.
>
> Bspec says there are (at least) non-ULT/ULX Broadwells with LP PCH. We
> do seem to warn about the combo in the bare metal PCH detection
.d...@intel.com>
>
> I noticed a few issues in the surrounding code: SPT/SPT_LP and
> CNP/CNP_LP have the same problem, although we don't need to distinguish
> between them atm. I think a cleaner way would be to adjust id and ext_id
> in the pass-through case in intel_detect_pch()
> On ke, 2017-05-03 at 09:22 +0000, Zhang, Xiong Y wrote:
> > >
> > > >
> > > > + David and Jon
> > > >
> > > > On ti, 2017-04-25 at 18:34 +0800, Xiong Zhang wrote:
> > > >
> > > > The blocking issue I see is tha
e something wrong with them, in addition to stolen memory problems.
> [Zhang, Xiong Y] I only try kernel 4.8 and 4.9 above, as the bugzilla
> descripted,
> guest 4.8 kernel doesn't see gpu hang in guest dmesg, 4.9 kernel has gpu hang
> in guest dmesg. From this point, we could do git bise
d assume a successful
> bisect to land at the patches where we start creating kernel internal
> objects from stolen memory. Otherwise we could be ignoring a bug
> elsewhere. If it consistently lands on those patches, then there might
> be something wrong with them, in addition to stolen memory
> On Thu, 13 Apr 2017 05:44:18 +
> "Zhang, Xiong Y" <xiong.y.zh...@intel.com> wrote:
>
> > > On Wed, 12 Apr 2017 20:20:00 +0800
> > > Xiong Zhang <xiong.y.zh...@intel.com> wrote:
> > >
> > > > Stolen memory isn't a standar
_get_class(ISA). So
> > stolen memory will be disabled in this case also.
>
> Where does QEMU make this guarantee or any sort of guarantee wrt the
> ISA bridge? Thanks,
>
> Alex
>
[Zhang, Xiong Y] In my guest environment I always see emulated devices
are at head of pci de
ned-off-by: Xiong Zhang <xiong.y.zh...@intel.com>
> > Reviewed-by: Zhenyu Wang <zhen...@linux.intel.com>
> > Reviewed-by: Daniel Vetter <daniel.vet...@ffwll.ch>
> > Cc: sta...@vger.kernel.org
>
> The commit message still fails to address the fact that the Bug
gt; } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
> > ret = PCH_SPT;
> > + if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv))
> > + dev_priv->pch_id = INTEL_PCH_SPT_LP_DEVICE_ID_TYPE;
> > + else
> > +
> Which machine where does this blow up on?
> -Daniel
[Zhang, Xiong Y] Yes. Stolen memory is protected by RMRR on host. But Qemu
couldn't support and don't have plan to support RMRR. Then EPT lack of mapping
for stolen memory, guest couldn't access it.
The Qemu/Vfio is designed by Redhat en
e:
> > > > > >>
> > > > > >>
> > > > > >>
> > > > > >> On 2015-11-26 10:24, Takashi Iwai wrote:
> > > > > >>> On Thu, 26 Nov 2015 10:16:17 +0100,
> > > > > >>> Zhang, Xion
> On Thu, 26 Nov 2015 08:57:30 +0100,
> Zhang, Xiong Y wrote:
> >
> > > > > BTW, I have a patchset to avoid the audio h/w wakeup by a new
> > > > > component ops to get ELD and connection states. It was posted to
> > > > > alsa-devel s
Recently I always see the following error message during S4 or S3 resume with
drm-intel-nightly.
[ 97.778063] PM: Syncing filesystems ... done.
[ 97.801550] Freezing user space processes ... (elapsed 0.002 seconds) done.
[ 97.804297] PM: Marking nosave pages: [mem 0x-0x0fff]
[
> On Wed, 25 Nov 2015 10:56:51 +0100,
> Zhang, Xiong Y wrote:
> >
> > Recently I always see the following error message during S4 or S3 resume
> with drm-intel-nightly.
> > [ 97.778063] PM: Syncing filesystems ... done.
> > [ 97.801550] Freezing user space pro
patches are found in test/hdmi-jack
> > > branch of my sound git tree.
>
> Did you try this branch (merge onto intel-test-nightly)?
>
[Zhang, Xiong Y] Yes, this branch could fix my issue.
>
> Takashi
___
Intel-gfx mailing list
Intel-gf
> On Wed, 25 Nov 2015 11:57:13 +0100,
> Zhang, Xiong Y wrote:
> >
> > > On Wed, 25 Nov 2015 10:56:51 +0100,
> > > Zhang, Xiong Y wrote:
> > > >
> > > > Recently I always see the following error message during S4 or S3 resume
> >
I see the similar error message on one SKL machine, but DP system works well
and system doesn't panic.
I resolved it by one of the following three method, maybe you could try it.
1) boot with i915.disable_power_well=0
2)delete /lib/firmware/i915/skl_dmc_ver1.bin
3) apply the patch set in
On Wed, 2015-08-26 at 11:15 +0300, Jani Nikula wrote:
On Thu, 13 Aug 2015, Jindal, Sonika sonika.jin...@intel.com
wrote:
On 8/13/2015 8:57 AM, Zhang, Xiong Y wrote:
On Wed, 2015-08-12 at 02:20 +, Zhang, Xiong Y wrote:
On Tue, 2015-08-11 at 07:05 +, Zhang, Xiong Y wrote
On Fri, Aug 14, 2015 at 07:28:44PM +0300, Ville Syrjälä wrote:
On Fri, Aug 14, 2015 at 05:12:57AM +, Zhang, Xiong Y wrote:
On Mon, Aug 10, 2015 at 03:26:09PM +0800, Xiong Zhang wrote:
Only internal eDP, LVDS, DVI screen could set scalling mode, some
customers need to set
(POWER_DOMAIN_PORT_DDI_E_2_LANES)
[Zhang, Xiong Y] this line put DDI_E_2_LANES into
SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, but the git format-patch doesn’t show
#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS. So it isn’t easy to review this.
| \
BIT(POWER_DOMAIN_AUX_B
On Thu, Aug 13, 2015 at 02:57:38AM +, Zhang, Xiong Y wrote:
On Wed, Aug 12, 2015 at 06:39:34PM +0800, Xiong Zhang wrote:
DDI-E doesn't have the correspondent GMBUS pin.
We rely on VBT to tell us which one it being used instead.
The DVI/HDMI on shared port couldn't exist
/6]?
Nevermind, I see now that it got merged already.
I dropped that patch again so that we can rectify this properly. Jani's
complaint
about the sub-par commit message still holds though, like why was this not
caught in testing?
[Zhang, Xiong Y] Yes, it's better to drop it. I
understand the big scope first and then dig into details. But this one here
really
is small enough to just be squashed in.
-Daniel
[Zhang, Xiong Y] Thanks for teaching me how to handle this. I'll follow it in
the next version.
thanks
___
Intel-gfx
);
+ }
How are we supposed to get rid of a stale fixed_mode when some other
display gets plugged in?
[Zhang, Xiong Y] Thanks so much for your good question. Yes, we should clear the
stale fitting_mode and fixed_mode when display is disconnect in
intel_dp_hpd_pulse() function.
Also what would happen
.
v2: fix trailing whitespace
v3: WARN() take place of BUG()
I asked for MISSING_CASE, not WARN.
-Daniel
[Zhang, Xiong Y] Because DDI-E on SKL doesn't have correspondent GMBUS pin, it
should share such pin with DDI-B/C/D. We don't know the default GMBUS pin for
DDI-E if VBT doesn't tell us
On Wed, 2015-08-12 at 02:20 +, Zhang, Xiong Y wrote:
On Tue, 2015-08-11 at 07:05 +, Zhang, Xiong Y wrote:
-Original Message-
From: Vivi, Rodrigo
Sent: Saturday, August 8, 2015 8:34 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vivi, Rodrigo; Zhang, Xiong Y
On Tue, 2015-08-11 at 11:47 +0200, Daniel Vetter wrote:
On Thu, Aug 06, 2015 at 03:51:39PM +0800, Xiong Zhang wrote:
From: Rodrigo Vivi rodrigo.v...@intel.com
On Skylake we have eDP-to-VGA using DDI-E and another aux.
So let's identify it properly.
eDP means panel (the only
Reviewed-by: Xiong Zhang xiong.y.zh...@intel.com
thanks
From: Intel-gfx [intel-gfx-boun...@lists.freedesktop.org] on behalf of Rodrigo
Vivi [rodrigo.v...@intel.com]
Sent: Saturday, August 08, 2015 8:01 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vivi,
-Original Message-
From: Vivi, Rodrigo
Sent: Saturday, August 8, 2015 8:34 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vivi, Rodrigo; Zhang, Xiong Y
Subject: [PATCH 7/6] drm/i915/skl: DDI-E and DDI-A shares 4 lanes.
DDI-A and DDI-E shares the 4 lanes. So when DDI-E is present we
DDI-4 should be DDI-A in commit message.
Reviewed-by: Xiong Zhang xiong.y.zh...@intel.com
thanks
From: Intel-gfx [intel-gfx-boun...@lists.freedesktop.org] on behalf of Xiong
Zhang [xiong.y.zh...@intel.com]
Sent: Thursday, August 06, 2015 3:51 PM
To:
Reviewed-by: Xiong Zhang xiong.y.zh...@intel.com
thanks
From: Intel-gfx [intel-gfx-boun...@lists.freedesktop.org] on behalf of Xiong
Zhang [xiong.y.zh...@intel.com]
Sent: Thursday, August 06, 2015 3:51 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vivi,
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Tuesday, August 11, 2015 5:47 PM
To: Zhang, Xiong Y
Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo
Subject: Re: [Intel-gfx] [PATCH 4/6] drm/i915: eDP can be present on DDI-E
Reviewed-by: Xiong Zhang xiong.y.zh...@intel.com
thanks
-Original Message-
From: Vivi, Rodrigo
Sent: Saturday, August 8, 2015 8:35 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vivi, Rodrigo; Zhang, Xiong Y
Subject: [PATCH 8/6] drm/i915/skl: Enable DDI-E
There are OEMs using DDI-E
On Tue, 2015-08-11 at 07:05 +, Zhang, Xiong Y wrote:
-Original Message-
From: Vivi, Rodrigo
Sent: Saturday, August 8, 2015 8:34 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vivi, Rodrigo; Zhang, Xiong Y
Subject: [PATCH 7/6] drm/i915/skl: DDI-E and DDI-A shares 4 lanes
Hi, Vivi:
Do you think this patch could resolve the following two issues ?
https://bugs.freedesktop.org/show_bug.cgi?id=91050
https://bugs.freedesktop.org/show_bug.cgi?id=91269
thanks
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
On one Broadwell machine with Ubuntu 15.04, eDP is black after running xrandr
-output eDP1 -rotate inverted.
Only 3.19 kernel has such issue, 4.0 kernel doesn't have such issue.
When this issue happens, I see the following call trace in dmesg:
[ 108.777612] [drm:drm_mode_setcrtc] [CRTC:9]
[
Ubuntu 15.04 which will be released at the end of this month should support
Broadwell-H.
Ubuntu 15.04 beta still couldn’t support Broadwell-H.
Several days ago, I run Kernel 3.19.3 and xf86-video-intel – 2.99.917 on BDW-H.
thanks
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org]
I don’t know the status of Fedora.
You could compile upstream 3.19.3 / 4.0 kernel and xf86-video-intel – 2.99.917
in Fedora.
thanks
From: Heah, Jim Poh
Sent: Tuesday, April 14, 2015 12:38 PM
To: Zhang, Xiong Y; intel-gfx@lists.freedesktop.org
Subject: RE: [Contact] Graphics Driver for Broadwell
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Tuesday, December 23, 2014 7:31 PM
To: Zhang, Xiong Y
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] igt: Correct the return value for drm
short_buffer read
On Tue, Dec 23, 2014
-Original Message-
From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
Sent: Tuesday, December 23, 2014 5:53 PM
To: Zhang, Xiong Y
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] igt: Correct the return value for drm
short_buffer read
On Tue, Dec 23, 2014
Yes, I have tested it before I sent out the patch.
It hit all the slow paths.
Thanks.
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Saturday, July 20, 2013 12:14 AM
To: Zhang, Xiong Y
Cc: intel-gfx@lists.freedesktop.org
Subject
of
fault_in_multipages_writeable() lager than fault_in_multipages_readable() ?
See the attachment.
thanks
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Friday, July 19, 2013 3:29 PM
To: Zhang, Xiong Y
Cc: intel-gfx
?
Thanks
-Original Message-
From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of
Daniel Vetter
Sent: Friday, July 12, 2013 1:32 AM
To: Jesse Barnes
Cc: Zhang, Xiong Y; intel-gfx
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Decrease pll-refcount when freeze
gpu
On Thu, Jul
I found this issue when I read code. I don't have testcase.
thanks
-Original Message-
From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
Sent: Friday, July 05, 2013 9:41 PM
To: Zhang, Xiong Y
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 2
When ppgtt is enabled, dev_priv-gtt.total has excluded the gtt space occupied
by ppgtt table in i915_gem_init_global_gtt() function. So the calculation of
first_pd_entry_in_global_pt doesn't need to subtract I915_PPGTT_PD_ENTRIES
again. Or else PPGTT directory table will be destroyed by global
when system enter suspend, hibernate and poweroff state, it will
disable modeset firstly, then disable irq, but some system generate
hotplug event between disable modeset and disable irq, this will
result in S3, S4 failure. So this hotplug event should be ignored.
Bugzilla:
Using the latest mesa master tree, I test it on my Core i7-2600 :
1) In default configuration, the monitor's refresh rate is 60FPS, so the test
result is 59.3 FPS
2) export vblank_mode = 0, then the test result is 170 FPS.
I don't see the big difference between using direct transfer or using
Hi, all:
When gfx executes batch buffer in render ring buffer, it will do context switch
.
Since only when the previous batch buffer has finished, the next batch buffer
can start. the batch buffer is executed in order. So I think there is no need
to do context switch.
Why i915 driver
Who will monitor this sysfs interface, 2D driver or 3D driver or other
application ?
Now, I don't find any user of this sysfs interface in 2D driver or 3D driver.
thanks
-Original Message-
From: intel-gfx-bounces+xiong.y.zhang=intel@lists.freedesktop.org
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