>From spec the drain latency precision multipler is either 32 or 64 for VLV.
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/i915_reg.h | 18 +-
drivers/gpu/drm/i915/intel_pm.c | 12 ++--
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm
On Fri, Feb 28, 2014 at 06:50:06AM +0800, Zhenyu Wang wrote:
> >From spec the drain latency precision multipler is either 32 or 64 for VLV.
>
> Signed-off-by: Zhenyu Wang
> ---
> drivers/gpu/drm/i915/i915_reg.h | 18 +-
> drivers/gpu/drm/i915/intel_pm.c | 12 ++--
> 2 fil
On 2014.03.05 18:51:48 +0200, Ville Syrjälä wrote:
> > entries = (clock / 1000) * pixel_size;
> > *plane_prec_mult = (entries > 256) ?
>
> The threshold should also be reduced to 128 entries.
>
hmm, I'll double check if this is really required or not.
> > - DRAIN_LATENCY_PRECI
