Does my explanation from Thursday make sense or is it completely
off? Does the patch description need some update to be less
confusing to those used to different terminology?
On Thu, Aug 15, 2019 at 12:50:02PM +0200, Christoph Hellwig wrote:
> Except for the different naming scheme vs the code
On Thu, Aug 15, 2019 at 10:25:52AM +0100, James Bottomley wrote:
> > which means exporting normally cachable memory to userspace is
> > relatively dangrous due to cache aliasing.
> >
> > But normally cachable memory is only allocated by dma_alloc_coherent
> > on parisc when using the sba_iommu
On Thu, 2019-08-08 at 19:00 +0300, Christoph Hellwig wrote:
> parisc is the only architecture that sets ARCH_NO_COHERENT_DMA_MMAP
> when an MMU is enabled. AFAIK this is because parisc CPUs use VIVT
> caches,
We're actually VIPT but the same principle applies.
> which means exporting normally
Helger, or other parisc folks: can you take a look at this patch
in particular and the series in general? Thanks!
parisc is the only architecture that sets ARCH_NO_COHERENT_DMA_MMAP
when an MMU is enabled. AFAIK this is because parisc CPUs use VIVT
caches, which means exporting normally cachable memory to userspace is
relatively dangrous due to cache aliasing.
But normally cachable memory is only allocated
