> From: Lu Baolu < baolu...@linux.intel.com >
> Sent: Tuesday, December 17, 2019 10:04 AM
> To: Liu, Yi L ; Joerg Roedel ; David
> Woodhouse ; Alex Williamson
>
> Subject: Re: [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over
> first level
>
> Hi Yi,
Hi Yi,
On 12/15/19 5:37 PM, Liu, Yi L wrote:
XD (bit 63) is only for the first level, and SNP (bit 11) is only for second
level, right? I
think we need to always set XD bit for IOVA over FL case. thoughts?
Oops, I made a mistake here. Please forget SNP bit, there is no way to control
SNP
with
Hi Baolu,
> From: Lu Baolu [mailto:baolu...@linux.intel.com]
> Sent: Saturday, December 14, 2019 11:04 AM
> To: Liu, Yi L ; Joerg Roedel ; David
> Woodhouse ; Alex Williamson
>
> Subject: Re: [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over
> first level
>
Hi Liu Yi,
Thanks for reviewing my patch.
On 12/13/19 5:23 PM, Liu, Yi L wrote:
From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On Behalf
Of Lu Baolu
Sent: Wednesday, December 11, 2019 10:12 AM
Subject: [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over first
level
Hi Allen,
> From: kvm-ow...@vger.kernel.org [mailto:kvm-ow...@vger.kernel.org] On Behalf
> Of Lu Baolu
> Sent: Wednesday, December 11, 2019 10:12 AM
> Subject: [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over first
> level
>
> Intel VT-d in scalable mode supports two types of page ta
