2015-02-26 19:31-0300, Marcelo Tosatti:
> On Thu, Feb 26, 2015 at 10:49:53AM +0200, Nadav Amit wrote:
> > Marcello, Radim,
> >
> > As you know - I can run some tests on the patches and whether they comply
> > with real hardware. Please let me know which version to test and I’ll try to
> > do next
2015-02-25 22:55-0300, Marcelo Tosatti:
> > 1) when we have no x2APIC ID 0xff00, but send x2APIC message there
>
> 10.7 SYSTEM AND APIC BUS ARBITRATION
>
> Note that except for the SIPI IPI (see Section 10.6.1, “Interrupt
> Command Register (ICR)”), all bus messages that fail to be delivered
On Thu, Feb 26, 2015 at 10:49:53AM +0200, Nadav Amit wrote:
> Marcello, Radim,
>
> As you know - I can run some tests on the patches and whether they comply
> with real hardware. Please let me know which version to test and I’ll try to
> do next week.
>
> Regards,
> Nadav
>From what i understand
Marcello, Radim,
As you know - I can run some tests on the patches and whether they comply
with real hardware. Please let me know which version to test and I’ll try to
do next week.
Regards,
Nadav
Marcelo Tosatti wrote:
> Radim,
>
> On Thu, Feb 12, 2015 at 07:41:30PM +0100, Radim Krčmář wrote
Radim,
On Thu, Feb 12, 2015 at 07:41:30PM +0100, Radim Krčmář wrote:
> Each patch has a diff from v1, here is only a prologue on the mythical
> mixed xAPIC and x2APIC mode:
>
> There is one interesting alias in xAPIC and x2APIC ICR destination, the
> 0xff00, which is a broadcast in xAPIC and
Each patch has a diff from v1, here is only a prologue on the mythical
mixed xAPIC and x2APIC mode:
There is one interesting alias in xAPIC and x2APIC ICR destination, the
0xff00, which is a broadcast in xAPIC and either a physical message
to high x2APIC ID or a message to an empty set in x2AP