From: Marcelo Tosatti <[EMAIL PROTECTED]>
The irq ack during pic reset has three problems:
- Ignores slave/master PIC, using gsi 0-8 for both.
- Generates an ACK even if the APIC is in control.
- Depends upon IMR being clear, which is broken if the irq was masked
at the time it was generated.
Th
Avi Kivity wrote:
> Avi Kivity wrote:
>> Marcelo Tosatti wrote:
>>> On Wed, Aug 13, 2008 at 01:40:34PM +0300, Avi Kivity wrote:
>>>
Marcelo Tosatti wrote:
> The irq ack during pic reset has three problems:
>
> - Ignores slave/master PIC, using gsi 0-8 for both.
> - Ge
Avi Kivity wrote:
Marcelo Tosatti wrote:
On Wed, Aug 13, 2008 at 01:40:34PM +0300, Avi Kivity wrote:
Marcelo Tosatti wrote:
The irq ack during pic reset has three problems:
- Ignores slave/master PIC, using gsi 0-8 for both.
- Generates an ACK even if the APIC is in control.
- Depends u
Marcelo Tosatti wrote:
On Wed, Aug 13, 2008 at 01:40:34PM +0300, Avi Kivity wrote:
Marcelo Tosatti wrote:
The irq ack during pic reset has three problems:
- Ignores slave/master PIC, using gsi 0-8 for both.
- Generates an ACK even if the APIC is in control.
- Depends upon IMR being cle
On Wed, Aug 13, 2008 at 01:40:34PM +0300, Avi Kivity wrote:
> Marcelo Tosatti wrote:
>> The irq ack during pic reset has three problems:
>>
>> - Ignores slave/master PIC, using gsi 0-8 for both.
>> - Generates an ACK even if the APIC is in control.
>> - Depends upon IMR being clear, which is broken
Marcelo Tosatti wrote:
The irq ack during pic reset has three problems:
- Ignores slave/master PIC, using gsi 0-8 for both.
- Generates an ACK even if the APIC is in control.
- Depends upon IMR being clear, which is broken if the
irq was masked at the time it was generated.
The last one cause
The irq ack during pic reset has three problems:
- Ignores slave/master PIC, using gsi 0-8 for both.
- Generates an ACK even if the APIC is in control.
- Depends upon IMR being clear, which is broken if the
irq was masked at the time it was generated.
The last one causes the BIOS to hang after
