On 29 November 2016 at 21:09, Christoffer Dall
wrote:
> Actually, I'm not sure what the semantics of the line level ioctl should
> be for edge-triggered interrupts? My inclination is that it shouldn't
> have any effect at this point, but that would mean that at this point we
> should only set the
Hi,
In a VM (virsh controlled, KVM acceleration enabled) on a recent
kvmarm kernel host, I find I am unable to use perf to obtain
performance statistics for a complex task like kernel build.
(I've verified this is seen with a Fedora 25 VM and host combination
as well)
APM folks CC'ed think this m
On Tue, Nov 29, 2016 at 10:06:27PM +0530, Vijay Kilari wrote:
> On Tue, Nov 29, 2016 at 1:20 AM, Christoffer Dall
> wrote:
> > On Wed, Nov 23, 2016 at 06:31:54PM +0530, vijay.kil...@gmail.com wrote:
> >> From: Vijaya Kumar K
> >>
> >> Userspace requires to store and restore of line_level for
> >>
On Tue, Nov 29, 2016 at 11:53 AM, Suzuki K Poulose
wrote:
> On 29/11/16 09:36, Marc Zyngier wrote:
>>
>> On 29/11/16 03:28, Jintack Lim wrote:
>>>
>>> On Mon, Nov 28, 2016 at 1:39 PM, Marc Zyngier
>>> wrote:
On 28/11/16 17:43, Marc Zyngier wrote:
>>>
>>> This looks much cleaner than my
On 11/29/2016 4:29 AM, Shiju Jose wrote:
@@ -451,12 +484,12 @@ void cper_estatus_print(const char *pfx,
printk("%s""event severity: %s\n", pfx,
cper_severity_str(severity));
data_len = estatus->data_length;
gdata = (struct acpi_hest_generic_data *)(estatus + 1);
+
On 29/11/16 09:36, Marc Zyngier wrote:
On 29/11/16 03:28, Jintack Lim wrote:
On Mon, Nov 28, 2016 at 1:39 PM, Marc Zyngier wrote:
On 28/11/16 17:43, Marc Zyngier wrote:
This looks much cleaner than my patch.
While we are at it, is it worth to consider that we just need to set
those bits once
On Tue, Nov 29, 2016 at 1:20 AM, Christoffer Dall
wrote:
> On Wed, Nov 23, 2016 at 06:31:54PM +0530, vijay.kil...@gmail.com wrote:
>> From: Vijaya Kumar K
>>
>> Userspace requires to store and restore of line_level for
>> level triggered interrupts using ioctl KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO.
>>
Hello James,
On 11/25/2016 11:23 AM, James Morse wrote:
Hi Tyler,
On 21/11/16 22:35, Tyler Baicar wrote:
Add support for ARMv8 Common Platform Error Record (CPER).
UEFI 2.6 specification adds support for ARMv8 specific
processor error information to be reported as part of the
CPER records. Thi
Hi Tyler,
Please find the following comment.
Thanks,
Shiju
>
> Currently when a RAS error is reported it is not timestamped.
> The ACPI 6.1 spec adds the timestamp field to the generic error data
> entry v3 structure. The timestamp of when the firmware generated the
> error is now being report
> -Original Message-
> From: linux-acpi-ow...@vger.kernel.org [mailto:linux-acpi-
> ow...@vger.kernel.org] On Behalf Of Tyler Baicar
> Sent: 21 November 2016 22:36
> To: marc.zyng...@arm.com; pbonz...@redhat.com; rkrc...@redhat.com;
> li...@armlinux.org.uk; catalin.mari...@arm.com; will.dea
On Mon, Nov 28, 2016 at 09:13:02PM -0500, Jintack Lim wrote:
> From: Jintack
>
> Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit.
> EL1PCEN and EL1PCTEN are 1st and 0th bits when E2H is not set, but they
> are 11th and 10th bits respectively when E2H is set. Current code i
On Tue, Nov 29, 2016 at 4:36 AM, Marc Zyngier wrote:
> On 29/11/16 03:28, Jintack Lim wrote:
>> On Mon, Nov 28, 2016 at 1:39 PM, Marc Zyngier wrote:
>>> On 28/11/16 17:43, Marc Zyngier wrote:
Hi Jintack,
>>
>> Hi Marc,
>>
On 28/11/16 16:46, Jintack Lim wrote:
> Bit positions of
On 29/11/16 10:47, Christoffer Dall wrote:
> On Tue, Nov 29, 2016 at 09:37:07AM +, Marc Zyngier wrote:
>> On 28/11/16 19:42, Christoffer Dall wrote:
>>> On Mon, Nov 28, 2016 at 06:39:04PM +, Marc Zyngier wrote:
On 28/11/16 17:43, Marc Zyngier wrote:
> Hi Jintack,
>
> On 28/
On Tue, Nov 29, 2016 at 03:31:44PM +0530, Vijay Kilari wrote:
> On Tue, Nov 29, 2016 at 2:07 PM, Christoffer Dall
> wrote:
> > On Tue, Nov 29, 2016 at 01:08:26PM +0530, Vijay Kilari wrote:
> >> On Tue, Nov 29, 2016 at 1:09 AM, Christoffer Dall
> >> wrote:
> >> > On Wed, Nov 23, 2016 at 06:31:53PM
On Tue, Nov 29, 2016 at 09:37:07AM +, Marc Zyngier wrote:
> On 28/11/16 19:42, Christoffer Dall wrote:
> > On Mon, Nov 28, 2016 at 06:39:04PM +, Marc Zyngier wrote:
> >> On 28/11/16 17:43, Marc Zyngier wrote:
> >>> Hi Jintack,
> >>>
> >>> On 28/11/16 16:46, Jintack Lim wrote:
> Bit pos
On Tue, Nov 29, 2016 at 2:07 PM, Christoffer Dall
wrote:
> On Tue, Nov 29, 2016 at 01:08:26PM +0530, Vijay Kilari wrote:
>> On Tue, Nov 29, 2016 at 1:09 AM, Christoffer Dall
>> wrote:
>> > On Wed, Nov 23, 2016 at 06:31:53PM +0530, vijay.kil...@gmail.com wrote:
>> >> From: Vijaya Kumar K
>> >>
>>
On 28/11/16 19:42, Christoffer Dall wrote:
> On Mon, Nov 28, 2016 at 06:39:04PM +, Marc Zyngier wrote:
>> On 28/11/16 17:43, Marc Zyngier wrote:
>>> Hi Jintack,
>>>
>>> On 28/11/16 16:46, Jintack Lim wrote:
Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit.
EL1PCE
On 29/11/16 03:28, Jintack Lim wrote:
> On Mon, Nov 28, 2016 at 1:39 PM, Marc Zyngier wrote:
>> On 28/11/16 17:43, Marc Zyngier wrote:
>>> Hi Jintack,
>
> Hi Marc,
>
>>>
>>> On 28/11/16 16:46, Jintack Lim wrote:
Bit positions of CNTHCTL_EL2 are changing depending on HCR_EL2.E2H bit.
EL
On Tue, Nov 29, 2016 at 01:08:26PM +0530, Vijay Kilari wrote:
> On Tue, Nov 29, 2016 at 1:09 AM, Christoffer Dall
> wrote:
> > On Wed, Nov 23, 2016 at 06:31:53PM +0530, vijay.kil...@gmail.com wrote:
> >> From: Vijaya Kumar K
> >>
> >> VGICv3 CPU interface registers are accessed using
> >> KVM_DEV
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