likely(order >= MAX_ORDER)) {
WARN_ON_ONCE(!(gfp & __GFP_NOWARN));
return NULL;
}
WARNING: CPU: 122 PID: 4025 at mm/page_alloc.c:5383 __alloc_pages
CPU: 122 PID: 4025 Comm: brk_near_huge Not tainted 5.18.0-rc5-next-20220503 #79
pstate: 2049 (nzCv daif
On Wed, 4 May 2022 at 05:22, Mark Brown wrote:
>
> On Tue, May 03, 2022 at 06:23:40PM -0400, Qian Cai wrote:
> > On Tue, Apr 19, 2022 at 12:22:08PM +0100, Mark Brown wrote:
> > > This series provides initial support for the ARMv9 Scalable Matrix
> > > Extension (SME). SME takes the approach used
On Tue, May 03, 2022 at 06:23:40PM -0400, Qian Cai wrote:
> On Tue, Apr 19, 2022 at 12:22:08PM +0100, Mark Brown wrote:
> > This series provides initial support for the ARMv9 Scalable Matrix
> > Extension (SME). SME takes the approach used for vectors in SVE and
> > extends this to provide archite
When adding support for the slightly wonky Apple M1, we had to
populate ID_AA64PFR0_EL1.GIC==1 to present something to the guest,
as the HW itself doesn't advertise the feature.
However, we gated this on the in-kernel irqchip being created.
This causes some trouble for QEMU, which snapshots the st
On Tue, 03 May 2022 19:49:13 +0100,
Raghavendra Rao Ananta wrote:
>
> Hi Marc,
>
> On Tue, May 3, 2022 at 10:24 AM Marc Zyngier wrote:
> >
> > On Tue, 03 May 2022 00:38:44 +0100,
> > Raghavendra Rao Ananta wrote:
> > >
> > > Hello,
> > >
> > > Continuing the discussion from [1], the series tri
On Mon, 02 May 2022 17:54:45 +0100,
Kalesh Singh wrote:
>
> On Thu, Apr 28, 2022 at 12:55 PM Marc Zyngier wrote:
> >
> > On Wed, 20 Apr 2022 14:42:51 -0700, Kalesh Singh wrote:
> > > This is v8 of the nVHE hypervisor stack enhancements. This version is
> > > based
> > > on 5.18-rc3.
> > >
> > >
Hi Ricardo,
On 4/27/22 20:48, Ricardo Koller wrote:
> Failed ITS restores should clean up all state restored until the
> failure. There is some cleanup already present when failing to restore
> some tables, but it's not complete. Add the missing cleanup.
>
> Note that this changes the behavior in
Hi Ricardo,
On 4/27/22 20:48, Ricardo Koller wrote:
> Restoring a corrupted collection entry is being ignored and treated as
maybe precise what is a corrupted ITE (out of range id or not matching
guest RAM)
> success. More specifically, vgic_its_restore_cte failure is treated as
> success by vgic_
On Tue, 03 May 2022 00:38:44 +0100,
Raghavendra Rao Ananta wrote:
>
> Hello,
>
> Continuing the discussion from [1], the series tries to add support
> for the userspace to elect the hypercall services that it wishes
> to expose to the guest, rather than the guest discovering them
> unconditional
Hi Ricardo,
On 4/27/22 20:48, Ricardo Koller wrote:
> Try to improve the predictability of ITS save/restores (and debuggability
> of failed ITS saves) by failing early on restore when trying to read
> corrupted tables.
>
> Restoring the ITS tables does some checks for corrupted tables, but not as
Hi Ricardo,
On 4/27/22 20:48, Ricardo Koller wrote:
> Try to improve the predictability of ITS save/restores by failing
> commands that would lead to failed saves. More specifically, fail any
> command that adds an entry into an ITS table that is not in guest
> memory, which would otherwise lead t
On Tue, 03 May 2022 00:38:50 +0100,
Raghavendra Rao Ananta wrote:
>
> Add the documentation for the bitmap firmware registers in
> hypercalls.rst and api.rst. This includes the details for
> KVM_REG_ARM_STD_BMAP, KVM_REG_ARM_STD_HYP_BMAP, and
> KVM_REG_ARM_VENDOR_HYP_BMAP registers.
>
> Since th
On Tue, 03 May 2022 00:38:46 +0100,
Raghavendra Rao Ananta wrote:
>
> KVM regularly introduces new hypercall services to the guests without
> any consent from the userspace. This means, the guests can observe
> hypercall services in and out as they migrate across various host
> kernel versions. T
On Tue, 03 May 2022 00:38:45 +0100,
Raghavendra Rao Ananta wrote:
>
> Common hypercall firmware register handing is currently employed
> by psci.c. Since the upcoming patches add more of these registers,
> it's better to move the generic handling to hypercall.c for a
> cleaner presentation.
>
>
On Tue, 3 May 2022 06:01:58 +, Oliver Upton wrote:
> KVM/arm64 does not restrict the guest's view of the AArch32 feature
> registers when read from AArch32. HCR_EL2.TID3 is cleared for AArch32
> guests, meaning that register reads come straight from hardware. This is
> problematic as KVM relies
The 04/28/2022 10:19, Catalin Marinas wrote:
> On Tue, Apr 19, 2022 at 12:22:12PM +0100, Mark Brown wrote:
> > +* There are a number of optional SME features, presence of these is
> > reported
> > + through AT_HWCAP2 through:
> > +
> > + HWCAP2_SME_I16I64
> > + HWCAP2_SME_F64F64
> > + HWCAP
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