On Sat, May 14, 2022 at 1:59 AM David Matlack wrote:
>
> Allow the capacity of the kvm_mmu_memory_cache struct to be chosen at
> declaration time rather than being fixed for all declarations. This will
> be used in a follow-up commit to declare an cache in x86 with a capacity
> of 512+ objects wit
On Fri, 13 May 2022 21:28:18 +0100,
David Matlack wrote:
>
> Allow the capacity of the kvm_mmu_memory_cache struct to be chosen at
> declaration time rather than being fixed for all declarations. This will
> be used in a follow-up commit to declare an cache in x86 with a capacity
> of 512+ object
On Fri, 13 May 2022 10:26:07 +0100,
Quentin Perret wrote:
>
> Will reported the following splat when running with Protected KVM
> enabled:
>
> [2.427181] [ cut here ]
> [2.427668] WARNING: CPU: 3 PID: 1 at arch/arm64/kvm/mmu.c:489
> __create_hyp_private_mapping+0
On Tue, 10 May 2022 09:57:06 +, Fuad Tabba wrote:
> This series changes the way KVM communicates host pmu event changes to the
> hypervisor in nvhe and protected mode. Instead of accessing hyp data directly
> from the host, the data is passed to hyp via the loaded vcpu. This provides
> more iso
On Sat, 14 May 2022 11:25:24 +0100, Marc Zyngier wrote:
> Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
> original M1 and generate random SErrors in the host when a guest
> tickles the GICv3 CPU interface the wrong way.
>
> Add the part numbers for both the CPU types found in
On 2022-05-05 14:32, Paolo Bonzini wrote:
On 5/5/22 14:04, Marc Zyngier wrote:
diff --git a/arch/arm64/include/uapi/asm/kvm.h
b/arch/arm64/include/uapi/asm/kvm.h
index e523bb6eac67..3cde9f958eee 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -342,6 +34
Hi Fuad,
On 2022-05-10 10:57, Fuad Tabba wrote:
Hi,
This series changes the way KVM communicates host pmu event changes to
the
hypervisor in nvhe and protected mode. Instead of accessing hyp data
directly
from the host, the data is passed to hyp via the loaded vcpu. This
provides
more isolat
On Sat, May 14, 2022 at 11:25:24AM +0100, Marc Zyngier wrote:
> Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
> original M1 and generate random SErrors in the host when a guest
> tickles the GICv3 CPU interface the wrong way.
>
> Add the part numbers for both the CPU types fou