, APDBKey) are disabled,
and will behave as NOPs. These may be made use of in future patches.
No support is added for the generic key (APGAKey), though this cannot be
trapped or made to behave as a NOP. Its presence is not advertised with
a hwcap.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com&
On Wed, Apr 12, 2017 at 08:51:31PM +0200, Andrey Konovalov wrote:
> On Wed, Apr 12, 2017 at 8:43 PM, Marc Zyngier wrote:
> > On 12/04/17 17:19, Andrey Konovalov wrote:
> >> I now have a way to reproduce it, so I can test proposed patches. I
> >> don't have a simple C
Hi,
On Thu, Mar 30, 2017 at 06:31:07PM +0800, Xie XiuQi wrote:
> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index f20c64a..22f9c90 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
> @@ -106,6 +106,20 @@
> #define ESR_ELx_AR
registers, and
to allow us to change the way these are handled in future, a new
sys_insn() alias for sys_reg() is added and used for these new
definitions.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Marc Zyngier <marc.zyng...@arm.
Now that we have common definitions for the GICv3 register encodings,
make the KVM code use these, simplifying the sys_reg_descs table.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.
This patch adds a macro enabling us to initialise sys_reg_desc
structures based on common sysreg encoding definitions in
. Subsequent patches will use this to simplify the KVM
code.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linaro.org&
Now that we have common definitions for the remaining register encodings
required by KVM, make the KVM code use these, simplifying the
sys_reg_descs table and the genericv8_sys_regs table.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linar
Now that we have common definitions for the register encodings used by
KVM, make the KVM code uses thse for invariant sysreg definitions. This
makes said definitions a reasonable amount shorter, especially as many
comments are rendered redundant and can be removed.
Signed-off-by: Mark Rutland
-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/kvm/sys_regs.c | 73 ++-
1 file changed, 21 insertion
Now that we have common definitions for the encoding of Set/Way cache
maintenance operations, make the KVM code use these, simplifying the
sys_reg_descs table.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linaro.org>
Cc: Marc Zyngie
are only made for
registers used today by KVM.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: Suzuki K Poulose <suzuki.poul...@arm.com>
Cc: Will Deacon <will.dea...@arm.com&g
document.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: Suzuki K Poulose <suzuki.poul...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
---
arch/arm64/include/asm/sysreg.h | 2
This patch adds sysreg definitions for system registers in the debug and
trace system register encoding space. Subsequent patches will make use
of these definitions.
The encodings were taken from ARM DDI 0487A.k_iss10775, Table C5-5.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: C
Now that we have common definitions for the physical timer control
registers, make the KVM code use these, simplifying the sys_reg_descs
table.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.
is applied to bring these into line with the usual comment style.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/k
This patch adds sysreg definitions for system registers used to control
the architected physical timer. Subsequent patches will make use of
these definitions.
The encodings were taken from ARM DDI 0487A.k_iss10775, Table C5-6.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: C
moves the definitions to ,
adding a SYS_ prefix, and sorting the registers per their encoding.
Existing users of the definitions are fixed up so that this change is
not problematic.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc:
conflicts.
This patch enforces this order, by moving the few items that break it.
There should be no functional change.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: Suzuki K Poulose <s
the physical counter registers.
* Verified section differences again.
Thanks,
Mark.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git
arm64/common-sysreg
[2]
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-January/484693.html
Mark Rutland (15):
arm64: sysreg: sort
e(pte, pfn_pte(pfn, prot));
> - pfn++;
> + set_pte(pte, pfn_pte(__phys_to_pfn(phys), prot));
> + phys += PAGE_SIZE;
Minor nit: so as to align the strucutre of the loop with the other
functions, it'd be nice to have this on the f
On Thu, Mar 09, 2017 at 04:52:18AM -0800, Christoffer Dall wrote:
> On Mon, Jan 16, 2017 at 05:33:34PM +0800, Shannon Zhao wrote:
> > From: Shannon Zhao
> >
> > Check if the configuration is fine.
>
> This commit message really needs some love and attention.
>
> >
> >
ing() without
exposing those more generally, this also looks fine.
FWIW:
Reviewed-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
___
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
On Thu, Mar 09, 2017 at 09:25:12AM +0100, Ard Biesheuvel wrote:
> +static inline u64 pte_cont_addr_end(u64 addr, u64 end)
> +{
> + return min((addr + CONT_PTE_SIZE) & CONT_PTE_MASK, end);
> +}
> +
> +static inline u64 pmd_cont_addr_end(u64 addr, u64 end)
> +{
> + return min((addr +
>
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Reviewed-by: Mark Rutland <mark.rutl...@arm.com>
Strictly speaking, I think this is marginally more stringent than what
the ARM ARM describes. My reading is that the "Misprogramming of the
Contiguous bit"
lloc(), and never mandate
page mappings.
Regardless:
Reviewed-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
> ---
> arch/arm64/mm/mmu.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
> index c3963c592ec
On Fri, Mar 10, 2017 at 06:35:55PM +, Will Deacon wrote:
> On Fri, Mar 10, 2017 at 08:17:22AM +, Marc Zyngier wrote:
> > On Thu, Mar 09 2017 at 5:07:12 pm GMT, Mark Rutland <mark.rutl...@arm.com>
> > wrote:
> > The next question is how do we merge this
On Wed, Mar 08, 2017 at 11:57:22AM +0100, Ard Biesheuvel wrote:
> On 7 March 2017 at 17:46, Mark Rutland <mark.rutl...@arm.com> wrote:
> > Note that I've cheated and made alloc_init_pte() take a phys_addr_t
> > rather than a pfn, which I think we should do anyhow for co
On Mon, Mar 06, 2017 at 07:08:03AM -0800, Christoffer Dall wrote:
> On Mon, Feb 20, 2017 at 12:30:11PM +0000, Mark Rutland wrote:
> > static exit_handle_fn arm_exit_handlers[] = {
> > + [0 ... HSR_EC_MAX] = kvm_handle_unknown_ec,
>
> Cool stuff, didn't know y
ap_kernel_segment(pgd, __start_rodata, __inittext_begin, PAGE_KERNEL,
> +_rodata);
> + map_kernel_segment(pgd, __inittext_begin, __inittext_end, text_prot,
> +_inittext);
> + map_kernel_segment(pgd, __initdata_begin, __initdata_end, PAGE_KER
el_segment(pgd, _text, _etext, PAGE_KERNEL_EXEC, _text);
> + pgprot_t text_prot = rodata_enabled ? PAGE_KERNEL_ROX :
> PAGE_KERNEL_EXEC;
> +
It might be worth having a comment as to why, e.g.
/*
* External debuggers may need to write directly to the text
Hi,
On Sat, Mar 04, 2017 at 02:30:48PM +, Ard Biesheuvel wrote:
> This is the third attempt at enabling the use of contiguous hints for
> kernel mappings. The most recent attempt 0bfc445dec9d was reverted after
> it turned out that updating permission attributes on live contiguous ranges
>
gt; is fine to do so, as we are doing it from the context of the same process.
>
> This also prevents the race condition where mmu_notifier_release() could
> be called in parallel and one instance could end up using a free'd kvm
> instance.
>
> Cc: Mark Rutland <mark.rutl...@arm
On Tue, Apr 18, 2017 at 09:32:31AM +0100, Mark Rutland wrote:
> Hi Suzuki,
>
> On Thu, Apr 13, 2017 at 04:50:46PM +0100, Suzuki K. Poulose wrote:
> > kvm: Hold reference to the user address space
> >
> > The core KVM code, uses mmgrab/mmdrop to pin the mm struct
On Tue, Jul 25, 2017 at 01:06:43PM +0100, Mark Rutland wrote:
> On Fri, Jul 21, 2017 at 06:05:09PM +0100, Dave Martin wrote:
> > On Wed, Jul 19, 2017 at 05:01:21PM +0100, Mark Rutland wrote:
> > > This series adds support for the ARMv8.3 pointer authentication extension.
>
.
This is sufficient for systems with uniform pointer authentication
support. For systems with mismatched support, it will be necessary to
hide the feature from the guest's view of the ID registers.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linaro.org>
Cc:
, APDBKey) are disabled,
and will behave as NOPs. These may be made use of in future patches.
No support is added for the generic key (APGAKey), though this cannot be
trapped or made to behave as a NOP. Its presence is not advertised with
a hwcap.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com&
in
__tlb_switch_to_guest_vhe().
The now unused HCR_HOST_VHE_FLAGS definition is removed.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/inc
Now that we've added code to support pointer authentication, add some
documentation so that people can figure out if/how to use it.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Jiong Wang <jiong.w...@arm.com>
Cc: Wil
HCR_EL2
itself.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Christoffer Dall <christoffer.d...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Cc: kvmarm@lists.cs.columbia.e
So that we can dynamically handle the presence of pointer authentication
functionality, wire up probing code in cpufeature.c.
Currently, this only detects the presence of an architected algorithm.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@ar
ned-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Cc: Suzuki K Poulose <suzuki.poul...@arm.com>
---
arch/arm64/kernel/cpufeature.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(
://lists.infradead.org/pipermail/linux-arm-kernel/2017-April/498941.html
[2] git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git
arm64/pointer-auth
[3] git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git
pointer-auth
Mark Rutland (11):
arm64: docs: describe ELF hwcaps
asm-generic
, allow each hook to be overridden indiviually,
by placing each under an #ifndef block. As architectures providing their
own hooks can't include this file today, this shouldn't adversely affect
any existing hooks.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Arnd Bergmann <a...@arn
ESR_ELx.EC code used when the new instructions are affected by
configurable traps
This patch adds the relevant definitions to and
for these, to be used by subsequent patches.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Suzu
that developers could
refer to.
This patch adds a document describing the (native) arm64 ELF hwcaps.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Dave Martin <dave.mar...@arm.com>
Cc: Suzuki K Poulose <suzuki.poul...@arm.com>
C
On Fri, Jul 21, 2017 at 06:05:09PM +0100, Dave Martin wrote:
> On Wed, Jul 19, 2017 at 05:01:21PM +0100, Mark Rutland wrote:
> > This series adds support for the ARMv8.3 pointer authentication extension.
> > Open questions
> > ==
> >
> > * Should k
On Tue, Jul 25, 2017 at 01:11:48PM +0100, Dave Martin wrote:
> On Mon, Apr 03, 2017 at 04:19:23PM +0100, Mark Rutland wrote:
> > +/*
> > + * The pointer bits used by a pointer authentication code.
> > + * If we were to use tagged pointers, bits 63:56 would also apply.
Hi,
On Tue, Jul 25, 2017 at 12:32:10PM +0100, Yao Qi wrote:
> On 19/07/17 17:01, Mark Rutland wrote:
> > If authentication fails, bits are set in the pointer such that it is
> > guaranteed to cause a fault if used.
>
> How does user space know the fault is caused b
Hi,
On Wed, Apr 26, 2017 at 02:46:16PM -0700, Matthias Kaehlcke wrote:
> Many inline assembly statements don't include the 'x' modifier when
> using xN registers as operands. This is perfectly valid, however it
> causes clang to raise warnings like this:
>
> warning: value size does not match
On Fri, Apr 28, 2017 at 11:20:21AM +0100, Ard Biesheuvel wrote:
> On 28 April 2017 at 10:53, Mark Rutland <mark.rutl...@arm.com> wrote:
> > On Fri, Apr 28, 2017 at 08:18:52AM +0100, Ard Biesheuvel wrote:
> >> On 27 April 2017 at 23:52, Matthias Kaehlcke <m...@chromiu
On Fri, Apr 28, 2017 at 08:18:52AM +0100, Ard Biesheuvel wrote:
> On 27 April 2017 at 23:52, Matthias Kaehlcke <m...@chromium.org> wrote:
> > El Thu, Apr 27, 2017 at 12:02:56PM +0100 Mark Rutland ha dit:
> >> On Wed, Apr 26, 2017 at 02:46:16PM -0700, Matthias Kaehlck
On Tue, Aug 01, 2017 at 01:00:14PM +0200, Christoffer Dall wrote:
> On Wed, Jul 19, 2017 at 05:01:31PM +0100, Mark Rutland wrote:
> > When pointer authentication is supported, a guest may wish to use it.
> > This patch adds the necessary KVM infrastructure for this to work, with
On Wed, May 03, 2017 at 11:45:42AM +0100, Marc Zyngier wrote:
> As we're about to access the Active Priority registers a lot more,
> let's define accessors that take the register number as a parameter.
>
> Signed-off-by: Marc Zyngier
> ---
> virt/kvm/arm/hyp/vgic-v3-sr.c |
kill, let's add a set of macros that convert an ESR value into
> the corresponding sysreg encoding.
>
> We handle both AArch32 and AArch64, taking advantage of identical
> encodings between system registers and CP15 accessors.
>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm
We've supported KVM with 16K pages since commit:
02e0b7600f835007 ("arm64: kvm: Add support for 16K pages")
... yet the kconfig text says this combination is not supported.
Let's fix that by deleting the misleading text.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
kvm-arm64/gicv3-cpuif-mediated-access
Mark Rutland (2):
arm64/kvm: sysreg: fix typo'd SYS_ICC_IGRPEN*_EL1
arm64/kvm: vgic: use SYS_DESC()
arch/arm64/include/asm/arch_gicv3.h | 2 +-
arch/arm64/include/asm/sysreg.h | 12
Almost all of the arm64 KVM code uses the sysreg mnemonics for AArch64
register descriptions. Move the last straggler over.
To match what we do for SYS_ICH_AP*R*_EL2, the SYS_ICC_AP*R*_EL1
mnemonics are expanded in .
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin M
Per ARM DDI 0487B.a, the registers are named ICC_IGRPEN*_EL1 rather than
ICC_GRPEN*_EL1. Correct our mnemonics and comments to match, before we
add more GICv3 register definitions.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc:
On Tue, May 30, 2017 at 05:17:01PM +0100, Marc Zyngier wrote:
> On 03/05/17 16:58, Marc Zyngier wrote:
> > On 03/05/17 16:32, Mark Rutland wrote:
> >> On Wed, May 03, 2017 at 11:45:42AM +0100, Marc Zyngier wrote:
> >>> +static void __hyp_text __vgic
So that we can dynamically handle the presence of pointer authentication
functionality, wire up probing code in cpufeature.c.
It is assumed that if all CPUs support an IMP DEF algorithm, the same
algorithm is used across all CPUs.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: C
sts and
userspace. As marking them with FTR_HIDDEN only hides them from
userspace, they are also protected with ifdeffery on
CONFIG_ARM64_POINTER_AUTHENTICATION.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Suzuki K Poulose <suzuki.poul...@arm.com>
Cc: Catalin Marinas <catal
, allow each hook to be overridden indiviually,
by placing each under an #ifndef block. As architectures providing their
own hooks can't include this file today, this shouldn't adversely affect
any existing hooks.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Arnd Bergmann <a...@arn
is added for the generic key (APGAKey), though this cannot be
trapped or made to behave as a NOP. Its presence is not advertised with
a hwcap.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Suzuki K Poulose <suzuki.poul
HCR_EL2
itself.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Christoffer Dall <cd...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
---
ar
the LR value, and not the
FP.
This only affects the in-kernel unwinder. When userspace performs
unwinding, it is up to userspace to strip PACs as necessary (which can
be determined from DWARF information).
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari..
ESR_ELx.EC code used when the new instructions are affected by
configurable traps
This patch adds the relevant definitions to and
for these, to be used by subsequent patches.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Suzu
://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git
pointer-auth
Mark Rutland (12):
asm-generic: mm_hooks: allow hooks to be overridden individually
arm64: add pointer authentication register bits
arm64/cpufeature: add ARMv8.3 id_aa64isar1 bits
arm64/cpufeature: detect
in
__tlb_switch_to_guest_vhe().
The now unused HCR_HOST_VHE_FLAGS definition is removed.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Reviewed-by: Christoffer Dall <cd...@linaro.org>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/include/
(when scheduled on a physical CPU which
supports the relevant feature). When the guest is scheduled on a
physical CPU lacking the feature, these atetmps will result in an UNDEF
being taken by the guest.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Christoffer Dall <cd...@linaro.org&
Now that we've added code to support pointer authentication, add some
documentation so that people can figure out if/how to use it.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Cc: Yao
On Wed, Nov 01, 2017 at 08:54:44PM +0800, gengdongjiu wrote:
> On 2017/11/1 19:24, Robin Murphy wrote:
> >> + esb
> >> +alternative_else_nop_endif
> >> +1:
> >> + .endm
> > Having a branch in here is pretty horrible, and furthermore using label
> > number 1 has a pretty high chance of subtly
// SPDX-License-Identifier: GPL-2.0
> +// Copyright (C) 2017 Arm Ltd.
> +#ifndef __ASM_VMAP_STACK_H
> +#define __ASM_VMAP_STACK_H
> +
> +#include
> +#include
> +#include
> +#include
> +#include
I think we also need:
#include // for BUILD_BUG_ON()
#incldue
Hi,
On Sun, Dec 10, 2017 at 08:03:43PM -0600, Shanker Donthineni wrote:
> +/**
> + * Errata workaround prior to disable MMU. Insert an ISB immediately prior
> + * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
> + */
> + .macro pre_disable_mmu_workaround
> +#ifdef
On Sat, Oct 21, 2017 at 05:18:17PM +0200, Christoffer Dall wrote:
> On Fri, Oct 20, 2017 at 05:54:40PM +0100, Mark Rutland wrote:
> > On Fri, Oct 20, 2017 at 05:53:39PM +0100, Marc Zyngier wrote:
> > > On 20/10/17 17:27, Mark Rutland wrote:
> > > > On Fri, Oct 20,
On Fri, Apr 27, 2018 at 11:51:39AM +0200, Christoffer Dall wrote:
> On Tue, Apr 17, 2018 at 07:37:26PM +0100, Mark Rutland wrote:
> > In KVM we define the configuration of HCR_EL2 for a VHE HOST in
> > HCR_HOST_VHE_FLAGS, but we don't ahve a similar definition for the
>
> nit
On Wed, Apr 25, 2018 at 12:23:32PM +0100, Catalin Marinas wrote:
> Hi Mark,
>
> On Tue, Apr 17, 2018 at 07:37:31PM +0100, Mark Rutland wrote:
> > diff --git a/arch/arm64/include/asm/mmu_context.h
> > b/arch/arm64/include/asm/mmu_context.h
> > index 39ec0b
block.
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Christoffer Dall <christoffer.d...@arm.com>
Cc: Marc Zyngier <marc.zyng...@arm.com>
Cc: kvmarm@lists.cs.columbia.edu
---
arch/arm64/include/asm/kvm_asm.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
Sinc
On Wed, May 23, 2018 at 10:23:20AM +0100, Julien Grall wrote:
> Hi Marc,
>
> On 05/22/2018 04:06 PM, Marc Zyngier wrote:
> > diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> > index ec2ee720e33e..f33e6aed3037 100644
> > --- a/arch/arm64/kernel/entry.S
> > +++
On Tue, May 22, 2018 at 04:06:36PM +0100, Marc Zyngier wrote:
> In order for the kernel to protect itself, let's call the SSBD mitigation
> implemented by the higher exception level (either hypervisor or firmware)
> on each transition between userspace and kernel.
>
> We must take the PSCI
On Thu, May 24, 2018 at 12:00:58PM +0100, Mark Rutland wrote:
> On Tue, May 22, 2018 at 04:06:36PM +0100, Marc Zyngier wrote:
> > In order for the kernel to protect itself, let's call the SSBD mitigation
> > implemented by the higher exception level (either hypervisor or firmwa
I guess this may fix the issue I noted with the prior patch,
assuming we only set arm64_ssbd_callback_required for a CPU when the FW
supports the mitigation.
If so, if you fold this together with the prior patch:
Reviewed-by: Mark Rutland <mark.rutl...@arm.com>
Thanks,
Mark.
> ---
> ar
On Wed, May 23, 2018 at 09:42:56AM +0100, Suzuki K Poulose wrote:
> On 03/05/18 14:20, Mark Rutland wrote:
> > +#define __ptrauth_key_install(k, v)\
> > +do { \
> > + write_sysreg_s(v.lo, S
On Fri, May 25, 2018 at 12:08:28PM +0100, Marc Zyngier wrote:
> On 25/05/18 11:50, Mark Rutland wrote:
> > On Thu, May 10, 2018 at 12:13:47PM +0100, Mark Rutland wrote:
> >> For historical reasons, we open-code lm_alias() in kvm_ksym_ref().
> >>
> >> Let's
On Wed, May 23, 2018 at 09:48:28AM +0100, Suzuki K Poulose wrote:
>
> Mark,
>
> On 03/05/18 14:20, Mark Rutland wrote:
> > So that we can dynamically handle the presence of pointer authentication
> > functionality, wire up probing code in cpufeature.c.
> &
On Tue, May 22, 2018 at 04:06:44PM +0100, Marc Zyngier wrote:
> If running on a system that performs dynamic SSBD mitigation, allow
> userspace to request the mitigation for itself. This is implemented
> as a prctl call, allowing the mitigation to be enabled or disabled at
> will for this
offer.d...@arm.com>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Reviewed-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
> ---
> arch/arm/include/asm/kvm_host.h | 12
> arch/arm64/include/asm/kvm_host.h | 23 +++
> arch/ar
ve_cb_end
> + get_vcpu_ptrx2, x0
> + ldr x0, [x2, #VCPU_WORKAROUND_FLAGS]
> +
> + /* Sanitize the argument and update the guest flags*/
Nit: space before the trailing '*/'. Either that or use a '//' comment.
Otherwise, this looks fine, so with that fixed:
Reviewed-by:
gt;
> Reviewed-by: Christoffer Dall <christoffer.d...@arm.com>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Reviewed-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
> ---
> arch/arm64/include/asm/kvm_asm.h | 27 +--
> 1 file changed, 25 inse
On Thu, May 17, 2018 at 11:35:47AM +0100, Marc Zyngier wrote:
> There is no need to perform cache maintenance operations when
> creating the HYP page tables if we have the multiprocessing
> extensions. ARMv7 mandates them with the virtualization support,
> and ARMv8 just mandates them
gt; KVM to disable ARCH_WORKAROUND_2 before entering the guest,
> and enable it when exiting it.
>
> Reviewed-by: Christoffer Dall <christoffer.d...@arm.com>
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Reviewed-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
-off-by: Marc Zyngier <marc.zyng...@arm.com>
Reviewed-by: Mark Rutland <mark.rutl...@arm.com>
[...]
> +static void do_ssbd(bool state)
> +{
> + switch (psci_ops.conduit) {
> + case PSCI_CONDUIT_HVC:
> + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_W
->EL1 exceptions (and as with many other bits of the arm64
code, it's arguably misleading in the VHE case).
Perhaps ARM64_SSBD_KERNEL, which would align with the parameter name?
Not a big deal either way, and otherwise this looks good to me.
Regardless:
Reviewed-by: Mark Rutland <mark.rutl..
out if we're doing dynamic mitigation.
>
> Think of it as a poor man's static key...
I guess in future we can magic up a more general asm static key if we
need them elsewhere.
> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com>
Reviewed-by: Mark Rutland <mark.rutl...@arm.co
flag cannot be flipped while a task is in
userspace:
Reviewed-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
> ---
> arch/arm64/include/asm/thread_info.h | 1 +
> arch/arm64/kernel/entry.S| 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/arch
On Wed, May 30, 2018 at 01:47:01PM +0100, Marc Zyngier wrote:
> Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes
> results in the strongest attribute of the two stages. This means
> that the hypervisor has to perform quite a lot of cache maintenance
> just in case the guest has
On Wed, May 30, 2018 at 01:47:02PM +0100, Marc Zyngier wrote:
> Set/Way handling is one of the ugliest corners of KVM. We shouldn't
> have to handle that, but better safe than sorry.
>
> Thankfully, FWB fixes this for us by not requiering any maintenance
> whatsoever, which means we don't have to
em.
>
> Signed-off-by: Marc Zyngier
Acked-by: Mark Rutland
Mark.
> ---
> arch/arm/include/asm/kvm_mmu.h | 12 ---
> arch/arm64/include/asm/kvm_mmu.h | 3 ---
> virt/kvm/arm/mmu.c | 35
> 3 files changed, 31 inse
andates them unconditionally.
>
> Let's remove these operations.
>
> Signed-off-by: Marc Zyngier
Acked-by: Mark Rutland
Mark.
> ---
> virt/kvm/arm/mmu.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
> index ad1980d2118a
r how the folding logic works for ARM is a pgd entry the
entire pud table?
Assuming so:
Acked-by: Mark Rutland
> +
> static inline pte_t kvm_s2pte_mkwrite(pte_t pte)
> {
> pte_val(pte) |= L_PTE_S2_RDWR;
> diff --git a/arch/arm64/include/asm/kvm_mmu.h
> b/arch/arm64/include
te the
> icache is an unnecessary overhead.
>
> On such systems, we can safely leave the page as being executable.
>
> Acked-by: Catalin Marinas
> Signed-off-by: Marc Zyngier
Acked-by: Mark Rutland
Mark.
> ---
> arch/arm64/include/asm/pgtable-prot.h | 14 --
101 - 200 of 469 matches
Mail list logo