Mark Rutland writes:
> On Tue, Jun 05, 2018 at 08:54:03PM +1000, Michael Ellerman wrote:
>> Mark Rutland writes:
>> > On Tue, Jun 05, 2018 at 11:26:37AM +0200, Peter Zijlstra wrote:
>> >> On Tue, May 29, 2018 at 04:43:35PM +0100, Mark Rutland wrote:
>> >> > /**
>> >> > + * atomic64_add_unless -
snd_soc_card is retrieved as device drvdata during unbind().
Set it as drvdata during bind() to avoid memory corruption during
unbind().
Signed-off-by: Rohit kumar
---
sound/soc/qcom/apq8096.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/qcom/apq8096.c b/sound/soc/qcom/apq8096.c
On Wed, Jun 06, 2018 at 10:04:08AM +0200, Oscar Salvador wrote:
> On Wed, Jun 06, 2018 at 05:16:24AM +, Naoya Horiguchi wrote:
> > On Tue, Jun 05, 2018 at 07:35:01AM +, Horiguchi Naoya(堀口 直也) wrote:
> > > On Mon, Jun 04, 2018 at 06:18:36PM -0700, Matthew Wilcox wrote:
> > > > On Tue, Jun 05
On Fri, Jun 01, 2018 at 03:26:04PM +0800, Aaron Lu wrote:
> On Mon, May 28, 2018 at 07:40:19PM +0800, kernel test robot wrote:
> >
> > Greeting,
> >
> > FYI, we noticed a +23.0% improvement of vm-scalability.throughput due to
> > commit:
> >
> >
> > commit: 309fe96bfc0ae387f53612927a8f0dc3eb05
For x86, there is around 200 vectors left for external device on a
single logic cpu.
Is there any case that we exhaust them in real world, and is it worth to fix?
Thanks,
Pingfan
On Thu, May 24, 2018 at 01:08:48PM -0500, shenwei.w...@nxp.com wrote:
> On the new i.MX8x SoC family, the following changes were made on the FTM
> block:
>
> 1. Need to enable the IPG clock before accessing any FTM registers. Because
> the IPG clock is not an option for FTM counter clock source, i
On Tue, Jun 05, 2018 at 04:07:10PM -0500, Kim Phillips wrote:
> Allow to build coresight as a module. This enhances
> coresight developer efficiency by allowing the development to
> take place exclusively on the target, and without needing to
> reboot in between changes.
>
> - Kconfig becomes a t
Why RFC again:
This series is different from earlier versions[1]. Earlier series
implemented this feature in trace_uprobe while this has implemented
the logic in core uprobe. Few reasons for this:
1. One of the major reason was the deadlock between uprobe_lock and
mm->mmap inside trace_uprobe_mm
On Tue, Jun 05, 2018 at 04:06:59PM -0500, Kim Phillips wrote:
> barrier_pkt[] is used in the etb and tmc-etf coresight
> components. Change barrier_pkt[] to a static definition,
> so as to allow them to be built as modules.
>
> Cc: Mathieu Poirier
> Cc: Leo Yan
> Cc: Alexander Shishkin
> Cc: R
Le Tuesday 05 Jun 2018 à 16:11:29 (+0100), Patrick Bellasi a écrit :
> Hi Vincent,
>
> On 05-Jun 08:57, Vincent Guittot wrote:
> > On 4 June 2018 at 18:06, Patrick Bellasi wrote:
>
> [...]
>
> > > Let's improve the estimated utilization by adding a new "sort-of" PELT
> > > signal, explicitly on
Looks goo, you also updated comments of location of some functions.
Acked-by: Dmitry Kasatkin
Thanks
From: Vasily Averin [v...@virtuozzo.com]
Sent: Friday, June 01, 2018 7:29 PM
To: Andrew Morton; linux-kernel@vger.kernel.org
Cc: Dmitry Kasatkin
Subject:
On Tue, Jun 05, 2018 at 04:06:57PM -0500, Kim Phillips wrote:
> - provide the name of the module in the Kconfig help section
> - define a MODULE_DEVICE_TABLE in order to be autoloaded on boot
>
> Cc: Mathieu Poirier
> Cc: Leo Yan
> Cc: Alexander Shishkin
> Cc: Randy Dunlap
> Cc: Suzuki K Pou
On Tue, Jun 05, 2018 at 04:07:01PM -0500, Kim Phillips wrote:
> Increment the refcnt for driver modules in current use by calling
> module_get in coresight_build_path and module_put in release_path.
>
> This prevents driver modules from being unloaded when they are in use,
> either in sysfs or per
On Tue 05-06-18 20:51:40, Mel Gorman wrote:
[...]
> mremap: Avoid excessive TLB flushing for anonymous pages that are not in swap
> cache
>
> Commit 5d1904204c99 ("mremap: fix race between mremap() and page cleanning")
> fixed races between mremap and other operations for both file-backed and
> a
Currently by default we try to match the user specified PMU
name to all PMU units available and use them to aggregate
all matched PMUs event counts into one 'pattern' event.
While this is useful for uncore events, it screws up names
for other events, where this is not desirable, like:
Before:
#
On Tue, Jun 05, 2018 at 05:30:32PM -0700, Nathan Chancellor wrote:
> On Tue, Jun 05, 2018 at 07:01:05PM +0200, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 4.4.136 release.
> > There are 37 patches in this series, all will be posted as a response
> > to this on
Hi Thomas,
At 06/06/2018 04:04 PM, Thomas Gleixner wrote:
On Wed, 6 Jun 2018, Dou Liyang wrote:
Hi Thomas,
At 06/05/2018 07:41 PM, Thomas Gleixner wrote:
On Tue, 5 Jun 2018, Dou Liyang wrote:
+{
+ if (unlikely(irqd_is_setaffinity_pending(irqd)))
Affinity pending is also judged in
On Fri, May 25, 2018 at 11:08:30PM +0200, Arnd Bergmann wrote:
> Without dmaengine support, we get a harmless warning about an
> unused function:
>
> drivers/pwm/pwm-stm32.c:166:12: error: 'stm32_pwm_capture' defined but not
> used [-Werror=unused-function]
>
> Changing the #ifdef to an IS_ENABL
On Fri, May 25, 2018 at 06:04:54PM +0200, Arnd Bergmann wrote:
> When compile-testing the pwm driver without also enabling the
> stm32_timers MFD, we run into a link error:
>
> drivers/pwm/pwm-stm32.o: In function `stm32_pwm_raw_capture.isra.6':
> pwm-stm32.c:(.text+0xcb0): undefined reference to
Hi Rob,
On Tue, 5 Jun 2018 at 17:23, Rob Herring wrote:
>
> On Mon, Jun 04, 2018 at 12:00:33PM +0200, Clément Péron wrote:
> > From: Clément Peron
> >
> > Add devicetree binding document for NXP's i.MX SoC specific
> > EPIT timer driver.
> >
> > Signed-off-by: Clément Peron
> > ---
> > .../dev
On Tue, Jun 05, 2018 at 04:01:05PM -0600, Shuah Khan wrote:
> On 06/05/2018 11:01 AM, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 4.9.107 release.
> > There are 61 patches in this series, all will be posted as a response
> > to this one. If anyone has any iss
From: Colin Ian King
The pointers vchiq_dbg_dir and vchiq_dbg_clients are local to the
source and do not need to be in global scope, so make them static.
Cleans up sparse warnings:
warning: symbol 'vchiq_dbg_dir' was not declared. Should it be static?
warning: symbol 'vchiq_dbg_clients' was not
On Wed, 6 Jun 2018, Dou Liyang wrote:
> Hi Thomas,
>
> At 06/05/2018 07:41 PM, Thomas Gleixner wrote:
> > On Tue, 5 Jun 2018, Dou Liyang wrote:
> > > > +{
> > > > + if (unlikely(irqd_is_setaffinity_pending(irqd)))
> > >
> > > Affinity pending is also judged in
> > >
> > > > +
On Fri, May 25, 2018 at 06:04:54PM +0200, Arnd Bergmann wrote:
> When compile-testing the pwm driver without also enabling the
> stm32_timers MFD, we run into a link error:
>
> drivers/pwm/pwm-stm32.o: In function `stm32_pwm_raw_capture.isra.6':
> pwm-stm32.c:(.text+0xcb0): undefined reference to
On Wed, Jun 06, 2018 at 05:16:24AM +, Naoya Horiguchi wrote:
> On Tue, Jun 05, 2018 at 07:35:01AM +, Horiguchi Naoya(堀口 直也) wrote:
> > On Mon, Jun 04, 2018 at 06:18:36PM -0700, Matthew Wilcox wrote:
> > > On Tue, Jun 05, 2018 at 12:54:03AM +, Naoya Horiguchi wrote:
> > > > Reproduction
On 05/06/18 19:00, Andi Kleen wrote:
>> +#ifdef CONFIG_X86_64
>> +int arch_get_kallsym(unsigned int symnum, unsigned long *value, char *type,
>> + char *name)
>> +{
>> +unsigned int cpu, ncpu;
>> +
>> +if (symnum >= num_possible_cpus())
>> +return -EINVAL;
>> +
>
On Tue, Jun 05, 2018 at 04:44:04PM +0200, Borislav Petkov wrote:
> Hi guys,
>
> X just froze here ontop of 4.17-rc7+ tip/master (kernel is from last
> week) with the splat at the end.
>
> Box is a x470 chipset with Ryzen 2700X.
>
> GPU gets detected as
>
> [7.440971] [drm] radeon kernel mod
With Micrel KSZ8061 PHY, the link may occasionally not come up after
Ethernet cable connect. The vendor's (Microchip, former Micrel) errata
sheet 8688A.pdf describes the problem and possible workarounds in
detail, see below.
The patch implements workaround 1, which permanently fixes the issue.
On 2018/6/5 19:24, Leizhen (ThunderTown) wrote:
> After I executed "echo 0 > /proc/sys/abi/vsyscall32" to disable vdso, the
> rt_sigaction01 test case from ltp_2015 failed.
> The test case source code please refer to the attachment, and the output as
> blow:
>
> -
> ./rt_sigac
Added notes about the controller and driver
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v9:
- Addressed the comments given by Miquel and Randy
Changes in v8
- None
Changes in v7:
- None
Changes in v6:
- None
Changes in v5:
- Fixed the review comments
Changes in v4:
- None
---
Document
Add driver for arm pl353 static memory controller nand interface with
HW ECC support. This controller is used in xilinx zynq soc for interfacing
the nand flash memory.
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v9:
- Addressed the below comments given by Miquel
- instead of using pl35
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v9:
- Addressed commens given by Randy Dunlap and Miquel Raynal
Changes in v8:
- None
Changes in v7:
- Corrected clocks description
- prefixed '#' for address and size cells
Add driver for arm pl353 static memory controller. This controller is
used in xilinx zynq soc for interfacing the nand and nor/sram memory
devices.
Signed-off-by: Naga Sureshkumar Relli
---
Changes in v9:
- Addressed the comments given by Julia Cartwright to the v8 series.
Changes in v8:
- None
The following patches add arm pl353 static memory controller driver and nand
driver
for xilinx zynq soc. The arm pl353 smc supports two interfaces i.e nand and
nor/sram
memory interfaces. The current implementation supports only a single SMC
instance and nand specific configuration.
xilinx zynq
On Tue, 5 Jun 2018, Josh Poimboeuf wrote:
> On Tue, Jun 05, 2018 at 09:17:52AM +0200, Miroslav Benes wrote:
> > On Mon, 4 Jun 2018, Josh Poimboeuf wrote:
> >
> > > On Mon, Jun 04, 2018 at 04:16:35PM +0200, Miroslav Benes wrote:
> > > > An administrator may send a fake signal to all remaining bloc
On Tue, 2018-06-05 at 16:53 -0700, Joel Fernandes wrote:
> (Resending since Andy wasn't on CC - sorry)
> Andy, previously made some suggestions to this patch. The updated
> version is
> below and I am planning to send it along with this series as v9. I
> have
> included it in advance below for you
Hi Andy,
On Wed, Jun 6, 2018 at 8:58 AM Ricardo Ribalda Delgado
wrote:
>
> Hi Andy
> On Tue, Jun 5, 2018 at 3:42 PM Andy Shevchenko
> wrote:
> >
> > On Tue, May 29, 2018 at 4:10 PM, Ricardo Ribalda Delgado
> > wrote:
> > > Standard TTY port that can be loaded/unloaded via serdev sysfs. This
> >
On Tue, 2018-06-05 at 10:39 -0700, Linus Torvalds wrote:
> On Tue, Jun 5, 2018 at 10:30 AM Linus Torvalds
> wrote:
> >
> > Honestly, this looks questionable to me.
> >
> > I'm not talking about the changes themselves - I can live with them.
> > But the _rationale_ is pure and utter garbage, and
On Tue, Jun 05, 2018 at 04:58:43PM +0300, Andy Shevchenko wrote:
> On Tue, May 29, 2018 at 1:02 PM, Matti Vaittinen
> wrote:
> > Support for controlling the 8 bucks and 7 LDOs the PMIC contains.
>
Thanks for the comments Andy. The regulator part of patch set v4 was
already applied by Mark but
On Tue, Jun 05, 2018 at 10:46:14AM -0500, Rob Herring wrote:
> On Mon, Jun 4, 2018 at 6:32 AM, Matti Vaittinen
> wrote:
> > On Fri, Jun 01, 2018 at 12:32:16PM -0500, Rob Herring wrote:
> >> On Fri, Jun 1, 2018 at 1:25 AM, Matti Vaittinen
> >> wrote:
> >> > On Thu, May 31, 2018 at 09:07:24AM -0500
On Wed 2018-06-06 07:33:32, H. Nikolaus Schaller wrote:
> Hi,
>
> > Am 05.06.2018 um 22:39 schrieb Pavel Machek :
> >
> > On Tue 2018-06-05 18:37:21, Andy Shevchenko wrote:
> >> On Wed, May 23, 2018 at 5:06 PM, Pavel Machek wrote:
> >>> On Thu 2018-05-17 06:59:49, H. Nikolaus Schaller wrote:
> >
Hi Rob,
On Tue, 5 Jun 2018 14:11:02 -0600
Rob Herring wrote:
> On Fri, Jun 01, 2018 at 12:16:33AM +0200, Stefan Agner wrote:
> > Allow to define a NAND chip as a boot device. This can be helpful
> > for the selection of the ECC algorithm and strength in case the boot
> > ROM supports only a subs
Hi Andy,
On Tue, Jun 5, 2018 at 3:44 PM Andy Shevchenko
wrote:
>
> On Tue, May 29, 2018 at 4:10 PM, Ricardo Ribalda Delgado
> wrote:
> > If a serdev ttyport controller does not have an acpi nor an of child,
> > create a ttydev as a child of that controller.
> >
> > Doing this allows the removal,
On Tue, Jun 05, 2018 at 06:33:04PM -0700, Dan Williams wrote:
> Unless the nouveau patches are using the entirety of what is already
> upstream for HMM, we should look to pare HMM back.
>
> There is plenty of precedent of building a large capability
> out-of-tree and piecemeal merging it later, so
Add an interface to invalidate intermediate page tables
from TLB for kernel.
Signed-off-by: Chintan Pandya
---
arch/arm64/include/asm/tlbflush.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h
b/arch/arm64/include/asm/tlbflush.h
index dfc61d7..a4a190
From: Chintan Pandya
The following kernel panic was observed on ARM64 platform due to a stale
TLB entry.
1. ioremap with 4K size, a valid pte page table is set.
2. iounmap it, its pte entry is set to 0.
3. ioremap the same address with 2M size, update its pmd entry with
a new value.
4. C
arm64 requires break-before-make. Originally, before
setting up new pmd/pud entry for huge mapping, in few
cases, the modifying pmd/pud entry was still valid
and pointing to next level page table as we only
clear off leaf PTE in unmap leg.
a) This was resulting into stale entry in TLBs (as few
This series of patches re-bring huge vmap back for arm64.
Patch 1/3 has been taken by Toshi in his series of patches
by name "[PATCH v3 0/3] fix free pmd/pte page handlings on x86"
to avoid merge conflict with this series.
These patches are tested on 4.16 kernel with Cortex-A75 based SoC.
The te
On Mon, Jun 4, 2018 at 8:26 PM, Ravi Chandra Sadineni
wrote:
> Currently ACPI LID increments wakeup count irrespective of the wake source.
> This is because we call acpi_lid_initialize_state on every resume.
I don't quite understand the connection between the two sentences
above. Care to clarify
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