Davidlohr Bueso wrote:
> On Mon, 22 Aug 2022, Dan Williams wrote:
>
> >Davidlohr Bueso wrote:
> >> On Sun, 21 Aug 2022, Christoph Hellwig wrote:
> >>
> >> >On Fri, Aug 19, 2022 at 10:10:24AM -0700, Davidlohr Bueso wrote:
> >> >> index b192d917a6d0..ac4d4fd4e508 100644
> >> >> --- a/arch/x86/includ
> What I'm missing from this text here is, what *is* the mce->misc LSB
> field in human speak? What does that field denote?
The SDM says:
Recoverable Address LSB (bits 5:0): The lowest valid recoverable address bit.
Indicates the position of the least
significant bit (LSB) of the recoverable e
>>> I suppose this wants to go upstream via the tree the bug came from
(NVDIMM
>>> tree? ACPI tree?), or should we pick it up into the x86 tree?
>>
>> No idea. Maintainers?
>
> There's no real NVDIMM dependency here, just a general cleanup of how
> APEI error granularities are managed. So
On Mon, 22 Aug 2022, Dan Williams wrote:
Davidlohr Bueso wrote:
On Sun, 21 Aug 2022, Christoph Hellwig wrote:
>On Fri, Aug 19, 2022 at 10:10:24AM -0700, Davidlohr Bueso wrote:
>> index b192d917a6d0..ac4d4fd4e508 100644
>> --- a/arch/x86/include/asm/cacheflush.h
>> +++ b/arch/x86/include/asm/ca
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