On Fri, Aug 28, 2020 at 12:14:28PM +1000, Michael Ellerman wrote:
> Dmitry Safonov <0x7f454...@gmail.com> writes:
> > On Wed, 26 Aug 2020 at 15:39, Michael Ellerman wrote:
> >> Christophe Leroy writes:
> >> We added a test for vdso unmap recently because it happened to trigger a
> >> KAUP failure
On Wed, Jul 29, 2020 at 01:11:20PM +0200, pet...@infradead.org wrote:
> On Tue, Jul 28, 2020 at 11:56:38AM +0100, David Howells wrote:
> > Peter Zijlstra wrote:
> >
> > > > Please do not _undo_ the changes; just add the API you need.
> > >
> > > add_return and sub_return are horrible interface f
Hi Anthony,
On Sun, Sep 20, 2020 at 03:25:23AM -0700, Anthony Steinhauser wrote:
> > As a heads up: I'm currently reworking most of this, and hope to post
> > something within the next two weeks.
>
> Sure. Let me know whether you want to implement the
> PR_SPEC_DISABLE_NOEXEC support directly or
On Tue, 15 Sep 2020 16:41:09 -0400, Mark Salter wrote:
> This splat was reported on newer Fedora kernels booting on certain
> X-gene based machines:
>
> xgene-pmu APMC0D83:00: X-Gene PMU version 3
> Unable to handle kernel read from unreadable memory at virtual \
> address 4006
> .
On Fri, 18 Sep 2020 03:33:12 +, Clint Sbisa wrote:
> This change exposes write-combine mappings under sysfs for
> prefetchable PCI resources on arm64.
>
> Originally, the usage of "write combine" here was driven by the x86
> definition of write combine. This definition is specific to x86 and
>
On Fri, 18 Sep 2020 11:47:11 +0100, Boyan Karatotev wrote:
> Pointer Authentication (PAuth) is a security feature introduced in ARMv8.3.
> It introduces instructions to sign addresses and later check for potential
> corruption using a second modifier value and one of a set of keys. The
> signature,
On Mon, 14 Sep 2020 16:34:06 +0100, Mark Brown wrote:
> This series updates the arm64 stacktrace code to use the newer and much
> simpler arch_stack_walk() interface, the main benefit being a single
> entry point to the arch code with no need for the arch code to worry
> about skipping frames. Alon
On Sat, Sep 19, 2020 at 12:35:48AM +0900, Sergey Senozhatsky wrote:
> ipi_teardown() is used only when CONFIG_HOTPLUG_CPU is set.
>
> Signed-off-by: Sergey Senozhatsky
> ---
> arch/arm64/kernel/smp.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
I think this is a duplicate of:
h
ing: Excess function parameter 'kvm'
> description in 'stage2_wp_range'
>
> Signed-off-by: Xiaofei Tan
> ---
> arch/arm64/kvm/mmu.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
Acked-by: Will Deacon
Will
On Fri, Sep 18, 2020 at 02:21:36AM -0700, Bailu Lin wrote:
> This is a Chinese translated version of Documentation/arm64/amu.rst
>
> Signed-off-by: Bailu Lin
> ---
> Changes in v2:
> - Add index to arm64 directoy.
> - Fix a document format error.
> - Correct email encoding format.
> ---
> Doc
create mode 100644 Documentation/translations/zh_CN/arm64/index.rst
Acked-by: Will Deacon
I'm assuming Jon will pick this one up.
Cheers,
Will
On Wed, Sep 16, 2020 at 06:34:38PM +0100, David Brazdil wrote:
> Add hyp percpu section to linker script and rename the corresponding ELF
> sections of hyp/nvhe object files. This moves all nVHE-specific percpu
> variables to the new hyp percpu section.
>
> Allocate sufficient amount of memory for
On Wed, Sep 16, 2020 at 06:34:37PM +0100, David Brazdil wrote:
> In preparation for unmapping hyp pages from host stage-2, allocate/free hyp
> stack using new helpers which automatically mark the pages reserved.
Given that this series doesn't get us that the point of having a stage-2 for
the host,
On Wed, Sep 16, 2020 at 06:34:35PM +0100, David Brazdil wrote:
> Hyp keeps track of which cores require SSBD callback by accessing a
> kernel-proper global variable. Create an nVHE symbol of the same name
> and copy the value from kernel proper to nVHE at KVM init time.
>
> Done in preparation for
de(void)
> for_each_possible_cpu(cpu) {
> kvm_host_data_t *cpu_data;
>
> - cpu_data = per_cpu_ptr(&kvm_host_data, cpu);
> + cpu_data = per_cpu_ptr_hyp(kvm_host_data, cpu);
I stand by my earlier comment to add _sym here, given that the ampersand
gets dropped from the argument.
So assuming you do that in the earlier patch:
Acked-by: Will Deacon
Will
yp_mode() should avoid read_sysreg()
and instead use a non-volatile asm to allow the result to be cached by
the compiler. Hmm.
But I think that can be tackled as a future patch, so with the naming nits
resolved:
Acked-by: Will Deacon
Will
2
.endm
#else
.macro this_cpu_offset, dst
alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
mrs \dst, tpidr_el1
alternative_else
mrs \dst, tpidr_el2
alternative_endif
.endm
#endif
(and should we have a shorthand __HYPERVISOR define to avoid the NVHE || VHE
logic?)
With that:
Acked-by: Will Deacon
Will
4 insertions(+)
It's also useful because we're about to add another entry here, so:
Acked-by: Will Deacon
Will
On Wed, Sep 16, 2020 at 06:34:32PM +0100, David Brazdil wrote:
> this_cpu_ptr is meant for use in kernel proper because it selects between
> TPIDR_EL1/2 based on nVHE/VHE. __hyp_this_cpu_ptr was used in hyp to always
> select TPIDR_EL2. Unify all users behind this_cpu_ptr and friends by
> selecting
> arch/arm64/include/asm/kvm_asm.h | 8 +---
> arch/arm64/kernel/image-vars.h | 2 --
> 3 files changed, 13 insertions(+), 9 deletions(-)
Acked-by: Will Deacon
Will
comment below for more info.
> -ccflags-y += $(call cc-option,-fno-reorder-functions)
> +# 2) Compile linker script.
> +$(obj)/hyp.lds: $(src)/hyp.lds.S FORCE
> + $(call if_changed_dep,cpp_lds_S)
You need a .gitignore file listing hyp.lds, otherwise some idiot will end
up committing it. I definitely didn't do that when playing around with this
series. Nope. Not at all.
With that, and the regex resolved:
Acked-by: Will Deacon
Will
ing the arm instruction offsets.
>
> Fixes: 2589726d12a1 ("bpf: introduce bounded loops")
> Reported-by: Naresh Kamboju
> Reported-by: Jiri Olsa
> Co-developed-by: Jean-Philippe Brucker
> Signed-off-by: Jean-Philippe Brucker
> Co-developed-by: Yauheni Kaliuta
> Signed-off-by: Yauheni Kaliuta
> Signed-off-by: Ilias Apalodimas
Acked-by: Will Deacon
Catalin -- do you want to take this as a fix?
Will
On Wed, Sep 16, 2020 at 08:32:20PM +0800, Hou Tao wrote:
> > Subject: locking/percpu-rwsem: Use this_cpu_{inc,dec}() for read_count
> > From: Hou Tao
> > Date: Tue, 15 Sep 2020 22:07:50 +0800
> >
> > From: Hou Tao
> >
> > The __this_cpu*() accessors are (in general) IRQ-unsafe which, given
> >
On Wed, Sep 16, 2020 at 01:24:12PM +0100, David Brazdil wrote:
> > I was also wondering about another approach - using the PERCPU_SECTION macro
> > unchanged in the hyp linker script. It would lay out a single .data..percpu
> > and
> > we would then prefix it with .hyp and the symbols with __kvm_n
On Tue, Sep 15, 2020 at 09:57:01PM -0700, Bailu Lin wrote:
> Add filesystems subdirectory into the table of Contents for zh_CN,
> all translations residing on it would be indexed conveniently.
Sorry, I don't understand the reference to "filesystems" here. Is this
a copy-paste of a different commit
On Wed, Sep 16, 2020 at 10:00:39AM +0800, Xiaofei Tan wrote:
> Fix following warnings caused by mismatch bewteen function parameters
> and comments.
> arch/arm64/kvm/mmu.c:128: warning: Function parameter or member 'mmu' not
> described in '__unmap_stage2_range'
> arch/arm64/kvm/mmu.c:128: warning
On Wed, Sep 16, 2020 at 01:25:23PM +1000, Gavin Shan wrote:
> This enables color zero pages by allocating contigous page frames
> for it. The number of pages for this is determined by L1 dCache
> (or iCache) size, which is probbed from the hardware.
>
>* Add cache_total_size() to return L1 dCa
On Tue, Sep 15, 2020 at 08:11:12PM +0200, pet...@infradead.org wrote:
> On Tue, Sep 15, 2020 at 05:11:23PM +0100, Will Deacon wrote:
> > On Tue, Sep 15, 2020 at 06:03:44PM +0200, pet...@infradead.org wrote:
> > > On Tue, Sep 15, 2020 at 05:51:50PM +0200, pet...@i
On Tue, Sep 15, 2020 at 04:53:44PM +0300, Ilias Apalodimas wrote:
> On Tue, Sep 15, 2020 at 02:11:03PM +0100, Will Deacon wrote:
> > Hi Ilias,
> >
> > On Mon, Sep 14, 2020 at 07:03:55PM +0300, Ilias Apalodimas wrote:
> > > Running the eBPF test_verifier leads to r
quot;)
> Signed-off-by: Hou Tao
> Signed-off-by: Peter Zijlstra (Intel)
> Link: https://lkml.kernel.org/r/20200915140750.137881-1-hout...@huawei.com
> ---
> include/linux/percpu-rwsem.h |8
> kernel/locking/percpu-rwsem.c |4 ++--
> 2 files changed, 6 insertions(+), 6 deletions(-)
For the patch:
Acked-by: Will Deacon
Will
On Mon, Sep 14, 2020 at 10:42:13PM +0200, Thomas Gleixner wrote:
> CONFIG_PREEMPT_COUNT is now unconditionally enabled and will be
> removed. Cleanup the leftovers before doing so.
>
> Signed-off-by: Thomas Gleixner
> Cc: Peter Zijlstra
> Cc: Ingo Molnar
> Cc: Will Dea
On Mon, 14 Sep 2020 11:04:16 -0700, Tuan Phan wrote:
> Add support for probing device from ACPI node.
> Each DSU ACPI node and its associated cpus are inside a cluster node.
Applied to will (for-next/perf), thanks!
[1/1] perf: arm_dsu: Support DSU ACPI devices
https://git.kernel.org/will/c/
n test_bit(bitnum, addr);
> -#elif defined CONFIG_PREEMPT_COUNT
> - return preempt_count();
> #else
> - return 1;
> + return preempt_count();
> #endif
Acked-by: Will Deacon
Will
Hi Ilias,
On Mon, Sep 14, 2020 at 07:03:55PM +0300, Ilias Apalodimas wrote:
> Running the eBPF test_verifier leads to random errors looking like this:
>
> [ 6525.735488] Unexpected kernel BRK exception at EL1
> [ 6525.735502] Internal error: ptrace BRK handler: f2000100 [#1] SMP
Does this happen
Hi David,
On Thu, Sep 03, 2020 at 11:17:02AM +0200, David Brazdil wrote:
> Introduce '.hyp.data..percpu' as part of ongoing effort to make nVHE
> hyp code self-contained and independent of the rest of the kernel.
>
> The series builds on top of the "Split off nVHE hyp code" series which
> used ob
On Mon, 14 Sep 2020 09:47:30 +1000, Gavin Shan wrote:
> The function __{pgd, pud, pmd, pte}_error() are introduced so that
> they can be called by {pgd, pud, pmd, pte}_ERROR(). However, some
> of the functions could never be called when the corresponding page
> table level isn't enabled. For exampl
Hi Ilias,
On Mon, Sep 14, 2020 at 04:23:50PM +0300, Ilias Apalodimas wrote:
> On Mon, Sep 14, 2020 at 03:35:04PM +0300, Ilias Apalodimas wrote:
> > On Mon, Sep 14, 2020 at 01:20:43PM +0100, Will Deacon wrote:
> > > On Mon, Sep 14, 2020 at 11:36:21AM +0300, Ilias Apalodimas wrot
On Mon, Sep 14, 2020 at 09:13:39AM -0400, Mark Salter wrote:
> On Mon, 2020-09-14 at 12:28 +0100, Will Deacon wrote:
> > On Sun, Sep 13, 2020 at 01:45:36PM -0400, Mark Salter wrote:
> > > @@ -1483,11 +1473,23 @@ xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct
> >
On Mon, Sep 14, 2020 at 09:51:31PM +0900, Masahiro Yamada wrote:
> On Sat, Sep 12, 2020 at 12:22 AM Will Deacon wrote:
> > On Thu, Sep 10, 2020 at 10:51:17PM +0900, Masahiro Yamada wrote:
> > > The minimal compiler versions, GCC 4.9 and Clang 10 support this flag.
> > >
On Thu, Sep 03, 2020 at 11:17:04AM +0200, David Brazdil wrote:
> Previous series introduced custom build rules for nVHE hyp code, using
> objcopy to prefix ELF section and symbol names to separate nVHE code
> into its own "namespace". This approach was limited by the expressiveness
> of objcopy's c
On Mon, Sep 14, 2020 at 11:36:21AM +0300, Ilias Apalodimas wrote:
> Running the eBPF test_verifier leads to random errors looking like this:
>
> [ 6525.735488] Unexpected kernel BRK exception at EL1
> [ 6525.735502] Internal error: ptrace BRK handler: f2000100 [#1] SMP
> [ 6525.741609] Modules lin
On Sun, Sep 13, 2020 at 01:45:36PM -0400, Mark Salter wrote:
> @@ -1483,11 +1473,23 @@ xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(struct
> xgene_pmu *xgene_pmu,
> return NULL;
>
> INIT_LIST_HEAD(&resource_list);
> - rc = acpi_dev_get_resources(adev, &resource_list,
> -
On Mon, Aug 31, 2020 at 12:04:46PM +0100, Boyan Karatotev wrote:
> Pointer Authentication (PAuth) is a security feature introduced in ARMv8.3.
> It introduces instructions to sign addresses and later check for potential
> corruption using a second modifier value and one of a set of keys. The
> sign
On Thu, 10 Sep 2020 19:59:34 +1000, Gavin Shan wrote:
> The macro was introduced by commit ("arm64: PTE/PMD
> contiguous bit definition") at the beginning. It's only used by
> commit <348a65cdcbbf> ("arm64: Mark kernel page ranges contiguous"),
> which was reverted later by commit <667c27597ca8>.
On Thu, Sep 10, 2020 at 10:51:17PM +0900, Masahiro Yamada wrote:
> The minimal compiler versions, GCC 4.9 and Clang 10 support this flag.
>
> Here is the godbolt:
> https://godbolt.org/z/odq8h9
>
> Signed-off-by: Masahiro Yamada
> ---
>
> Makefile | 2 +-
> arch/arm64/
On Wed, 9 Sep 2020 10:23:01 +0530, Anshuman Khandual wrote:
> This series enables THP migration on arm64 via ARCH_ENABLE_THP_MIGRATION.
> But first this modifies all existing THP helpers like pmd_present() and
> pmd_trans_huge() etc per expected generic memory semantics as concluded
> from a previo
On Wed, 9 Sep 2020 11:18:55 +0530, Anshuman Khandual wrote:
> HWCAP name arrays (hwcap_str, compat_hwcap_str, compat_hwcap2_str) that are
> scanned for /proc/cpuinfo are detached from their bit definitions making it
> vulnerable and difficult to correlate. It is also bit problematic because
> durin
On Tue, Sep 08, 2020 at 02:37:22PM -0400, Mark Salter wrote:
> On Mon, 2020-09-07 at 14:50 +0100, Will Deacon wrote:
> > On Wed, Sep 02, 2020 at 02:27:29PM -0400, Mark Salter wrote:
> > > diff --git a/drivers/perf/xgene_pmu.c b/drivers/perf/xgene_pmu.c
> > > index edac28
On Fri, Sep 11, 2020 at 05:03:06PM +0100, Robin Murphy wrote:
> BTW am I supposed to have received 3 copies of everything? Because I did...
Yeah, this seems to be happening for all of Sai's emails :/
Will
operations, _relaxed functions,
> but not atomic_read or atomic_set. A common example where a memory
> barrier may be required is when atomic ops are used for reference
The document remains unreadable, but this is still worth fixing!
Acked-by: Will Deacon
Will
On Tue, Sep 08, 2020 at 10:43:12AM +0530, Anshuman Khandual wrote:
>
>
> On 09/07/2020 05:46 PM, Will Deacon wrote:
> > On Mon, Aug 17, 2020 at 05:34:23PM +0530, Anshuman Khandual wrote:
> >> HWCAP name arrays (hwcap_str, compat_hwcap_str, compat_hwcap2_str) that ar
On Sat, 29 Aug 2020 14:00:16 +0100, Valentin Schneider wrote:
> In the absence of ACPI or DT topology data, we fallback to haphazardly
> decoding *something* out of MPIDR. Sadly, the contents of that register are
> mostly unusable due to the implementation leniancy and things like Aff0
> having to
Modulo my horrible grammar nit on the last patch:
Acked-by: Will Deacon
Thanks!
Will
On Wed, Sep 02, 2020 at 03:59:11PM -0700, Nick Desaulniers wrote:
> As Kees suggests, doing so provides developers with two useful pieces of
> information:
I struggle to parse this. "doing so" what? These things are supposed to
be in the imperative.
Will
On Fri, 4 Sep 2020 14:00:59 +0530, Anshuman Khandual wrote:
> Kernel virtual region [BPF_JIT_REGION_START..BPF_JIT_REGION_END] is missing
> from address_markers[], hence relevant page table entries are not displayed
> with /sys/kernel/debug/kernel_page_tables. This adds those missing markers.
> Whi
[+ Suzuki as I'd like his Ack on this]
On Fri, Aug 14, 2020 at 05:39:40PM -0700, Tuan Phan wrote:
> Add support for probing device from ACPI node.
> Each DSU ACPI node and its associated cpus are inside a cluster node.
>
> Signed-off-by: Tuan Phan
> ---
> Changes in v3:
> - Based on the latest A
which is not expected on arm64.
>
> Cc: Catalin Marinas
> Cc: Will Deacon
> Cc: Mark Brown
> Cc: Dave Martin
> Cc: Ard Biesheuvel
> Cc: Mark Rutland
> Cc: Suzuki K Poulose
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-
On Fri, Jul 24, 2020 at 05:16:04PM +0800, Wei Li wrote:
> Armv8.3 extends the SPE by adding:
> - Alignment field in the Events packet, and filtering on this event
> using PMSEVFR_EL1.
> - Support for the Scalable Vector Extension (SVE).
>
> The main additions for SVE are:
> - Recording the vecto
On Fri, 4 Sep 2020 17:57:38 +0800, Qi Liu wrote:
> event_idx is obtained from armv8pmu_get_event_idx(), and this idx must be
> between ARMV8_IDX_CYCLE_COUNTER and cpu_pmu->num_events. So it's unnecessary
> to do this check. Let's remove it.
Applied to will (for-next/perf), thanks!
[1/1] arm64: pe
On Fri, Jul 17, 2020 at 04:05:32AM -0700, Anthony Steinhauser wrote:
> For x64 it was already implemented in:
> https://github.com/torvalds/linux/commit/71368af
>
> The rationale is the same as for the x64 implementation.
>
> Signed-off-by: Anthony Steinhauser
> ---
>
> It's actively attempted
On Wed, Sep 02, 2020 at 02:27:29PM -0400, Mark Salter wrote:
> diff --git a/drivers/perf/xgene_pmu.c b/drivers/perf/xgene_pmu.c
> index edac28cd25dd..fdbbd0804b92 100644
> --- a/drivers/perf/xgene_pmu.c
> +++ b/drivers/perf/xgene_pmu.c
> @@ -1483,6 +1483,7 @@ xgene_pmu_dev_ctx *acpi_get_pmu_hw_inf(
On Fri, Aug 07, 2020 at 12:16:35PM -0700, Sultan Alsawaf wrote:
> From: Sultan Alsawaf
>
> There's no reason to hold an RCU read lock the entire time while
> optimistically spinning for a mutex lock. This can needlessly lengthen
> RCU grace periods and slow down synchronize_rcu() when it doesn't
On Fri, 28 Aug 2020 11:18:22 +0800, Xiaoming Ni wrote:
>
Applied to arm64 (for-next/tpyos), thanks!
[1/1] arm64: fix some spelling mistakes in the comments by codespell
https://git.kernel.org/arm64/c/ad14c19242b5
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://wi
On Wed, 26 Aug 2020 22:17:58 +0800, Zenghui Yu wrote:
> The actual size of level-1 stream table is l1size. This looks like an
> oversight on commit d2e88e7c081ef ("iommu/arm-smmu: Fix LOG2SIZE setting
> for 2-level stream tables") which forgot to update the @size in error
> message as well.
>
> As
On Tue, 4 Aug 2020 16:53:47 +0800, Yue Hu wrote:
> Currently, there are different description strings in die() such as
> die("Oops",,), die("Oops - BUG",,). And panic() called by die() will
> always show "Fatal exception" or "Fatal exception in interrupt".
>
> Note that panic() will run any panic
On Tue, 18 Aug 2020 14:36:23 +0800, Zenghui Yu wrote:
> * From v1 [1]:
> - As pointed out by Hanjun, remove two now unused inline functions.
> Compile tested with CONFIG_IOMMU_API is not selected.
>
> [1] https://lore.kernel.org/r/20200817105946.1511-1-yuzeng...@huawei.com
>
> Zenghui Yu (2
On Tue, 11 Aug 2020 13:35:05 +0800, Leo Yan wrote:
> This patch is to add the general hardware last level cache (LLC) events
> for PMUv3: one event is for LLC access and another is for LLC miss.
>
> With this change, perf tool can support last level cache profiling,
> below is an example to demons
On Tue, 1 Sep 2020 17:11:54 +0800, yanfei...@windriver.com wrote:
> Fix a typo in comment of arm64_numa_init. 'encomapssing' should
> be 'encompassing'.
Applied to arm64 (for-next/tpyos), thanks!
[1/1] arm64/numa: Fix a typo in comment of arm64_numa_init
https://git.kernel.org/arm64/c/9a747
rch/*/kernel/module.lds to arch/*/include/asm/module.lds.h,
> which is included from scripts/module.lds.S.
>
> scripts/module.lds is fine because 'make clean' keeps all the build
> artifacts under scripts/.
>
> You can add arch-specific sections in .
>
> Si
On Wed, Aug 19, 2020 at 09:55:05PM +0200, Sebastian Andrzej Siewior wrote:
> The bits PF_IO_WORKER and PF_WQ_WORKER are tested together in
> sched_submit_work() which is considered to be a hot path.
> If the two bits cross the 8 or 16 bit boundary then most architecture
> require multiple load inst
Hi Oli,
Thanks for this. Just a few high-level comments below.
On Wed, Jul 01, 2020 at 09:12:49AM +0100, Oli Swede wrote:
> > Version 3 addressed this but I later found some issues with the fixup
> > correctness after further testing, and have partially re-written them
> > here, and addressed som
On Wed, Sep 02, 2020 at 05:17:43PM +0800, Hanjun Guo wrote:
> +Cc Will
>
> On 2020/8/18 17:16, Hanjun Guo wrote:
> > On 2020/8/18 14:36, Zenghui Yu wrote:
> > > * From v1 [1]:
> > > - As pointed out by Hanjun, remove two now unused inline functions.
> > > Compile tested with CONFIG_IOMMU_A
On Wed, Sep 02, 2020 at 09:22:53AM +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2020-09-01 at 13:37 -0500, Bjorn Helgaas wrote:
> > On Mon, Aug 31, 2020 at 03:18:27PM +, Clint Sbisa wrote:
> > > Using write-combine is crucial for performance of PCI devices where
> > > significant amounts of t
Hi Will, Pablo,
On Tue, Aug 04, 2020 at 01:37:11PM +0200, Pablo Neira Ayuso wrote:
> This patch is much smaller and if you confirm this is address the
> issue, then this is awesome.
Did that ever get confirmed? AFAICT, nothing ended up landing in the stable
trees for this.
Cheers,
Will
> On M
On Mon, Aug 31, 2020 at 11:46:51AM +0200, Jessica Yu wrote:
> +++ Will Deacon [21/08/20 13:30 +0100]:
> [snipped]
> > > > > > So module_enforce_rwx_sections() is already called after
> > > > > > module_frob_arch_sections() - which really baffled me at fir
wed-by: Kees Cook
> Reviewed-by: Nathan Chancellor
> Tested-by: Gustavo A. R. Silva
> Tested-by: Nathan Chancellor
> Signed-off-by: Nick Desaulniers
> ---
> Changes V1 -> V2:
> * fix typo, as per Will.
> * add link to getting LLVM, as per Nathan.
> * collect tags.
Acked-by: Will Deacon
Will
On Thu, Aug 27, 2020 at 03:28:48PM +0100, Al Viro wrote:
> On Thu, Aug 27, 2020 at 06:19:44PM +0800, Shaokun Zhang wrote:
> > From: Yuqi Jin
> >
> > It is well known that the performance of atomic_add is better than that of
> > atomic_cmpxchg.
> > The initial value of @f_count is 1. While @f_coun
On Tue, Aug 25, 2020 at 03:25:51PM -0700, Nick Desaulniers wrote:
> Based on a vote at the LLVM BoF at Plumbers 2020, we decided to start
> small, supporting just one formal upstream release of LLVM for now.
>
> We can probably widen the support window of supported versions over
> time. Also, not
Hi Florian,
On Fri, Aug 21, 2020 at 10:16:23AM -0700, Florian Fainelli wrote:
> On 8/21/20 9:03 AM, Will Deacon wrote:
> > On Fri, Aug 07, 2020 at 03:14:29PM +0200, Greg KH wrote:
> >> On Thu, Aug 06, 2020 at 01:00:54PM -0700, Florian Fainelli wrote:
> >>> Greg,
stage2_pgd")
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
Message-Id: <20200811102725.7121-3-w...@kernel.org>
Signed-off-by: Paolo Bonzini
Signed-off-by: Will Deacon
---
virt/kvm/arm/mmu.c | 17 +
1 file changed, 13 insertions(+),
# v5.7 only
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
Message-Id: <20200811102725.7121-2-w...@kernel.org>
Signed-off-by: Paolo Bonzini
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/mips/include/asm/kvm_h
# v5.8 only
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
Message-Id: <20200811102725.7121-2-w...@kernel.org>
Signed-off-by: Paolo Bonzini
Signed-off-by: Will Deacon
---
arch/arm64/include/asm/kvm_host.h | 2 +-
arch/arm64/kvm/mmu.c
stage2_pgd")
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
Message-Id: <20200811102725.7121-3-w...@kernel.org>
Signed-off-by: Paolo Bonzini
Signed-off-by: Will Deacon
---
virt/kvm/arm/mmu.c | 17 +
1 file changed, 13 insertions(+),
stage2_pgd")
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
Message-Id: <20200811102725.7121-3-w...@kernel.org>
Signed-off-by: Paolo Bonzini
Signed-off-by: Will Deacon
---
arch/arm64/kvm/mmu.c | 17 +
1 file changed, 13 insertion
# v5.4 only
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
Message-Id: <20200811102725.7121-2-w...@kernel.org>
Signed-off-by: Paolo Bonzini
Signed-off-by: Will Deacon
---
arch/arm/include/asm/kvm_host.h | 2 +-
arch/arm64/include/asm/kvm_ho
or not they are permitted to block.
Cc: # v4.19 only
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
Message-Id: <20200811102725.7121-2-w...@kernel.org>
Signed-off-by: Paolo Bonzini
[will: Backport to 4.19; use 'blockable' instead of non-exi
_pgd")
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
Message-Id: <20200811102725.7121-3-w...@kernel.org>
Signed-off-by: Paolo Bonzini
[will: Backport to 4.19; use 'blockable' instead of non-existent
MMU_NOTIFIER_RANGE_BLOCKABLE flag]
Signe
ad just remove the conditional
reschedule.
Cc: # v4.9 only
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
---
arch/arm/kvm/mmu.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index bb0d5e21d60b..b5ce1e81f945 1
ad just remove the conditional
reschedule.
Cc: # v4.14 only
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
---
virt/kvm/arm/mmu.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index 3814cdad643a..7fe673248e98 1
ad just remove the conditional
reschedule.
Cc: # v4.4 only
Cc: Marc Zyngier
Cc: Suzuki K Poulose
Cc: James Morse
Signed-off-by: Will Deacon
---
arch/arm/kvm/mmu.c | 8
1 file changed, 8 deletions(-)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index e0267532bd4e..edd392fdc14b 1
gt; Signed-off-by: Lukas Bulwahn
> ---
> Will, please ack.
Typo in subject: s/SSMU/SMMU/
With that:
Acked-by: Will Deacon
> Joerg, please pick this minor non-urgent patch for your -next branch.
Joerg -- can you queue this as a fix for 5.9-rc, please?
Thanks,
Will
t 12:50:23PM -0700, Florian Fainelli wrote:
> > >>> From: Will Deacon
> > >>>
> > >>> commit 679db70801da9fda91d26caf13bf5b5ccc74e8e8 upstream
> > >>>
> > >>> Some CPUs can speculate past an ERET instruction and potentia
3666313.0 lps (10.0 s, 1
> samples)
>
> System Benchmarks Partial Index BASELINE RESULTINDEX
> System Call Overhead 15000.03666313.0 2444.2
>
Hi Kees,
On Sun, Jun 28, 2020 at 11:18:23PM -0700, Kees Cook wrote:
> v4:
> - explicitly add .ARM.attributes
> - split up arm64 changes into separate patches
> - split up arm changes into separate patches
> - work around Clang section generation bug in -mbranch-protection
> - work around Clang sec
On Fri, Aug 21, 2020 at 02:27:05PM +0200, Ard Biesheuvel wrote:
> On Fri, 21 Aug 2020 at 14:20, Will Deacon wrote:
> >
> > On Thu, Aug 13, 2020 at 03:07:13PM +0200, Ard Biesheuvel wrote:
> > > On Thu, 13 Aug 2020 at 15:04, Jessica Yu wrote:
> > > >
> &
On Thu, Aug 13, 2020 at 03:07:13PM +0200, Ard Biesheuvel wrote:
> On Thu, 13 Aug 2020 at 15:04, Jessica Yu wrote:
> >
> > +++ Ard Biesheuvel [13/08/20 10:36 +0200]:
> > >On Wed, 12 Aug 2020 at 22:00, Peter Zijlstra wrote:
> > >>
> > >> On Wed, Aug 12, 2020 at 06:37:57PM +0200, Ard Biesheuvel wrot
> not _save()
>
> Signed-off-by: Marta Rybczynska
> ---
> Documentation/locking/locktypes.rst | 24
> 1 file changed, 12 insertions(+), 12 deletions(-)
Looks correct to me, thanks:
Acked-by: Will Deacon
Will
On Tue, Jul 14, 2020 at 08:48:11AM +, 彭浩(Richard) wrote:
> On Thu, Jul 09, 2020 at 07:18:01AM +,Peng Hao(Richard) wrote:
> > On Thu, 9 Jul 2020 at 09:50, Peng Hao(Richard)
> > wrote:
> > >> >Apparently, you are hitting a R_AARCH64_JUMP26 or R_AARCH64_CALL26
> > >> >relocation that operate
;
> - __add_wait_queue_entry_tail(&sem->waiters, &wq_entry);
> + wq_entry.flags |= reader * WQ_FLAG_CUSTOM;
> + __add_wait_queue_entry_tail_exclusive(&sem->waiters, &wq_entry);
> }
> spin_unlock_irq(&sem->waiters.lock);
Seems straightforward enough:
Acked-by: Will Deacon
Will
at: Add vDSO")
> Signed-off-by: Stephen Boyd
> ---
> arch/arm64/Makefile | 1 +
> arch/arm64/kernel/vdso32/Makefile | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
Acked-by: Will Deacon
Will
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