On 03/09/2015 07:18, Nakajima, Jun wrote:
> On Wed, Sep 2, 2015 at 3:38 PM, Steve Rutherford
> wrote:
>> On Thu, Aug 13, 2015 at 09:31:48AM +0200, Paolo Bonzini wrote:
>> Pinging this thread.
>>
>> Should I put together a patch to make split irqchip work properly with the
>> old TMR behavior?
On Wed, Sep 2, 2015 at 3:38 PM, Steve Rutherford wrote:
> On Thu, Aug 13, 2015 at 09:31:48AM +0200, Paolo Bonzini wrote:
> Pinging this thread.
>
> Should I put together a patch to make split irqchip work properly with the
> old TMR behavior?
Yes, please.
Intel® 64 and IA-32 Architectures Softw
On Thu, Aug 13, 2015 at 09:31:48AM +0200, Paolo Bonzini wrote:
Pinging this thread.
Should I put together a patch to make split irqchip work properly with the old
TMR behavior?
>
>
> On 13/08/2015 08:35, Zhang, Yang Z wrote:
> >> You may be right. It is safe if no future hardware plans to use
On 13/08/2015 08:35, Zhang, Yang Z wrote:
>> You may be right. It is safe if no future hardware plans to use
>> it. Let me check with our hardware team to see whether it will be
>> used or not in future.
>
> After checking with Jun, there is no guarantee that the guest running
> on another CPU w
Zhang, Yang Z wrote on 2015-08-04:
> Paolo Bonzini wrote on 2015-08-04:
>>
>>
>> On 04/08/2015 02:46, Zhang, Yang Z wrote:
It is a problem for split irqchip, where the EOI exit bitmap can
be inferred from the IOAPIC routes but the TMR cannot. The
hardware behavior on the other han
Paolo Bonzini wrote on 2015-08-04:
>
>
> On 04/08/2015 02:46, Zhang, Yang Z wrote:
>>> It is a problem for split irqchip, where the EOI exit bitmap can be
>>> inferred from the IOAPIC routes but the TMR cannot. The hardware
>>> behavior on the other hand can be implemented purely within the LAPI
On 04/08/2015 02:46, Zhang, Yang Z wrote:
> > It is a problem for split irqchip, where the EOI exit bitmap can be
> > inferred from the IOAPIC routes but the TMR cannot. The hardware
> > behavior on the other hand can be implemented purely within the LAPIC.
>
> So updating the TMR within LAPIC
Paolo Bonzini wrote on 2015-08-03:
>
>
> On 03/08/2015 12:23, Zhang, Yang Z wrote:
>>> In any case, the TMR behavior introduced by the APICv patches is
>>> completely different from the hardware behavior, so it has to be fixed.
>>
>> But any real problem with it?
>
> It is a problem for split i
On 03/08/2015 12:23, Zhang, Yang Z wrote:
> > In any case, the TMR behavior introduced by the APICv patches is
> > completely different from the hardware behavior, so it has to be fixed.
>
> But any real problem with it?
It is a problem for split irqchip, where the EOI exit bitmap can be
inferr
Paolo Bonzini wrote on 2015-08-03:
>
>
> On 03/08/2015 04:37, Zhang, Yang Z wrote:
Only virtualized APIC register reads use the virtual TMR
registers (SDM
29.4.2 or 29.5), but these just read data from the corresponding
field in the virtual APIC page.
>>
>> 24.11.4 Software A
On 03/08/2015 04:37, Zhang, Yang Z wrote:
>> > Only virtualized APIC register reads use the virtual TMR registers (SDM
>> > 29.4.2 or 29.5), but these just read data from the corresponding field
>> > in the virtual APIC page.
>
> 24.11.4 Software Access to Related Structures
> In addition to dat
Paolo Bonzini wrote on 2015-07-31:
>
>
> On 31/07/2015 04:49, Steve Rutherford wrote:
>> Oh... Yeah. That's a damn good point, given that the interrupt can be
>> injected from another thread while one is in that guest vcpu.
>>
>> Easiest time to update the TMR should be on guest entry through
>>
Paolo Bonzini wrote on 2015-07-31:
>
>
> On 31/07/2015 01:26, Zhang, Yang Z wrote:
Do not compute TMR in advance. Instead, set the TMR just before
the interrupt is accepted into the IRR. This limits the coupling
between IOAPIC and LAPIC.
>>
>> Uh.., it back to original way which
On 31/07/2015 01:26, Zhang, Yang Z wrote:
>>> Do not compute TMR in advance. Instead, set the TMR just before
>>> the interrupt is accepted into the IRR. This limits the coupling
>>> between IOAPIC and LAPIC.
>
> Uh.., it back to original way which is wrong. You cannot modify the
> apic page(h
On 31/07/2015 04:49, Steve Rutherford wrote:
> Oh... Yeah. That's a damn good point, given that the interrupt can be
> injected from another thread while one is in that guest vcpu.
>
> Easiest time to update the TMR should be on guest entry through
> vcpu_scan_ioapic, as before.
>
> The best wa
On Thu, Jul 30, 2015 at 11:26:28PM +, Zhang, Yang Z wrote:
> Paolo Bonzini wrote on 2015-07-29:
> > Do not compute TMR in advance. Instead, set the TMR just before the
> > interrupt is accepted into the IRR. This limits the coupling between
> > IOAPIC and LAPIC.
> >
>
> Uh.., it back to ori
Paolo Bonzini wrote on 2015-07-29:
> Do not compute TMR in advance. Instead, set the TMR just before the
> interrupt is accepted into the IRR. This limits the coupling between
> IOAPIC and LAPIC.
>
Uh.., it back to original way which is wrong. You cannot modify the apic
page(here is the TMR re
On Wed, Jul 29, 2015 at 03:37:34PM +0200, Paolo Bonzini wrote:
> Do not compute TMR in advance. Instead, set the TMR just before the interrupt
> is accepted into the IRR. This limits the coupling between IOAPIC and LAPIC.
>
> Signed-off-by: Paolo Bonzini
> ---
> arch/x86/kvm/ioapic.c | 9 ++--
Do not compute TMR in advance. Instead, set the TMR just before the interrupt
is accepted into the IRR. This limits the coupling between IOAPIC and LAPIC.
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/ioapic.c | 9 ++---
arch/x86/kvm/ioapic.h | 3 +--
arch/x86/kvm/lapic.c | 19 +
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