Re: [PATCH 2/3] PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)

On Mon, Jul 9, 2012 at 3:21 PM, Bjorn Helgaas wrote: > What bad things would happen if I just appended your patch to the end > of this series? Would that break bisection in some scenario? Should be ok. it should not break bisection. Don't think sizing is working for 1k before. Thanks Yinghai

Re: [PATCH 2/3] PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)

On Mon, Jul 9, 2012 at 3:43 PM, Yinghai Lu wrote: > On Mon, Jul 9, 2012 at 1:32 PM, Bjorn Helgaas wrote: >> >> Note that the bridge window assignment code, e.g., pbus_size_io(), should >> pay attention to dev->io_window_1k, too, but I didn't fix that. > > Please check attached patch that will fix

Re: [PATCH 2/3] PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)

On Mon, Jul 9, 2012 at 1:32 PM, Bjorn Helgaas wrote: > > Note that the bridge window assignment code, e.g., pbus_size_io(), should > pay attention to dev->io_window_1k, too, but I didn't fix that. Please check attached patch that will fix pbus_size_io. You may fold the patch in your patch, or co

[PATCH 2/3] PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)

9d265124d051 and 15a260d53f7c added quirks for P2P bridges that support I/O windows that start/end at 1K boundaries, not just the 4K boundaries defined by the PCI spec. For details, see the IOBL_ADR register and the EN1K bit in the CNF register in the Intel 82870P2 (P64H2). These quirks complicat