On Mon, Mar 26, 2018 at 03:19:48PM -0700, Alison Schofield wrote:
> On Thu, Mar 22, 2018 at 04:30:29PM -0700, Luck, Tony wrote:
> > On Thu, Mar 22, 2018 at 01:49:22PM -0700, Alison Schofield wrote:
> > > + if (!topology_same_node(c, o) &&
> > > + (c->x86_vendor == X86_VENDOR_INTEL &&
> > > +
On Thu, Mar 22, 2018 at 04:30:29PM -0700, Luck, Tony wrote:
> On Thu, Mar 22, 2018 at 01:49:22PM -0700, Alison Schofield wrote:
> > + if (!topology_same_node(c, o) &&
> > + (c->x86_vendor == X86_VENDOR_INTEL &&
> > +c->x86_model == INTEL_FAM6_SKYLAKE_X)) {
>
> Maybe make life easie
On Thu, Mar 22, 2018 at 05:42:41PM -0700, Tim Chen wrote:
> On 03/22/2018 01:49 PM, Alison Schofield wrote:
> >
> > +*/
> > + if (!topology_same_node(c, o) &&
> > + (c->x86_vendor == X86_VENDOR_INTEL &&
> > +c->x86_model == INTEL_FAM6_SKYLAKE_X)) {
> > + /* Use NUMA in
On 03/22/2018 01:49 PM, Alison Schofield wrote:
>
> + */
> + if (!topology_same_node(c, o) &&
> + (c->x86_vendor == X86_VENDOR_INTEL &&
> + c->x86_model == INTEL_FAM6_SKYLAKE_X)) {
> + /* Use NUMA instead of coregroups for scheduling: */
> + x86_has
On 03/22/2018 04:20 PM, Peter Zijlstra wrote:
>> +/*
>> + * Return value doesn't actually matter because we
>> + * are throwing away coregroups for scheduling anyway.
>> + * Return false to bypass topology broken bug messages
>> + * and fi
On Thu, Mar 22, 2018 at 01:49:22PM -0700, Alison Schofield wrote:
> + if (!topology_same_node(c, o) &&
> + (c->x86_vendor == X86_VENDOR_INTEL &&
> + c->x86_model == INTEL_FAM6_SKYLAKE_X)) {
Maybe make life easier in the future to add more models
to the list by using x86_match_
On Thu, Mar 22, 2018 at 01:49:22PM -0700, Alison Schofield wrote:
> + /*
> + * Some Intel CPUs enumerate an LLC that is shared by
> + * multiple NUMA nodes. The LLC on these systems is
> + * shared for off-package data access but private to the
> + * NUMA node (half of the
From: Alison Schofield
Intel's Skylake Server CPUs have a different LLC topology than previous
generations. When in Sub-NUMA-Clustering (SNC) mode, the package is
divided into two "slices", each containing half the cores, half the LLC,
and one memory controller and each slice is enumerated to Lin
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